clk: tegra: Add new fields and PLL types for Tegra114
Tegra114 introduces new PLL types. This requires new clocktypes as well as some new fields in the pll structure. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
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3e72771e21
commit
c1d1939c51
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@ -79,6 +79,48 @@
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#define PLLE_SS_CTRL 0x68
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#define PLLE_SS_DISABLE (7 << 10)
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#define PLLE_AUX_PLLP_SEL BIT(2)
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#define PLLE_AUX_ENABLE_SWCTL BIT(4)
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#define PLLE_AUX_SEQ_ENABLE BIT(24)
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#define PLLE_AUX_PLLRE_SEL BIT(28)
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#define PLLE_MISC_PLLE_PTS BIT(8)
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#define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
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#define PLLE_MISC_IDDQ_SW_CTRL BIT(14)
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#define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
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#define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
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#define PLLE_MISC_VREG_CTRL_SHIFT 2
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#define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT)
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#define PLLCX_MISC_STROBE BIT(31)
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#define PLLCX_MISC_RESET BIT(30)
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#define PLLCX_MISC_SDM_DIV_SHIFT 28
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#define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
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#define PLLCX_MISC_FILT_DIV_SHIFT 26
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#define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
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#define PLLCX_MISC_ALPHA_SHIFT 18
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#define PLLCX_MISC_DIV_LOW_RANGE \
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((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
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(0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
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#define PLLCX_MISC_DIV_HIGH_RANGE \
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((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
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(0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
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#define PLLCX_MISC_COEF_LOW_RANGE \
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((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
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#define PLLCX_MISC_KA_SHIFT 2
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#define PLLCX_MISC_KB_SHIFT 9
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#define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
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(0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
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PLLCX_MISC_DIV_LOW_RANGE | \
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PLLCX_MISC_RESET)
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#define PLLCX_MISC1_DEFAULT 0x000d2308
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#define PLLCX_MISC2_DEFAULT 0x30211200
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#define PLLCX_MISC3_DEFAULT 0x200
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#define PMC_PLLM_WB0_OVERRIDE 0x1dc
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#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
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#define PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK BIT(27)
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#define PMC_SATA_PWRGT 0x1ac
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#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
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#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
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@ -101,6 +143,24 @@
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#define divn_max(p) (divn_mask(p))
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#define divp_max(p) (1 << (divp_mask(p)))
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#ifdef CONFIG_ARCH_TEGRA_114_SOC
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/* PLLXC has 4-bit PDIV, but entry 15 is not allowed in h/w */
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#define PLLXC_PDIV_MAX 14
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/* non-monotonic mapping below is not a typo */
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static u8 pllxc_p[PLLXC_PDIV_MAX + 1] = {
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/* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
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/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32
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};
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#define PLLCX_PDIV_MAX 7
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static u8 pllcx_p[PLLCX_PDIV_MAX + 1] = {
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/* PDIV: 0, 1, 2, 3, 4, 5, 6, 7 */
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/* p: */ 1, 2, 3, 4, 6, 8, 12, 16
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};
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#endif
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static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
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{
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u32 val;
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@ -646,6 +706,520 @@ const struct clk_ops tegra_clk_plle_ops = {
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.enable = clk_plle_enable,
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};
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#ifdef CONFIG_ARCH_TEGRA_114_SOC
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static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
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unsigned long parent_rate)
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{
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if (parent_rate > pll_params->cf_max)
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return 2;
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else
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return 1;
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}
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static int clk_pll_iddq_enable(struct clk_hw *hw)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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unsigned long flags = 0;
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u32 val;
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int ret;
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if (pll->lock)
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spin_lock_irqsave(pll->lock, flags);
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val = pll_readl(pll->params->iddq_reg, pll);
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val &= ~BIT(pll->params->iddq_bit_idx);
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pll_writel(val, pll->params->iddq_reg, pll);
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udelay(2);
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_clk_pll_enable(hw);
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ret = clk_pll_wait_for_lock(pll);
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if (pll->lock)
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spin_unlock_irqrestore(pll->lock, flags);
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return 0;
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}
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static void clk_pll_iddq_disable(struct clk_hw *hw)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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unsigned long flags = 0;
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u32 val;
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if (pll->lock)
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spin_lock_irqsave(pll->lock, flags);
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_clk_pll_disable(hw);
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val = pll_readl(pll->params->iddq_reg, pll);
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val |= BIT(pll->params->iddq_bit_idx);
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pll_writel(val, pll->params->iddq_reg, pll);
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udelay(2);
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if (pll->lock)
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spin_unlock_irqrestore(pll->lock, flags);
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}
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static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
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struct tegra_clk_pll_freq_table *cfg,
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unsigned long rate, unsigned long parent_rate)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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unsigned int p;
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if (!rate)
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return -EINVAL;
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p = DIV_ROUND_UP(pll->params->vco_min, rate);
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cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
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cfg->p = p;
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cfg->output_rate = rate * cfg->p;
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cfg->n = cfg->output_rate * cfg->m / parent_rate;
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if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
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return -EINVAL;
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return 0;
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}
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static int _pll_ramp_calc_pll(struct clk_hw *hw,
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struct tegra_clk_pll_freq_table *cfg,
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unsigned long rate, unsigned long parent_rate)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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int err = 0;
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err = _get_table_rate(hw, cfg, rate, parent_rate);
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if (err < 0)
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err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
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else if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
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WARN_ON(1);
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err = -EINVAL;
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goto out;
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}
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if (!cfg->p || (cfg->p > pll->params->max_p))
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err = -EINVAL;
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out:
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return err;
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}
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static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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struct tegra_clk_pll_freq_table cfg, old_cfg;
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unsigned long flags = 0;
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int ret = 0;
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u8 old_p;
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ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
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if (ret < 0)
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return ret;
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if (pll->lock)
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spin_lock_irqsave(pll->lock, flags);
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_get_pll_mnp(pll, &old_cfg);
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old_p = pllxc_p[old_cfg.p];
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if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_p != cfg.p) {
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cfg.p -= 1;
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ret = _program_pll(hw, &cfg, rate);
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}
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if (pll->lock)
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spin_unlock_irqrestore(pll->lock, flags);
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return ret;
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}
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static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct tegra_clk_pll_freq_table cfg;
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int ret = 0;
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u64 output_rate = *prate;
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ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
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if (ret < 0)
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return ret;
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output_rate *= cfg.n;
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do_div(output_rate, cfg.m * cfg.p);
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return output_rate;
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}
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static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct tegra_clk_pll_freq_table cfg;
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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unsigned long flags = 0;
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int state, ret = 0;
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u32 val;
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if (pll->lock)
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spin_lock_irqsave(pll->lock, flags);
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state = clk_pll_is_enabled(hw);
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if (state) {
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if (rate != clk_get_rate(hw->clk)) {
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pr_err("%s: Cannot change active PLLM\n", __func__);
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ret = -EINVAL;
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goto out;
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}
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goto out;
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}
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ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
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if (ret < 0)
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goto out;
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cfg.p -= 1;
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val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE);
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if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) {
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val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE_2);
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val = cfg.p ? (val | PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK) :
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(val & ~PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK);
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writel_relaxed(val, pll->pmc + PMC_PLLM_WB0_OVERRIDE_2);
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val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE);
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val &= ~(divn_mask(pll) | divm_mask(pll));
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val |= (cfg.m << pll->divm_shift) | (cfg.n << pll->divn_shift);
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writel_relaxed(val, pll->pmc + PMC_PLLM_WB0_OVERRIDE);
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} else
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_update_pll_mnp(pll, &cfg);
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out:
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if (pll->lock)
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spin_unlock_irqrestore(pll->lock, flags);
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return ret;
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}
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static void _pllcx_strobe(struct tegra_clk_pll *pll)
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{
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u32 val;
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val = pll_readl_misc(pll);
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val |= PLLCX_MISC_STROBE;
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pll_writel_misc(val, pll);
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udelay(2);
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val &= ~PLLCX_MISC_STROBE;
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pll_writel_misc(val, pll);
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}
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static int clk_pllc_enable(struct clk_hw *hw)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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u32 val;
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int ret = 0;
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unsigned long flags = 0;
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if (pll->lock)
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spin_lock_irqsave(pll->lock, flags);
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_clk_pll_enable(hw);
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udelay(2);
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val = pll_readl_misc(pll);
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val &= ~PLLCX_MISC_RESET;
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pll_writel_misc(val, pll);
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udelay(2);
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_pllcx_strobe(pll);
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ret = clk_pll_wait_for_lock(pll);
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if (pll->lock)
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spin_unlock_irqrestore(pll->lock, flags);
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return ret;
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}
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static void _clk_pllc_disable(struct clk_hw *hw)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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u32 val;
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_clk_pll_disable(hw);
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val = pll_readl_misc(pll);
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val |= PLLCX_MISC_RESET;
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pll_writel_misc(val, pll);
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udelay(2);
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}
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static void clk_pllc_disable(struct clk_hw *hw)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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unsigned long flags = 0;
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if (pll->lock)
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spin_lock_irqsave(pll->lock, flags);
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_clk_pllc_disable(hw);
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if (pll->lock)
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spin_unlock_irqrestore(pll->lock, flags);
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}
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static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
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unsigned long input_rate, u32 n)
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{
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u32 val, n_threshold;
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switch (input_rate) {
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case 12000000:
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n_threshold = 70;
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break;
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case 13000000:
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case 26000000:
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n_threshold = 71;
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break;
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case 16800000:
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n_threshold = 55;
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break;
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case 19200000:
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n_threshold = 48;
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break;
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default:
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pr_err("%s: Unexpected reference rate %lu\n",
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__func__, input_rate);
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return -EINVAL;
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}
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val = pll_readl_misc(pll);
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val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
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val |= n <= n_threshold ?
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PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
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pll_writel_misc(val, pll);
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return 0;
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}
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static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct tegra_clk_pll_freq_table cfg;
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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unsigned long flags = 0;
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int state, ret = 0;
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u32 val;
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u16 old_m, old_n;
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u8 old_p;
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if (pll->lock)
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spin_lock_irqsave(pll->lock, flags);
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ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
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if (ret < 0)
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goto out;
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val = pll_readl_base(pll);
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old_m = (val >> pll->divm_shift) & (divm_mask(pll));
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old_n = (val >> pll->divn_shift) & (divn_mask(pll));
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old_p = pllcx_p[(val >> pll->divp_shift) & (divp_mask(pll))];
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if (cfg.m != old_m) {
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WARN_ON(1);
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goto out;
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}
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if (old_n == cfg.n && old_p == cfg.p)
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goto out;
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cfg.p -= 1;
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state = clk_pll_is_enabled(hw);
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if (state)
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_clk_pllc_disable(hw);
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ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
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if (ret < 0)
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goto out;
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_update_pll_mnp(pll, &cfg);
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if (state)
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ret = clk_pllc_enable(hw);
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out:
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if (pll->lock)
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spin_unlock_irqrestore(pll->lock, flags);
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return ret;
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}
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static long _pllre_calc_rate(struct tegra_clk_pll *pll,
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struct tegra_clk_pll_freq_table *cfg,
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unsigned long rate, unsigned long parent_rate)
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{
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u16 m, n;
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u64 output_rate = parent_rate;
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m = _pll_fixed_mdiv(pll->params, parent_rate);
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n = rate * m / parent_rate;
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output_rate *= n;
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do_div(output_rate, m);
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if (cfg) {
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cfg->m = m;
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cfg->n = n;
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}
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return output_rate;
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}
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static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct tegra_clk_pll_freq_table cfg, old_cfg;
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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unsigned long flags = 0;
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int state, ret = 0;
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if (pll->lock)
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spin_lock_irqsave(pll->lock, flags);
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_pllre_calc_rate(pll, &cfg, rate, parent_rate);
|
||||
_get_pll_mnp(pll, &old_cfg);
|
||||
cfg.p = old_cfg.p;
|
||||
|
||||
if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
|
||||
state = clk_pll_is_enabled(hw);
|
||||
if (state)
|
||||
_clk_pll_disable(hw);
|
||||
|
||||
_update_pll_mnp(pll, &cfg);
|
||||
|
||||
if (state) {
|
||||
_clk_pll_enable(hw);
|
||||
ret = clk_pll_wait_for_lock(pll);
|
||||
}
|
||||
}
|
||||
|
||||
if (pll->lock)
|
||||
spin_unlock_irqrestore(pll->lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct tegra_clk_pll_freq_table cfg;
|
||||
struct tegra_clk_pll *pll = to_clk_pll(hw);
|
||||
u64 rate = parent_rate;
|
||||
|
||||
_get_pll_mnp(pll, &cfg);
|
||||
|
||||
rate *= cfg.n;
|
||||
do_div(rate, cfg.m);
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
struct tegra_clk_pll *pll = to_clk_pll(hw);
|
||||
|
||||
return _pllre_calc_rate(pll, NULL, rate, *prate);
|
||||
}
|
||||
|
||||
static int clk_plle_tegra114_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct tegra_clk_pll *pll = to_clk_pll(hw);
|
||||
struct tegra_clk_pll_freq_table sel;
|
||||
u32 val;
|
||||
int ret;
|
||||
unsigned long flags = 0;
|
||||
unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
|
||||
|
||||
if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate))
|
||||
return -EINVAL;
|
||||
|
||||
if (pll->lock)
|
||||
spin_lock_irqsave(pll->lock, flags);
|
||||
|
||||
val = pll_readl_base(pll);
|
||||
val &= ~BIT(29); /* Disable lock override */
|
||||
pll_writel_base(val, pll);
|
||||
|
||||
val = pll_readl(pll->params->aux_reg, pll);
|
||||
val |= PLLE_AUX_ENABLE_SWCTL;
|
||||
val &= ~PLLE_AUX_SEQ_ENABLE;
|
||||
pll_writel(val, pll->params->aux_reg, pll);
|
||||
udelay(1);
|
||||
|
||||
val = pll_readl_misc(pll);
|
||||
val |= PLLE_MISC_LOCK_ENABLE;
|
||||
val |= PLLE_MISC_IDDQ_SW_CTRL;
|
||||
val &= ~PLLE_MISC_IDDQ_SW_VALUE;
|
||||
val |= PLLE_MISC_PLLE_PTS;
|
||||
val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
|
||||
pll_writel_misc(val, pll);
|
||||
udelay(5);
|
||||
|
||||
val = pll_readl(PLLE_SS_CTRL, pll);
|
||||
val |= PLLE_SS_DISABLE;
|
||||
pll_writel(val, PLLE_SS_CTRL, pll);
|
||||
|
||||
val = pll_readl_base(pll);
|
||||
val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
|
||||
val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT);
|
||||
val |= sel.m << pll->divm_shift;
|
||||
val |= sel.n << pll->divn_shift;
|
||||
val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
|
||||
pll_writel_base(val, pll);
|
||||
udelay(1);
|
||||
|
||||
_clk_pll_enable(hw);
|
||||
ret = clk_pll_wait_for_lock(pll);
|
||||
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
/* TODO: enable hw control of xusb brick pll */
|
||||
|
||||
out:
|
||||
if (pll->lock)
|
||||
spin_unlock_irqrestore(pll->lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void clk_plle_tegra114_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct tegra_clk_pll *pll = to_clk_pll(hw);
|
||||
unsigned long flags = 0;
|
||||
u32 val;
|
||||
|
||||
if (pll->lock)
|
||||
spin_lock_irqsave(pll->lock, flags);
|
||||
|
||||
_clk_pll_disable(hw);
|
||||
|
||||
val = pll_readl_misc(pll);
|
||||
val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
|
||||
pll_writel_misc(val, pll);
|
||||
udelay(1);
|
||||
|
||||
if (pll->lock)
|
||||
spin_unlock_irqrestore(pll->lock, flags);
|
||||
}
|
||||
#endif
|
||||
|
||||
static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
|
||||
void __iomem *pmc, unsigned long fixed_rate,
|
||||
struct tegra_clk_pll_params *pll_params, u32 pll_flags,
|
||||
|
@ -741,3 +1315,268 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
|
|||
|
||||
return clk;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_114_SOC
|
||||
const struct clk_ops tegra_clk_pllxc_ops = {
|
||||
.is_enabled = clk_pll_is_enabled,
|
||||
.enable = clk_pll_iddq_enable,
|
||||
.disable = clk_pll_iddq_disable,
|
||||
.recalc_rate = clk_pll_recalc_rate,
|
||||
.round_rate = clk_pll_ramp_round_rate,
|
||||
.set_rate = clk_pllxc_set_rate,
|
||||
};
|
||||
|
||||
const struct clk_ops tegra_clk_pllm_ops = {
|
||||
.is_enabled = clk_pll_is_enabled,
|
||||
.enable = clk_pll_iddq_enable,
|
||||
.disable = clk_pll_iddq_disable,
|
||||
.recalc_rate = clk_pll_recalc_rate,
|
||||
.round_rate = clk_pll_ramp_round_rate,
|
||||
.set_rate = clk_pllm_set_rate,
|
||||
};
|
||||
|
||||
const struct clk_ops tegra_clk_pllc_ops = {
|
||||
.is_enabled = clk_pll_is_enabled,
|
||||
.enable = clk_pllc_enable,
|
||||
.disable = clk_pllc_disable,
|
||||
.recalc_rate = clk_pll_recalc_rate,
|
||||
.round_rate = clk_pll_ramp_round_rate,
|
||||
.set_rate = clk_pllc_set_rate,
|
||||
};
|
||||
|
||||
const struct clk_ops tegra_clk_pllre_ops = {
|
||||
.is_enabled = clk_pll_is_enabled,
|
||||
.enable = clk_pll_iddq_enable,
|
||||
.disable = clk_pll_iddq_disable,
|
||||
.recalc_rate = clk_pllre_recalc_rate,
|
||||
.round_rate = clk_pllre_round_rate,
|
||||
.set_rate = clk_pllre_set_rate,
|
||||
};
|
||||
|
||||
const struct clk_ops tegra_clk_plle_tegra114_ops = {
|
||||
.is_enabled = clk_pll_is_enabled,
|
||||
.enable = clk_plle_tegra114_enable,
|
||||
.disable = clk_plle_tegra114_disable,
|
||||
.recalc_rate = clk_pll_recalc_rate,
|
||||
};
|
||||
|
||||
|
||||
struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
|
||||
void __iomem *clk_base, void __iomem *pmc,
|
||||
unsigned long flags, unsigned long fixed_rate,
|
||||
struct tegra_clk_pll_params *pll_params,
|
||||
u32 pll_flags,
|
||||
struct tegra_clk_pll_freq_table *freq_table,
|
||||
spinlock_t *lock)
|
||||
{
|
||||
struct tegra_clk_pll *pll;
|
||||
struct clk *clk;
|
||||
|
||||
if (!pll_params->pdiv_tohw)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
|
||||
pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
|
||||
freq_table, lock);
|
||||
if (IS_ERR(pll))
|
||||
return ERR_CAST(pll);
|
||||
|
||||
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
|
||||
&tegra_clk_pllxc_ops);
|
||||
if (IS_ERR(clk))
|
||||
kfree(pll);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
|
||||
void __iomem *clk_base, void __iomem *pmc,
|
||||
unsigned long flags, unsigned long fixed_rate,
|
||||
struct tegra_clk_pll_params *pll_params,
|
||||
u32 pll_flags,
|
||||
struct tegra_clk_pll_freq_table *freq_table,
|
||||
spinlock_t *lock, unsigned long parent_rate)
|
||||
{
|
||||
u32 val;
|
||||
struct tegra_clk_pll *pll;
|
||||
struct clk *clk;
|
||||
|
||||
pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
|
||||
pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
|
||||
freq_table, lock);
|
||||
if (IS_ERR(pll))
|
||||
return ERR_CAST(pll);
|
||||
|
||||
/* program minimum rate by default */
|
||||
|
||||
val = pll_readl_base(pll);
|
||||
if (val & PLL_BASE_ENABLE)
|
||||
WARN_ON(val & pll_params->iddq_bit_idx);
|
||||
else {
|
||||
int m;
|
||||
|
||||
m = _pll_fixed_mdiv(pll_params, parent_rate);
|
||||
val = m << PLL_BASE_DIVM_SHIFT;
|
||||
val |= (pll_params->vco_min / parent_rate)
|
||||
<< PLL_BASE_DIVN_SHIFT;
|
||||
pll_writel_base(val, pll);
|
||||
}
|
||||
|
||||
/* disable lock override */
|
||||
|
||||
val = pll_readl_misc(pll);
|
||||
val &= ~BIT(29);
|
||||
pll_writel_misc(val, pll);
|
||||
|
||||
pll_flags |= TEGRA_PLL_LOCK_MISC;
|
||||
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
|
||||
&tegra_clk_pllre_ops);
|
||||
if (IS_ERR(clk))
|
||||
kfree(pll);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
|
||||
void __iomem *clk_base, void __iomem *pmc,
|
||||
unsigned long flags, unsigned long fixed_rate,
|
||||
struct tegra_clk_pll_params *pll_params,
|
||||
u32 pll_flags,
|
||||
struct tegra_clk_pll_freq_table *freq_table,
|
||||
spinlock_t *lock)
|
||||
{
|
||||
struct tegra_clk_pll *pll;
|
||||
struct clk *clk;
|
||||
|
||||
if (!pll_params->pdiv_tohw)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
pll_flags |= TEGRA_PLL_BYPASS;
|
||||
pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
|
||||
pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
|
||||
freq_table, lock);
|
||||
if (IS_ERR(pll))
|
||||
return ERR_CAST(pll);
|
||||
|
||||
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
|
||||
&tegra_clk_pllm_ops);
|
||||
if (IS_ERR(clk))
|
||||
kfree(pll);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
|
||||
void __iomem *clk_base, void __iomem *pmc,
|
||||
unsigned long flags, unsigned long fixed_rate,
|
||||
struct tegra_clk_pll_params *pll_params,
|
||||
u32 pll_flags,
|
||||
struct tegra_clk_pll_freq_table *freq_table,
|
||||
spinlock_t *lock)
|
||||
{
|
||||
struct clk *parent, *clk;
|
||||
struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
|
||||
struct tegra_clk_pll *pll;
|
||||
struct tegra_clk_pll_freq_table cfg;
|
||||
unsigned long parent_rate;
|
||||
|
||||
if (!p_tohw)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
parent = __clk_lookup(parent_name);
|
||||
if (IS_ERR(parent)) {
|
||||
WARN(1, "parent clk %s of %s must be registered first\n",
|
||||
name, parent_name);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
pll_flags |= TEGRA_PLL_BYPASS;
|
||||
pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
|
||||
freq_table, lock);
|
||||
if (IS_ERR(pll))
|
||||
return ERR_CAST(pll);
|
||||
|
||||
parent_rate = __clk_get_rate(parent);
|
||||
|
||||
/*
|
||||
* Most of PLLC register fields are shadowed, and can not be read
|
||||
* directly from PLL h/w. Hence, actual PLLC boot state is unknown.
|
||||
* Initialize PLL to default state: disabled, reset; shadow registers
|
||||
* loaded with default parameters; dividers are preset for half of
|
||||
* minimum VCO rate (the latter assured that shadowed divider settings
|
||||
* are within supported range).
|
||||
*/
|
||||
|
||||
cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
|
||||
cfg.n = cfg.m * pll_params->vco_min / parent_rate;
|
||||
|
||||
while (p_tohw->pdiv) {
|
||||
if (p_tohw->pdiv == 2) {
|
||||
cfg.p = p_tohw->hw_val;
|
||||
break;
|
||||
}
|
||||
p_tohw++;
|
||||
}
|
||||
|
||||
if (!p_tohw->pdiv) {
|
||||
WARN_ON(1);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
pll_writel_base(0, pll);
|
||||
_update_pll_mnp(pll, &cfg);
|
||||
|
||||
pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
|
||||
pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
|
||||
pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
|
||||
pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
|
||||
|
||||
_pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
|
||||
|
||||
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
|
||||
&tegra_clk_pllc_ops);
|
||||
if (IS_ERR(clk))
|
||||
kfree(pll);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
struct clk *tegra_clk_register_plle_tegra114(const char *name,
|
||||
const char *parent_name,
|
||||
void __iomem *clk_base, unsigned long flags,
|
||||
unsigned long fixed_rate,
|
||||
struct tegra_clk_pll_params *pll_params,
|
||||
struct tegra_clk_pll_freq_table *freq_table,
|
||||
spinlock_t *lock)
|
||||
{
|
||||
struct tegra_clk_pll *pll;
|
||||
struct clk *clk;
|
||||
u32 val, val_aux;
|
||||
|
||||
pll = _tegra_init_pll(clk_base, NULL, fixed_rate, pll_params,
|
||||
TEGRA_PLL_HAS_LOCK_ENABLE, freq_table, lock);
|
||||
if (IS_ERR(pll))
|
||||
return ERR_CAST(pll);
|
||||
|
||||
/* ensure parent is set to pll_re_vco */
|
||||
|
||||
val = pll_readl_base(pll);
|
||||
val_aux = pll_readl(pll_params->aux_reg, pll);
|
||||
|
||||
if (val & PLL_BASE_ENABLE) {
|
||||
if (!(val_aux & PLLE_AUX_PLLRE_SEL))
|
||||
WARN(1, "pll_e enabled with unsupported parent %s\n",
|
||||
(val & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : "pll_ref");
|
||||
} else {
|
||||
val_aux |= PLLE_AUX_PLLRE_SEL;
|
||||
pll_writel(val, pll_params->aux_reg, pll);
|
||||
}
|
||||
|
||||
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
|
||||
&tegra_clk_plle_tegra114_ops);
|
||||
if (IS_ERR(clk))
|
||||
kfree(pll);
|
||||
|
||||
return clk;
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
/*
|
||||
/*
|
||||
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
|
@ -156,6 +156,13 @@ struct tegra_clk_pll_params {
|
|||
u32 lock_reg;
|
||||
u32 lock_mask;
|
||||
u32 lock_enable_bit_idx;
|
||||
u32 iddq_reg;
|
||||
u32 iddq_bit_idx;
|
||||
u32 aux_reg;
|
||||
u32 dyn_ramp_reg;
|
||||
u32 ext_misc_reg[3];
|
||||
int stepa_shift;
|
||||
int stepb_shift;
|
||||
int lock_delay;
|
||||
int max_p;
|
||||
struct pdiv_map *pdiv_tohw;
|
||||
|
@ -238,12 +245,53 @@ struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
|
|||
unsigned long flags, unsigned long fixed_rate,
|
||||
struct tegra_clk_pll_params *pll_params, u32 pll_flags,
|
||||
struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
|
||||
|
||||
struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
|
||||
void __iomem *clk_base, void __iomem *pmc,
|
||||
unsigned long flags, unsigned long fixed_rate,
|
||||
struct tegra_clk_pll_params *pll_params, u32 pll_flags,
|
||||
struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
|
||||
|
||||
struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
|
||||
void __iomem *clk_base, void __iomem *pmc,
|
||||
unsigned long flags, unsigned long fixed_rate,
|
||||
struct tegra_clk_pll_params *pll_params,
|
||||
u32 pll_flags,
|
||||
struct tegra_clk_pll_freq_table *freq_table,
|
||||
spinlock_t *lock);
|
||||
|
||||
struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
|
||||
void __iomem *clk_base, void __iomem *pmc,
|
||||
unsigned long flags, unsigned long fixed_rate,
|
||||
struct tegra_clk_pll_params *pll_params,
|
||||
u32 pll_flags,
|
||||
struct tegra_clk_pll_freq_table *freq_table,
|
||||
spinlock_t *lock);
|
||||
|
||||
struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
|
||||
void __iomem *clk_base, void __iomem *pmc,
|
||||
unsigned long flags, unsigned long fixed_rate,
|
||||
struct tegra_clk_pll_params *pll_params,
|
||||
u32 pll_flags,
|
||||
struct tegra_clk_pll_freq_table *freq_table,
|
||||
spinlock_t *lock);
|
||||
|
||||
struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
|
||||
void __iomem *clk_base, void __iomem *pmc,
|
||||
unsigned long flags, unsigned long fixed_rate,
|
||||
struct tegra_clk_pll_params *pll_params,
|
||||
u32 pll_flags,
|
||||
struct tegra_clk_pll_freq_table *freq_table,
|
||||
spinlock_t *lock, unsigned long parent_rate);
|
||||
|
||||
struct clk *tegra_clk_register_plle_tegra114(const char *name,
|
||||
const char *parent_name,
|
||||
void __iomem *clk_base, unsigned long flags,
|
||||
unsigned long fixed_rate,
|
||||
struct tegra_clk_pll_params *pll_params,
|
||||
struct tegra_clk_pll_freq_table *freq_table,
|
||||
spinlock_t *lock);
|
||||
|
||||
/**
|
||||
* struct tegra_clk_pll_out - PLL divider down clock
|
||||
*
|
||||
|
|
Loading…
Reference in a new issue