[TG3]: Add PHY workaround for 5755M.
Some PHY trim values need to be fine-tuned on 5755M to be IEEE-compliant. Update version to 3.72. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -68,8 +68,8 @@
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#define DRV_MODULE_NAME "tg3"
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#define PFX DRV_MODULE_NAME ": "
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#define DRV_MODULE_VERSION "3.71"
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#define DRV_MODULE_RELDATE "December 15, 2006"
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#define DRV_MODULE_VERSION "3.72"
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#define DRV_MODULE_RELDATE "January 8, 2007"
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#define TG3_DEF_MAC_MODE 0
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#define TG3_DEF_RX_MODE 0
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@ -1015,7 +1015,12 @@ out:
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else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
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tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
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tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
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if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
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tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
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tg3_writephy(tp, MII_TG3_TEST1,
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MII_TG3_TEST1_TRIM_EN | 0x4);
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} else
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tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
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}
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/* Set Extended packet length bit (bit 14) on all chips that */
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@ -10803,9 +10808,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
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tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
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else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
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if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
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tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
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} else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
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tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
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}
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@ -1658,6 +1658,9 @@
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#define MII_TG3_EPHY_TEST 0x1f /* 5906 PHY register */
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#define MII_TG3_EPHY_SHADOW_EN 0x80
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#define MII_TG3_TEST1 0x1e
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#define MII_TG3_TEST1_TRIM_EN 0x0010
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/* There are two ways to manage the TX descriptors on the tigon3.
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* Either the descriptors are in host DMA'able memory, or they
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* exist only in the cards on-chip SRAM. All 16 send bds are under
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@ -2256,6 +2259,7 @@ struct tg3 {
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#define TG3_FLG2_1SHOT_MSI 0x10000000
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#define TG3_FLG2_PHY_JITTER_BUG 0x20000000
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#define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
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#define TG3_FLG2_PHY_ADJUST_TRIM 0x80000000
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u32 split_mode_max_reqs;
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#define SPLIT_MODE_5704_MAX_REQ 3
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