diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts
index 544a3b93ed41..d3ca42e09c7e 100755
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts
@@ -124,6 +124,19 @@
 	pinctrl-names = "default";
 
 	imx8mm-evk {
+		pinctrl_csi_pwn: csi_pwn_grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19
+			>;
+		};
+
+		pinctrl_csi_rst: csi_rst_grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19
+				MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1	0x59
+			>;
+		};
+
 		pinctrl_fec1: fec1grp {
 			fsl,pins = <
 				MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3
@@ -412,6 +425,16 @@
 	};
 };
 
+&csi1_bridge {
+	fsl,mipi-mode;
+	status = "okay";
+	port {
+		csi1_ep: endpoint {
+			remote-endpoint = <&csi1_mipi_ep>;
+		};
+	};
+};
+
 &i2c1 {
 	clock-frequency = <400000>;
 	pinctrl-names = "default";
@@ -613,6 +636,26 @@
 	};
 };
 
+
+&mipi_csi_1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	port {
+		mipi1_sensor_ep: endpoint1 {
+			remote-endpoint = <&ov5640_mipi1_ep>;
+			data-lanes = <2>;
+			csis-hs-settle = <13>;
+			csis-clk-settle = <2>;
+			csis-wclk;
+		};
+
+		csi1_mipi_ep: endpoint2 {
+			remote-endpoint = <&csi1_ep>;
+		};
+	};
+};
+
 &i2c3 {
 	clock-frequency = <100000>;
 	pinctrl-names = "default";
@@ -647,6 +690,29 @@
 		reg = <0x11>;
 		ak4497,pdn-gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>;
 	};
+
+	ov5640_mipi: ov5640_mipi@3c {
+		compatible = "ovti,ov5640_mipi";
+		reg = <0x3c>;
+		status = "okay";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>;
+		clocks = <&clk IMX8MM_CLK_CLKO1_DIV>;
+		clock-names = "csi_mclk";
+		assigned-clocks = <&clk IMX8MM_CLK_CLKO1_SRC>,
+				  <&clk IMX8MM_CLK_CLKO1_DIV>;
+		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_200M>;
+		assigned-clock-rates = <0>, <25000000>;
+		csi_id = <0>;
+		pwn-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+		mclk = <25000000>;
+		mclk_source = <0>;
+		port {
+			ov5640_mipi1_ep: endpoint {
+				remote-endpoint = <&mipi1_sensor_ep>;
+			};
+		};
+	};
 };
 
 &mu {
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi
index f483f0a9e0b0..28775fe176cc 100755
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi
@@ -166,6 +166,29 @@
 		};
 	};
 
+	csi1_bridge: csi1_bridge@32e20000 {
+		compatible = "fsl,imx8mm-csi", "fsl,imx8mq-csi", "fsl,imx6s-csi";
+		reg = <0x0 0x32e20000 0x0 0x10000>;
+		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MM_CLK_DUMMY>,
+			<&clk IMX8MM_CLK_CSI1_ROOT>,
+			<&clk IMX8MM_CLK_DUMMY>;
+		clock-names = "disp-axi", "csi_mclk", "disp_dcic";
+		status = "disabled";
+	};
+
+	mipi_csi_1: mipi_csi@32e30000 {
+		compatible = "fsl,imx8mm-mipi-csi";
+		reg = <0x0 0x32e30000 0x0 0x1000>;
+		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <333000000>;
+		clocks = <&clk IMX8MM_CLK_CSI1_CORE_DIV>,
+				<&clk IMX8MM_CLK_CSI1_PHY_REF_DIV>;
+		clock-names = "mipi_clk", "phy_clk";
+		bus-width = <4>;
+		status = "disabled";
+	};
+
 	mipi_pd: gpc_power_domain@0 {
 		compatible = "fsl,imx8mm-pm-domain";
 		#power-domain-cells = <0>;