serial: sh-sci: Move private definitions to private header file
Move private register definitions and enums from the public <linux/serial_sci.h> header file to the driver private "sh-sci.h" header file. The common Serial Control Register definitions are left in the public header file, as they're needed to fill in plat_sci_port.scscr on legacy systems not using DT. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>steinar/wifi_calib_4_9_kernel
Geert Uytterhoeven
Greg Kroah-Hartman
parent
f9ce5ccfd9
commit
c27ffc1080
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@ -2,6 +2,82 @@
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#include <linux/io.h>
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#include <linux/gpio.h>
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#define SCI_MAJOR 204
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#define SCI_MINOR_START 8
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/*
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* SCI register subset common for all port types.
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* Not all registers will exist on all parts.
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*/
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enum {
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SCSMR, /* Serial Mode Register */
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SCBRR, /* Bit Rate Register */
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SCSCR, /* Serial Control Register */
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SCxSR, /* Serial Status Register */
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SCFCR, /* FIFO Control Register */
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SCFDR, /* FIFO Data Count Register */
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SCxTDR, /* Transmit (FIFO) Data Register */
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SCxRDR, /* Receive (FIFO) Data Register */
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SCLSR, /* Line Status Register */
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SCTFDR, /* Transmit FIFO Data Count Register */
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SCRFDR, /* Receive FIFO Data Count Register */
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SCSPTR, /* Serial Port Register */
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HSSRR, /* Sampling Rate Register */
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SCIx_NR_REGS,
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};
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/* SCSMR (Serial Mode Register) */
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#define SCSMR_CHR (1 << 6) /* 7-bit Character Length */
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#define SCSMR_PE (1 << 5) /* Parity Enable */
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#define SCSMR_ODD (1 << 4) /* Odd Parity */
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#define SCSMR_STOP (1 << 3) /* Stop Bit Length */
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#define SCSMR_CKS 0x0003 /* Clock Select */
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/* Serial Control Register, SCIFA/SCIFB only bits */
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#define SCSCR_TDRQE (1 << 15) /* Tx Data Transfer Request Enable */
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#define SCSCR_RDRQE (1 << 14) /* Rx Data Transfer Request Enable */
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/* SCxSR (Serial Status Register) on SCI */
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#define SCI_TDRE 0x80 /* Transmit Data Register Empty */
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#define SCI_RDRF 0x40 /* Receive Data Register Full */
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#define SCI_ORER 0x20 /* Overrun Error */
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#define SCI_FER 0x10 /* Framing Error */
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#define SCI_PER 0x08 /* Parity Error */
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#define SCI_TEND 0x04 /* Transmit End */
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#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
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/* SCxSR (Serial Status Register) on SCIF, HSCIF */
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#define SCIF_ER 0x0080 /* Receive Error */
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#define SCIF_TEND 0x0040 /* Transmission End */
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#define SCIF_TDFE 0x0020 /* Transmit FIFO Data Empty */
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#define SCIF_BRK 0x0010 /* Break Detect */
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#define SCIF_FER 0x0008 /* Framing Error */
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#define SCIF_PER 0x0004 /* Parity Error */
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#define SCIF_RDF 0x0002 /* Receive FIFO Data Full */
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#define SCIF_DR 0x0001 /* Receive Data Ready */
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#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
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/* SCFCR (FIFO Control Register) */
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#define SCFCR_MCE 0x0008
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#define SCFCR_TFRST 0x0004
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#define SCFCR_RFRST 0x0002
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#define SCFCR_LOOP (1 << 0) /* Loopback Test */
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/* SCSPTR (Serial Port Register), optional */
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#define SCSPTR_RTSIO (1 << 7) /* Serial Port RTS Pin Input/Output */
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#define SCSPTR_CTSIO (1 << 5) /* Serial Port CTS Pin Input/Output */
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#define SCSPTR_SPB2IO (1 << 1) /* Serial Port Break Input/Output */
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#define SCSPTR_SPB2DT (1 << 0) /* Serial Port Break Data */
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/* HSSRR HSCIF */
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#define HSCIF_SRE 0x8000 /* Sampling Rate Register Enable */
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#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
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#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
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#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
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@ -28,10 +104,3 @@
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# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
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#endif
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/* SCFCR */
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#define SCFCR_RFRST 0x0002
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#define SCFCR_TFRST 0x0004
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#define SCFCR_MCE 0x0008
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#define SCI_MAJOR 204
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#define SCI_MINOR_START 8
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@ -10,13 +10,6 @@
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#define SCIx_NOT_SUPPORTED (-1)
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/* SCSMR (Serial Mode Register) */
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#define SCSMR_CHR (1 << 6) /* 7-bit Character Length */
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#define SCSMR_PE (1 << 5) /* Parity Enable */
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#define SCSMR_ODD (1 << 4) /* Odd Parity */
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#define SCSMR_STOP (1 << 3) /* Stop Bit Length */
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#define SCSMR_CKS 0x0003 /* Clock Select */
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/* Serial Control Register (@ = not supported by all parts) */
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#define SCSCR_TIE (1 << 7) /* Transmit Interrupt Enable */
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#define SCSCR_RIE (1 << 6) /* Receive Interrupt Enable */
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@ -26,43 +19,7 @@
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#define SCSCR_TOIE (1 << 2) /* Timeout Interrupt Enable @ */
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#define SCSCR_CKE1 (1 << 1) /* Clock Enable 1 */
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#define SCSCR_CKE0 (1 << 0) /* Clock Enable 0 */
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/* SCIFA/SCIFB only */
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#define SCSCR_TDRQE (1 << 15) /* Tx Data Transfer Request Enable */
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#define SCSCR_RDRQE (1 << 14) /* Rx Data Transfer Request Enable */
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/* SCxSR (Serial Status Register) on SCI */
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#define SCI_TDRE 0x80 /* Transmit Data Register Empty */
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#define SCI_RDRF 0x40 /* Receive Data Register Full */
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#define SCI_ORER 0x20 /* Overrun Error */
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#define SCI_FER 0x10 /* Framing Error */
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#define SCI_PER 0x08 /* Parity Error */
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#define SCI_TEND 0x04 /* Transmit End */
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#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
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/* SCxSR (Serial Status Register) on SCIF, HSCIF */
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#define SCIF_ER 0x0080 /* Receive Error */
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#define SCIF_TEND 0x0040 /* Transmission End */
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#define SCIF_TDFE 0x0020 /* Transmit FIFO Data Empty */
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#define SCIF_BRK 0x0010 /* Break Detect */
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#define SCIF_FER 0x0008 /* Framing Error */
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#define SCIF_PER 0x0004 /* Parity Error */
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#define SCIF_RDF 0x0002 /* Receive FIFO Data Full */
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#define SCIF_DR 0x0001 /* Receive Data Ready */
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#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
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/* SCFCR (FIFO Control Register) */
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#define SCFCR_LOOP (1 << 0) /* Loopback Test */
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/* SCSPTR (Serial Port Register), optional */
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#define SCSPTR_RTSIO (1 << 7) /* Serial Port RTS Pin Input/Output */
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#define SCSPTR_CTSIO (1 << 5) /* Serial Port CTS Pin Input/Output */
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#define SCSPTR_SPB2IO (1 << 1) /* Serial Port Break Input/Output */
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#define SCSPTR_SPB2DT (1 << 0) /* Serial Port Break Data */
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/* HSSRR HSCIF */
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#define HSCIF_SRE 0x8000 /* Sampling Rate Register Enable */
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enum {
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SCIx_PROBE_REGTYPE,
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@ -82,28 +39,6 @@ enum {
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SCIx_NR_REGTYPES,
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};
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/*
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* SCI register subset common for all port types.
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* Not all registers will exist on all parts.
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*/
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enum {
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SCSMR, /* Serial Mode Register */
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SCBRR, /* Bit Rate Register */
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SCSCR, /* Serial Control Register */
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SCxSR, /* Serial Status Register */
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SCFCR, /* FIFO Control Register */
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SCFDR, /* FIFO Data Count Register */
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SCxTDR, /* Transmit (FIFO) Data Register */
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SCxRDR, /* Receive (FIFO) Data Register */
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SCLSR, /* Line Status Register */
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SCTFDR, /* Transmit FIFO Data Count Register */
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SCRFDR, /* Receive FIFO Data Count Register */
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SCSPTR, /* Serial Port Register */
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HSSRR, /* Sampling Rate Register */
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SCIx_NR_REGS,
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};
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struct device;
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struct plat_sci_port_ops {
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