dmaengine: Mark struct dma_slave_caps kernel-doc correctly, clarify
struct dma_slave_caps documentation omitted the correct kernel-doc opening comment mark. Document byte granularity and interpretation of the src/dst_addr_widths bit flag fields used by struct dma_slave_caps and struct dma_device. Add punctuation to their "directions" member documentations, and cleanup wording of the description. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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@ -404,14 +404,16 @@ enum dma_residue_granularity {
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DMA_RESIDUE_GRANULARITY_BURST = 2,
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};
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/* struct dma_slave_caps - expose capabilities of a slave channel only
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*
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* @src_addr_widths: bit mask of src addr widths the channel supports
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* @dst_addr_widths: bit mask of dstn addr widths the channel supports
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* @directions: bit mask of slave direction the channel supported
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* since the enum dma_transfer_direction is not defined as bits for each
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* type of direction, the dma controller should fill (1 << <TYPE>) and same
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* should be checked by controller as well
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/**
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* struct dma_slave_caps - expose capabilities of a slave channel only
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* @src_addr_widths: bit mask of src addr widths the channel supports.
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* Width is specified in bytes, e.g. for a channel supporting
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* a width of 4 the mask should have BIT(4) set.
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* @dst_addr_widths: bit mask of dst addr widths the channel supports
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* @directions: bit mask of slave directions the channel supports.
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* Since the enum dma_transfer_direction is not defined as bit flag for
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* each type, the dma controller should set BIT(<TYPE>) and same
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* should be checked by controller as well
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* @max_burst: max burst capability per-transfer
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* @cmd_pause: true, if pause and thereby resume is supported
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* @cmd_terminate: true, if terminate cmd is supported
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@ -678,11 +680,13 @@ struct dma_filter {
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* @dev_id: unique device ID
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* @dev: struct device reference for dma mapping api
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* @src_addr_widths: bit mask of src addr widths the device supports
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* Width is specified in bytes, e.g. for a device supporting
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* a width of 4 the mask should have BIT(4) set.
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* @dst_addr_widths: bit mask of dst addr widths the device supports
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* @directions: bit mask of slave direction the device supports since
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* the enum dma_transfer_direction is not defined as bits for
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* each type of direction, the dma controller should fill (1 <<
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* <TYPE>) and same should be checked by controller as well
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* @directions: bit mask of slave directions the device supports.
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* Since the enum dma_transfer_direction is not defined as bit flag for
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* each type, the dma controller should set BIT(<TYPE>) and same
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* should be checked by controller as well
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* @max_burst: max burst capability per-transfer
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* @residue_granularity: granularity of the transfer residue reported
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* by tx_status
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