powerpc/perf: Add lost exception workaround
Some power8 revisions have a hardware bug where we can lose a PMU exception, this commit adds a workaround to detect the bad condition and rectify the situation. See the comment in the commit for a full description. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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@ -670,6 +670,7 @@
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#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
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#define MMCR0_PMCjCE 0x00004000UL /* PMCj count enable*/
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#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
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#define MMCR0_PMAO_SYNC 0x00000800UL /* PMU interrupt is synchronous */
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#define MMCR0_PMAO 0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
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#define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */
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#define MMCR0_FC56 0x00000010UL /* freeze counters 5 and 6 */
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@ -703,6 +704,7 @@
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#define SPRN_EBBHR 804 /* Event based branch handler register */
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#define SPRN_EBBRR 805 /* Event based branch return register */
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#define SPRN_BESCR 806 /* Branch event status and control register */
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#define BESCR_GE 0x8000000000000000ULL /* Global Enable */
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#define SPRN_WORT 895 /* Workload optimization register - thread */
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#define SPRN_PMC1 787
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@ -120,6 +120,7 @@ static inline void power_pmu_bhrb_enable(struct perf_event *event) {}
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static inline void power_pmu_bhrb_disable(struct perf_event *event) {}
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void power_pmu_flush_branch_stack(void) {}
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static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {}
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static void pmao_restore_workaround(bool ebb) { }
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#endif /* CONFIG_PPC32 */
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static bool regs_use_siar(struct pt_regs *regs)
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@ -545,10 +546,18 @@ static unsigned long ebb_switch_in(bool ebb, unsigned long mmcr0)
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/* Enable EBB and read/write to all 6 PMCs for userspace */
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mmcr0 |= MMCR0_EBE | MMCR0_PMCC_U6;
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/* Add any bits from the user reg, FC or PMAO */
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/*
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* Add any bits from the user MMCR0, FC or PMAO. This is compatible
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* with pmao_restore_workaround() because we may add PMAO but we never
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* clear it here.
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*/
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mmcr0 |= current->thread.mmcr0;
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/* Be careful not to set PMXE if userspace had it cleared */
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/*
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* Be careful not to set PMXE if userspace had it cleared. This is also
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* compatible with pmao_restore_workaround() because it has already
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* cleared PMXE and we leave PMAO alone.
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*/
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if (!(current->thread.mmcr0 & MMCR0_PMXE))
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mmcr0 &= ~MMCR0_PMXE;
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@ -559,6 +568,91 @@ static unsigned long ebb_switch_in(bool ebb, unsigned long mmcr0)
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out:
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return mmcr0;
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}
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static void pmao_restore_workaround(bool ebb)
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{
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unsigned pmcs[6];
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if (!cpu_has_feature(CPU_FTR_PMAO_BUG))
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return;
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/*
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* On POWER8E there is a hardware defect which affects the PMU context
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* switch logic, ie. power_pmu_disable/enable().
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*
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* When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0
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* by the hardware. Sometime later the actual PMU exception is
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* delivered.
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*
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* If we context switch, or simply disable/enable, the PMU prior to the
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* exception arriving, the exception will be lost when we clear PMAO.
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*
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* When we reenable the PMU, we will write the saved MMCR0 with PMAO
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* set, and this _should_ generate an exception. However because of the
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* defect no exception is generated when we write PMAO, and we get
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* stuck with no counters counting but no exception delivered.
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*
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* The workaround is to detect this case and tweak the hardware to
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* create another pending PMU exception.
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*
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* We do that by setting up PMC6 (cycles) for an imminent overflow and
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* enabling the PMU. That causes a new exception to be generated in the
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* chip, but we don't take it yet because we have interrupts hard
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* disabled. We then write back the PMU state as we want it to be seen
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* by the exception handler. When we reenable interrupts the exception
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* handler will be called and see the correct state.
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*
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* The logic is the same for EBB, except that the exception is gated by
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* us having interrupts hard disabled as well as the fact that we are
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* not in userspace. The exception is finally delivered when we return
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* to userspace.
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*/
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/* Only if PMAO is set and PMAO_SYNC is clear */
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if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO)
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return;
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/* If we're doing EBB, only if BESCR[GE] is set */
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if (ebb && !(current->thread.bescr & BESCR_GE))
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return;
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/*
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* We are already soft-disabled in power_pmu_enable(). We need to hard
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* enable to actually prevent the PMU exception from firing.
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*/
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hard_irq_disable();
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/*
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* This is a bit gross, but we know we're on POWER8E and have 6 PMCs.
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* Using read/write_pmc() in a for loop adds 12 function calls and
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* almost doubles our code size.
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*/
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pmcs[0] = mfspr(SPRN_PMC1);
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pmcs[1] = mfspr(SPRN_PMC2);
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pmcs[2] = mfspr(SPRN_PMC3);
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pmcs[3] = mfspr(SPRN_PMC4);
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pmcs[4] = mfspr(SPRN_PMC5);
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pmcs[5] = mfspr(SPRN_PMC6);
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/* Ensure all freeze bits are unset */
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mtspr(SPRN_MMCR2, 0);
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/* Set up PMC6 to overflow in one cycle */
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mtspr(SPRN_PMC6, 0x7FFFFFFE);
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/* Enable exceptions and unfreeze PMC6 */
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mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO);
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/* Now we need to refreeze and restore the PMCs */
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mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO);
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mtspr(SPRN_PMC1, pmcs[0]);
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mtspr(SPRN_PMC2, pmcs[1]);
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mtspr(SPRN_PMC3, pmcs[2]);
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mtspr(SPRN_PMC4, pmcs[3]);
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mtspr(SPRN_PMC5, pmcs[4]);
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mtspr(SPRN_PMC6, pmcs[5]);
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}
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#endif /* CONFIG_PPC64 */
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static void perf_event_interrupt(struct pt_regs *regs);
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@ -1191,6 +1285,8 @@ static void power_pmu_enable(struct pmu *pmu)
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cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
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out_enable:
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pmao_restore_workaround(ebb);
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mmcr0 = ebb_switch_in(ebb, cpuhw->mmcr[0]);
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mb();
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@ -10,6 +10,8 @@
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* 2 of the License, or (at your option) any later version.
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*/
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#define pr_fmt(fmt) "power8-pmu: " fmt
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#include <linux/kernel.h>
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#include <linux/perf_event.h>
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#include <asm/firmware.h>
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@ -774,6 +776,9 @@ static int __init init_power8_pmu(void)
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/* Tell userspace that EBB is supported */
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cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
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if (cpu_has_feature(CPU_FTR_PMAO_BUG))
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pr_info("PMAO restore workaround active.\n");
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return 0;
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}
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early_initcall(init_power8_pmu);
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