iommu/vt-d: Fix dev iotlb pfsid use
commit 1c48db4492
upstream.
PFSID should be used in the invalidation descriptor for flushing
device IOTLBs on SRIOV VFs.
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Cc: stable@vger.kernel.org
Cc: "Ashok Raj" <ashok.raj@intel.com>
Cc: "Lu Baolu" <baolu.lu@linux.intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
pull/10/head
parent
eb58c40465
commit
c2ea292b13
|
@ -1336,8 +1336,8 @@ void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
|
||||||
qi_submit_sync(&desc, iommu);
|
qi_submit_sync(&desc, iommu);
|
||||||
}
|
}
|
||||||
|
|
||||||
void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,
|
void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
|
||||||
u64 addr, unsigned mask)
|
u16 qdep, u64 addr, unsigned mask)
|
||||||
{
|
{
|
||||||
struct qi_desc desc;
|
struct qi_desc desc;
|
||||||
|
|
||||||
|
@ -1352,7 +1352,7 @@ void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,
|
||||||
qdep = 0;
|
qdep = 0;
|
||||||
|
|
||||||
desc.low = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) |
|
desc.low = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) |
|
||||||
QI_DIOTLB_TYPE;
|
QI_DIOTLB_TYPE | QI_DEV_IOTLB_PFSID(pfsid);
|
||||||
|
|
||||||
qi_submit_sync(&desc, iommu);
|
qi_submit_sync(&desc, iommu);
|
||||||
}
|
}
|
||||||
|
|
|
@ -1503,6 +1503,20 @@ static void iommu_enable_dev_iotlb(struct device_domain_info *info)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
pdev = to_pci_dev(info->dev);
|
pdev = to_pci_dev(info->dev);
|
||||||
|
/* For IOMMU that supports device IOTLB throttling (DIT), we assign
|
||||||
|
* PFSID to the invalidation desc of a VF such that IOMMU HW can gauge
|
||||||
|
* queue depth at PF level. If DIT is not set, PFSID will be treated as
|
||||||
|
* reserved, which should be set to 0.
|
||||||
|
*/
|
||||||
|
if (!ecap_dit(info->iommu->ecap))
|
||||||
|
info->pfsid = 0;
|
||||||
|
else {
|
||||||
|
struct pci_dev *pf_pdev;
|
||||||
|
|
||||||
|
/* pdev will be returned if device is not a vf */
|
||||||
|
pf_pdev = pci_physfn(pdev);
|
||||||
|
info->pfsid = PCI_DEVID(pf_pdev->bus->number, pf_pdev->devfn);
|
||||||
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_INTEL_IOMMU_SVM
|
#ifdef CONFIG_INTEL_IOMMU_SVM
|
||||||
/* The PCIe spec, in its wisdom, declares that the behaviour of
|
/* The PCIe spec, in its wisdom, declares that the behaviour of
|
||||||
|
@ -1568,7 +1582,8 @@ static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
|
||||||
|
|
||||||
sid = info->bus << 8 | info->devfn;
|
sid = info->bus << 8 | info->devfn;
|
||||||
qdep = info->ats_qdep;
|
qdep = info->ats_qdep;
|
||||||
qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
|
qi_flush_dev_iotlb(info->iommu, sid, info->pfsid,
|
||||||
|
qdep, addr, mask);
|
||||||
}
|
}
|
||||||
spin_unlock_irqrestore(&device_domain_lock, flags);
|
spin_unlock_irqrestore(&device_domain_lock, flags);
|
||||||
}
|
}
|
||||||
|
|
|
@ -453,9 +453,8 @@ extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
|
||||||
u8 fm, u64 type);
|
u8 fm, u64 type);
|
||||||
extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
|
extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
|
||||||
unsigned int size_order, u64 type);
|
unsigned int size_order, u64 type);
|
||||||
extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,
|
extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
|
||||||
u64 addr, unsigned mask);
|
u16 qdep, u64 addr, unsigned mask);
|
||||||
|
|
||||||
extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
|
extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
|
||||||
|
|
||||||
extern int dmar_ir_support(void);
|
extern int dmar_ir_support(void);
|
||||||
|
|
Loading…
Reference in New Issue