ARC: SMP failed to boot due to missing IVT setup
Commit 05b016ecf5
"ARC: Setup Vector Table Base in early boot" moved
the Interrupt vector Table setup out of arc_init_IRQ() which is called
for all CPUs, to entry point of boot cpu only, breaking booting of others.
Fix by adding the same to entry point of non-boot CPUs too.
read_arc_build_cfg_regs() printing IVT Base Register didn't help the
casue since it prints a synthetic value if zero which is totally bogus,
so fix that to print the exact Register.
[vgupta: Remove the now stale comment from header of arc_init_IRQ and
also added the commentary for halt-on-reset]
Cc: Gilad Ben-Yossef <gilad@benyossef.com>
Cc: Cc: <stable@vger.kernel.org> #3.11
Signed-off-by: Noam Camus <noamc@ezchip.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -11,7 +11,6 @@
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#include <asm-generic/sections.h>
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extern char _int_vec_base_lds[];
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extern char __arc_dccm_base[];
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extern char __dtb_start[];
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@ -34,6 +34,9 @@ stext:
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; IDENTITY Reg [ 3 2 1 0 ]
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; (cpu-id) ^^^ => Zero for UP ARC700
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; => #Core-ID if SMP (Master 0)
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; Note that non-boot CPUs might not land here if halt-on-reset and
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; instead breath life from @first_lines_of_secondary, but we still
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; need to make sure only boot cpu takes this path.
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GET_CPU_ID r5
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cmp r5, 0
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jnz arc_platform_smp_wait_to_boot
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@ -98,6 +101,8 @@ stext:
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first_lines_of_secondary:
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sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
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; setup per-cpu idle task as "current" on this CPU
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ld r0, [@secondary_idle_tsk]
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SET_CURR_TASK_ON_CPU r0, r1
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@ -24,7 +24,6 @@
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* -Needed for each CPU (hence not foldable into init_IRQ)
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*
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* what it does ?
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* -setup Vector Table Base Reg - in case Linux not linked at 0x8000_0000
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* -Disable all IRQs (on CPU side)
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* -Optionally, setup the High priority Interrupts as Level 2 IRQs
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*/
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@ -47,10 +47,7 @@ void read_arc_build_cfg_regs(void)
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READ_BCR(AUX_IDENTITY, cpu->core);
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cpu->timers = read_aux_reg(ARC_REG_TIMERS_BCR);
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cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
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if (cpu->vec_base == 0)
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cpu->vec_base = (unsigned int)_int_vec_base_lds;
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READ_BCR(ARC_REG_D_UNCACH_BCR, uncached_space);
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cpu->uncached_base = uncached_space.start << 24;
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