ASoC: rt5677: add API to select ASRC clock source
This patch defines an API to select the clock source for specified filters. Signed-off-by: Oder Chiou <oder_chiou@realtek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Oder Chiou
Mark Brown
parent
05a25fd53e
commit
c36aa0a192
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@ -1034,6 +1034,169 @@ static int can_use_asrc(struct snd_soc_dapm_widget *source,
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return 0;
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}
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/**
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* rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
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* @codec: SoC audio codec device.
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* @filter_mask: mask of filters.
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* @clk_src: clock source
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*
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* The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can
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* only support standard 32fs or 64fs i2s format, ASRC should be enabled to
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* support special i2s clock format such as Intel's 100fs(100 * sampling rate).
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* ASRC function will track i2s clock and generate a corresponding system clock
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* for codec. This function provides an API to select the clock source for a
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* set of filters specified by the mask. And the codec driver will turn on ASRC
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* for these filters if ASRC is selected as their clock source.
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*/
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int rt5677_sel_asrc_clk_src(struct snd_soc_codec *codec,
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unsigned int filter_mask, unsigned int clk_src)
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{
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struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
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unsigned int asrc3_mask = 0, asrc3_value = 0;
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unsigned int asrc4_mask = 0, asrc4_value = 0;
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unsigned int asrc5_mask = 0, asrc5_value = 0;
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unsigned int asrc6_mask = 0, asrc6_value = 0;
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unsigned int asrc7_mask = 0, asrc7_value = 0;
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switch (clk_src) {
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case RT5677_CLK_SEL_SYS:
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case RT5677_CLK_SEL_I2S1_ASRC:
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case RT5677_CLK_SEL_I2S2_ASRC:
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case RT5677_CLK_SEL_I2S3_ASRC:
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case RT5677_CLK_SEL_I2S4_ASRC:
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case RT5677_CLK_SEL_I2S5_ASRC:
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case RT5677_CLK_SEL_I2S6_ASRC:
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case RT5677_CLK_SEL_SYS2:
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case RT5677_CLK_SEL_SYS3:
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case RT5677_CLK_SEL_SYS4:
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case RT5677_CLK_SEL_SYS5:
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case RT5677_CLK_SEL_SYS6:
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case RT5677_CLK_SEL_SYS7:
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break;
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default:
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return -EINVAL;
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}
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/* ASRC 3 */
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if (filter_mask & RT5677_DA_STEREO_FILTER) {
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asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK;
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asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK)
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| (clk_src << RT5677_DA_STO_CLK_SEL_SFT);
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}
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if (filter_mask & RT5677_DA_MONO2_L_FILTER) {
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asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK;
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asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK)
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| (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT);
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}
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if (filter_mask & RT5677_DA_MONO2_R_FILTER) {
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asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK;
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asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK)
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| (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT);
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}
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if (asrc3_mask)
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regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
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asrc3_value);
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/* ASRC 4 */
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if (filter_mask & RT5677_DA_MONO3_L_FILTER) {
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asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK;
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asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK)
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| (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT);
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}
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if (filter_mask & RT5677_DA_MONO3_R_FILTER) {
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asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK;
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asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK)
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| (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT);
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}
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if (filter_mask & RT5677_DA_MONO4_L_FILTER) {
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asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK;
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asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK)
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| (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT);
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}
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if (filter_mask & RT5677_DA_MONO4_R_FILTER) {
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asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK;
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asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK)
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| (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT);
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}
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if (asrc4_mask)
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regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
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asrc4_value);
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/* ASRC 5 */
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if (filter_mask & RT5677_AD_STEREO1_FILTER) {
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asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK;
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asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK)
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| (clk_src << RT5677_AD_STO1_CLK_SEL_SFT);
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}
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if (filter_mask & RT5677_AD_STEREO2_FILTER) {
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asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK;
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asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK)
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| (clk_src << RT5677_AD_STO2_CLK_SEL_SFT);
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}
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if (filter_mask & RT5677_AD_STEREO3_FILTER) {
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asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK;
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asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK)
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| (clk_src << RT5677_AD_STO3_CLK_SEL_SFT);
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}
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if (filter_mask & RT5677_AD_STEREO4_FILTER) {
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asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK;
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asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK)
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| (clk_src << RT5677_AD_STO4_CLK_SEL_SFT);
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}
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if (asrc5_mask)
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regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
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asrc5_value);
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/* ASRC 6 */
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if (filter_mask & RT5677_AD_MONO_L_FILTER) {
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asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK;
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asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK)
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| (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT);
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}
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if (filter_mask & RT5677_AD_MONO_R_FILTER) {
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asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK;
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asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK)
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| (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT);
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}
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if (asrc6_mask)
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regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
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asrc6_value);
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/* ASRC 7 */
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if (filter_mask & RT5677_DSP_OB_0_3_FILTER) {
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asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK;
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asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK)
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| (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT);
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}
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if (filter_mask & RT5677_DSP_OB_4_7_FILTER) {
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asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK;
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asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK)
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| (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT);
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}
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if (asrc7_mask)
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regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
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asrc7_value);
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return 0;
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}
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EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src);
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/* Digital Mixer */
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static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
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SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
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@ -1406,6 +1406,46 @@
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#define RT5677_DSP_CLK_SRC_PLL2 (0x0 << 7)
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#define RT5677_DSP_CLK_SRC_BYPASS (0x1 << 7)
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/* ASRC Control 3 (0x85) */
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#define RT5677_DA_STO_CLK_SEL_MASK (0xf << 12)
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#define RT5677_DA_STO_CLK_SEL_SFT 12
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#define RT5677_DA_MONO2L_CLK_SEL_MASK (0xf << 4)
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#define RT5677_DA_MONO2L_CLK_SEL_SFT 4
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#define RT5677_DA_MONO2R_CLK_SEL_MASK (0xf << 0)
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#define RT5677_DA_MONO2R_CLK_SEL_SFT 0
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/* ASRC Control 4 (0x86) */
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#define RT5677_DA_MONO3L_CLK_SEL_MASK (0xf << 12)
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#define RT5677_DA_MONO3L_CLK_SEL_SFT 12
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#define RT5677_DA_MONO3R_CLK_SEL_MASK (0xf << 8)
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#define RT5677_DA_MONO3R_CLK_SEL_SFT 8
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#define RT5677_DA_MONO4L_CLK_SEL_MASK (0xf << 4)
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#define RT5677_DA_MONO4L_CLK_SEL_SFT 4
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#define RT5677_DA_MONO4R_CLK_SEL_MASK (0xf << 0)
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#define RT5677_DA_MONO4R_CLK_SEL_SFT 0
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/* ASRC Control 5 (0x87) */
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#define RT5677_AD_STO1_CLK_SEL_MASK (0xf << 12)
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#define RT5677_AD_STO1_CLK_SEL_SFT 12
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#define RT5677_AD_STO2_CLK_SEL_MASK (0xf << 8)
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#define RT5677_AD_STO2_CLK_SEL_SFT 8
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#define RT5677_AD_STO3_CLK_SEL_MASK (0xf << 4)
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#define RT5677_AD_STO3_CLK_SEL_SFT 4
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#define RT5677_AD_STO4_CLK_SEL_MASK (0xf << 0)
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#define RT5677_AD_STO4_CLK_SEL_SFT 0
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/* ASRC Control 6 (0x88) */
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#define RT5677_AD_MONOL_CLK_SEL_MASK (0xf << 12)
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#define RT5677_AD_MONOL_CLK_SEL_SFT 12
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#define RT5677_AD_MONOR_CLK_SEL_MASK (0xf << 8)
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#define RT5677_AD_MONOR_CLK_SEL_SFT 8
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/* ASRC Control 7 (0x89) */
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#define RT5677_DSP_OB_0_3_CLK_SEL_MASK (0xf << 12)
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#define RT5677_DSP_OB_0_3_CLK_SEL_SFT 12
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#define RT5677_DSP_OB_4_7_CLK_SEL_MASK (0xf << 8)
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#define RT5677_DSP_OB_4_7_CLK_SEL_SFT 8
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/* VAD Function Control 4 (0x9f) */
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#define RT5677_VAD_SRC_MASK (0x7 << 8)
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#define RT5677_VAD_SRC_SFT 8
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@ -1670,6 +1710,42 @@ enum rt5677_type {
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RT5676,
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};
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/* ASRC clock source selection */
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enum {
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RT5677_CLK_SEL_SYS,
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RT5677_CLK_SEL_I2S1_ASRC,
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RT5677_CLK_SEL_I2S2_ASRC,
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RT5677_CLK_SEL_I2S3_ASRC,
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RT5677_CLK_SEL_I2S4_ASRC,
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RT5677_CLK_SEL_I2S5_ASRC,
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RT5677_CLK_SEL_I2S6_ASRC,
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RT5677_CLK_SEL_SYS2,
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RT5677_CLK_SEL_SYS3,
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RT5677_CLK_SEL_SYS4,
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RT5677_CLK_SEL_SYS5,
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RT5677_CLK_SEL_SYS6,
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RT5677_CLK_SEL_SYS7,
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};
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/* filter mask */
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enum {
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RT5677_DA_STEREO_FILTER = 0x1,
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RT5677_DA_MONO2_L_FILTER = (0x1 << 1),
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RT5677_DA_MONO2_R_FILTER = (0x1 << 2),
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RT5677_DA_MONO3_L_FILTER = (0x1 << 3),
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RT5677_DA_MONO3_R_FILTER = (0x1 << 4),
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RT5677_DA_MONO4_L_FILTER = (0x1 << 5),
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RT5677_DA_MONO4_R_FILTER = (0x1 << 6),
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RT5677_AD_STEREO1_FILTER = (0x1 << 7),
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RT5677_AD_STEREO2_FILTER = (0x1 << 8),
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RT5677_AD_STEREO3_FILTER = (0x1 << 9),
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RT5677_AD_STEREO4_FILTER = (0x1 << 10),
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RT5677_AD_MONO_L_FILTER = (0x1 << 11),
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RT5677_AD_MONO_R_FILTER = (0x1 << 12),
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RT5677_DSP_OB_0_3_FILTER = (0x1 << 13),
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RT5677_DSP_OB_4_7_FILTER = (0x1 << 14),
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};
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struct rt5677_priv {
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struct snd_soc_codec *codec;
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struct rt5677_platform_data pdata;
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@ -1696,4 +1772,7 @@ struct rt5677_priv {
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bool is_vref_slow;
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};
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int rt5677_sel_asrc_clk_src(struct snd_soc_codec *codec,
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unsigned int filter_mask, unsigned int clk_src);
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#endif /* __RT5677_H__ */
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