clk: tegra: pllp_out2 divider is int only
The pllp_out2 should be integer only, the fractional bit should always be 0. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -1200,8 +1200,8 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
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/* PLLP_OUT2 */
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clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
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clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
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TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
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&pll_div_lock);
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TEGRA_DIVIDER_ROUND_UP | TEGRA_DIVIDER_INT, 24,
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8, 1, &pll_div_lock);
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clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
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clk_base + PLLP_OUTA, 17, 16,
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CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
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