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clk: tegra: pllp_out2 divider is int only

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The pllp_out2 should be integer only, the fractional bit should always be 0.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Peter De Schrijver 2013-06-05 16:37:17 +03:00 committed by Mike Turquette
parent 053b525f6f
commit c388eee21a
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/tegra/clk-tegra114.c
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@ -1200,8 +1200,8 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
/* PLLP_OUT2 */
clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
&pll_div_lock);
TEGRA_DIVIDER_ROUND_UP | TEGRA_DIVIDER_INT, 24,
8, 1, &pll_div_lock);
clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
clk_base + PLLP_OUTA, 17, 16,
CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,