ath5k: Check EEPROM before tweaking SERDES
* Read PCI-E infos offset from EEPROM and if it points to serdes section (0x40), enable serdes programming (further tweaking of serdes values during attach). This follows Legacy and Sam's HAL sources. Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Acked-by: Bob Copeland <me@bobcopeland.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -252,28 +252,6 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
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goto err_free;
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}
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/*
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* Write PCI-E power save settings
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*/
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if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
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ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
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ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
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/* Shut off RX when elecidle is asserted */
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ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
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ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
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/* TODO: EEPROM work */
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ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
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/* Shut off PLL and CLKREQ active in L1 */
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ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
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/* Preserce other settings */
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ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
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ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
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ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
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/* Reset SERDES to load new settings */
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ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
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mdelay(1);
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}
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/*
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* POST
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*/
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@ -295,6 +273,40 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
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goto err_free;
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}
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/*
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* Write PCI-E power save settings
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*/
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if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
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struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
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ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
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ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
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/* Shut off RX when elecidle is asserted */
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ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
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ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
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/* If serdes programing is enabled, increase PCI-E
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* tx power for systems with long trace from host
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* to minicard connector. */
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if (ee->ee_serdes)
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ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
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else
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ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES);
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/* Shut off PLL and CLKREQ active in L1 */
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ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
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/* Preserve other settings */
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ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
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ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
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ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
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/* Reset SERDES to load new settings */
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ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
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mdelay(1);
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}
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/* Get misc capabilities */
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ret = ath5k_hw_set_capabilities(ah);
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if (ret) {
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@ -167,6 +167,16 @@ ath5k_eeprom_init_header(struct ath5k_hw *ah)
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ee->ee_rfkill_pin = (u8) AR5K_REG_MS(val, AR5K_EEPROM_RFKILL_GPIO_SEL);
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ee->ee_rfkill_pol = val & AR5K_EEPROM_RFKILL_POLARITY ? true : false;
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/* Check if PCIE_OFFSET points to PCIE_SERDES_SECTION
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* and enable serdes programming if needed.
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*
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* XXX: Serdes values seem to be fixed so
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* no need to read them here, we write them
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* during ath5k_hw_attach */
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AR5K_EEPROM_READ(AR5K_EEPROM_PCIE_OFFSET, val);
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ee->ee_serdes = (val == AR5K_EEPROM_PCIE_SERDES_SECTION) ?
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true : false;
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return 0;
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}
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@ -19,6 +19,9 @@
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/*
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* Common ar5xxx EEPROM data offsets (set these on AR5K_EEPROM_BASE)
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*/
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#define AR5K_EEPROM_PCIE_OFFSET 0x02 /* Contains offset to PCI-E infos */
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#define AR5K_EEPROM_PCIE_SERDES_SECTION 0x40 /* PCIE_OFFSET points here when
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* SERDES infos are present */
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#define AR5K_EEPROM_MAGIC 0x003d /* EEPROM Magic number */
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#define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 /* Default - found on EEPROM */
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#define AR5K_EEPROM_MAGIC_5212 0x0000145c /* 5212 */
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@ -391,6 +394,7 @@ struct ath5k_eeprom_info {
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u8 ee_rfkill_pin;
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bool ee_rfkill_pol;
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bool ee_is_hb63;
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bool ee_serdes;
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u16 ee_misc0;
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u16 ee_misc1;
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u16 ee_misc2;
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