ACPICA: Clear PM register write-only bits on reading
Affects PM1 Control register only. When reading the register, zero the write-only bits as per the ACPI spec. ACPICA BZ 443. Lin Ming. http://www.acpica.org/bugzilla/show_bug.cgi?id=443 Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
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@ -781,6 +781,10 @@ struct acpi_bit_register_info {
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*/
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#define ACPI_PM1_STATUS_PRESERVED_BITS 0x0800 /* Bit 11 */
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/* Write-only bits must be zeroed by software */
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#define ACPI_PM1_CONTROL_WRITEONLY_BITS 0x2004 /* Bits 13, 2 */
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/* For control registers, both ignored and reserved bits must be preserved */
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#define ACPI_PM1_CONTROL_IGNORED_BITS 0x0201 /* Bits 9, 0(SCI_EN) */
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@ -207,6 +207,13 @@ acpi_hw_register_read(u32 register_id, u32 * return_value)
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xpm1a_control_block,
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&acpi_gbl_FADT.
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xpm1b_control_block);
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/*
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* Zero the write-only bits. From the ACPI specification, "Hardware
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* Write-Only Bits": "Upon reads to registers with write-only bits,
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* software masks out all write-only bits."
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*/
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value &= ~ACPI_PM1_CONTROL_WRITEONLY_BITS;
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break;
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case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
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