EDAC, altera: Add Altera L2 cache and OCRAM support
Add L2 Cache and On-Chip RAM EDAC support for the Altera SoCs. The SDRAM controller is using the Memory Controller model. Each type of ECC is individually configurable. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Cc: devicetree@vger.kernel.org Cc: dinguyen@opensource.altera.com Cc: galak@codeaurora.org Cc: grant.likely@linaro.org Cc: ijc+devicetree@hellion.org.uk Cc: linux-arm-kernel@lists.infradead.org Cc: linux@arm.linux.org.uk Cc: linux-doc@vger.kernel.org Cc: linux-edac <linux-edac@vger.kernel.org> Cc: mark.rutland@arm.com Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com> Cc: pawel.moll@arm.com Cc: robh+dt@kernel.org Link: http://lkml.kernel.org/r/1455132384-17108-1-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov <bp@suse.de>steinar/wifi_calib_4_9_kernel
Thor Thayer
Borislav Petkov
parent
9bf4f00567
commit
c3eea1942a
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@ -367,14 +367,30 @@ config EDAC_OCTEON_PCI
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Support for error detection and correction on the
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Cavium Octeon family of SOCs.
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config EDAC_ALTERA_MC
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bool "Altera SDRAM Memory Controller EDAC"
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config EDAC_ALTERA
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bool "Altera SOCFPGA ECC"
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depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA
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help
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Support for error detection and correction on the
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Altera SDRAM memory controller. Note that the
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preloader must initialize the SDRAM before loading
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the kernel.
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Altera SOCs. This must be selected for SDRAM ECC.
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Note that the preloader must initialize the SDRAM
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before loading the kernel.
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config EDAC_ALTERA_L2C
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bool "Altera L2 Cache ECC"
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depends on EDAC_ALTERA=y
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select CACHE_L2X0
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help
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Support for error detection and correction on the
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Altera L2 cache Memory for Altera SoCs. This option
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requires L2 cache so it will force that selection.
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config EDAC_ALTERA_OCRAM
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bool "Altera On-Chip RAM ECC"
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depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
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help
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Support for error detection and correction on the
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Altera On-Chip RAM Memory for Altera SoCs.
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config EDAC_SYNOPSYS
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tristate "Synopsys DDR Memory Controller"
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@ -67,6 +67,6 @@ obj-$(CONFIG_EDAC_OCTEON_L2C) += octeon_edac-l2c.o
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obj-$(CONFIG_EDAC_OCTEON_LMC) += octeon_edac-lmc.o
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obj-$(CONFIG_EDAC_OCTEON_PCI) += octeon_edac-pci.o
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obj-$(CONFIG_EDAC_ALTERA_MC) += altera_edac.o
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obj-$(CONFIG_EDAC_ALTERA) += altera_edac.o
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obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o
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obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o
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@ -1,5 +1,5 @@
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/*
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* Copyright Altera Corporation (C) 2014-2015. All rights reserved.
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* Copyright Altera Corporation (C) 2014-2016. All rights reserved.
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* Copyright 2011-2012 Calxeda, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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@ -17,8 +17,10 @@
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* Adapted from the highbank_mc_edac driver.
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*/
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#include <asm/cacheflush.h>
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#include <linux/ctype.h>
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#include <linux/edac.h>
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#include <linux/genalloc.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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@ -34,6 +36,7 @@
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#define EDAC_MOD_STR "altera_edac"
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#define EDAC_VERSION "1"
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#define EDAC_DEVICE "Altera"
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static const struct altr_sdram_prv_data c5_data = {
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.ecc_ctrl_offset = CV_CTLCFG_OFST,
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@ -75,6 +78,31 @@ static const struct altr_sdram_prv_data a10_data = {
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.ue_set_mask = A10_DIAGINT_TDERRA_MASK,
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};
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/************************** EDAC Device Defines **************************/
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/* OCRAM ECC Management Group Defines */
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#define ALTR_MAN_GRP_OCRAM_ECC_OFFSET 0x04
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#define ALTR_OCR_ECC_EN BIT(0)
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#define ALTR_OCR_ECC_INJS BIT(1)
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#define ALTR_OCR_ECC_INJD BIT(2)
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#define ALTR_OCR_ECC_SERR BIT(3)
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#define ALTR_OCR_ECC_DERR BIT(4)
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/* L2 ECC Management Group Defines */
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#define ALTR_MAN_GRP_L2_ECC_OFFSET 0x00
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#define ALTR_L2_ECC_EN BIT(0)
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#define ALTR_L2_ECC_INJS BIT(1)
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#define ALTR_L2_ECC_INJD BIT(2)
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#define ALTR_UE_TRIGGER_CHAR 'U' /* Trigger for UE */
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#define ALTR_TRIGGER_READ_WRD_CNT 32 /* Line size x 4 */
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#define ALTR_TRIG_OCRAM_BYTE_SIZE 128 /* Line size x 4 */
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#define ALTR_TRIG_L2C_BYTE_SIZE 4096 /* Full Page */
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/*********************** EDAC Memory Controller Functions ****************/
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/* The SDRAM controller uses the EDAC Memory Controller framework. */
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static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
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{
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struct mem_ctl_info *mci = dev_id;
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@ -504,6 +532,466 @@ static struct platform_driver altr_sdram_edac_driver = {
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module_platform_driver(altr_sdram_edac_driver);
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/************************* EDAC Parent Probe *************************/
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static const struct of_device_id altr_edac_device_of_match[];
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static const struct of_device_id altr_edac_of_match[] = {
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{ .compatible = "altr,socfpga-ecc-manager" },
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{},
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};
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MODULE_DEVICE_TABLE(of, altr_edac_of_match);
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static int altr_edac_probe(struct platform_device *pdev)
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{
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of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match,
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NULL, &pdev->dev);
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return 0;
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}
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static struct platform_driver altr_edac_driver = {
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.probe = altr_edac_probe,
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.driver = {
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.name = "socfpga_ecc_manager",
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.of_match_table = altr_edac_of_match,
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},
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};
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module_platform_driver(altr_edac_driver);
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/************************* EDAC Device Functions *************************/
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/*
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* EDAC Device Functions (shared between various IPs).
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* The discrete memories use the EDAC Device framework. The probe
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* and error handling functions are very similar between memories
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* so they are shared. The memory allocation and freeing for EDAC
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* trigger testing are different for each memory.
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*/
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const struct edac_device_prv_data ocramecc_data;
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const struct edac_device_prv_data l2ecc_data;
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struct edac_device_prv_data {
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int (*setup)(struct platform_device *pdev, void __iomem *base);
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int ce_clear_mask;
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int ue_clear_mask;
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char dbgfs_name[20];
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void * (*alloc_mem)(size_t size, void **other);
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void (*free_mem)(void *p, size_t size, void *other);
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int ecc_enable_mask;
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int ce_set_mask;
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int ue_set_mask;
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int trig_alloc_sz;
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};
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struct altr_edac_device_dev {
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void __iomem *base;
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int sb_irq;
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int db_irq;
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const struct edac_device_prv_data *data;
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struct dentry *debugfs_dir;
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char *edac_dev_name;
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};
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static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
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{
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irqreturn_t ret_value = IRQ_NONE;
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struct edac_device_ctl_info *dci = dev_id;
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struct altr_edac_device_dev *drvdata = dci->pvt_info;
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const struct edac_device_prv_data *priv = drvdata->data;
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if (irq == drvdata->sb_irq) {
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if (priv->ce_clear_mask)
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writel(priv->ce_clear_mask, drvdata->base);
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edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name);
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ret_value = IRQ_HANDLED;
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} else if (irq == drvdata->db_irq) {
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if (priv->ue_clear_mask)
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writel(priv->ue_clear_mask, drvdata->base);
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edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name);
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panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
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ret_value = IRQ_HANDLED;
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} else {
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WARN_ON(1);
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}
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return ret_value;
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}
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static ssize_t altr_edac_device_trig(struct file *file,
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const char __user *user_buf,
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size_t count, loff_t *ppos)
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{
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u32 *ptemp, i, error_mask;
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int result = 0;
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u8 trig_type;
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unsigned long flags;
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struct edac_device_ctl_info *edac_dci = file->private_data;
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struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
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const struct edac_device_prv_data *priv = drvdata->data;
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void *generic_ptr = edac_dci->dev;
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if (!user_buf || get_user(trig_type, user_buf))
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return -EFAULT;
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if (!priv->alloc_mem)
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return -ENOMEM;
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/*
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* Note that generic_ptr is initialized to the device * but in
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* some alloc_functions, this is overridden and returns data.
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*/
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ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr);
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if (!ptemp) {
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edac_printk(KERN_ERR, EDAC_DEVICE,
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"Inject: Buffer Allocation error\n");
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return -ENOMEM;
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}
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if (trig_type == ALTR_UE_TRIGGER_CHAR)
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error_mask = priv->ue_set_mask;
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else
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error_mask = priv->ce_set_mask;
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edac_printk(KERN_ALERT, EDAC_DEVICE,
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"Trigger Error Mask (0x%X)\n", error_mask);
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local_irq_save(flags);
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/* write ECC corrupted data out. */
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for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) {
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/* Read data so we're in the correct state */
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rmb();
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if (ACCESS_ONCE(ptemp[i]))
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result = -1;
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/* Toggle Error bit (it is latched), leave ECC enabled */
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writel(error_mask, drvdata->base);
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writel(priv->ecc_enable_mask, drvdata->base);
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ptemp[i] = i;
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}
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/* Ensure it has been written out */
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wmb();
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local_irq_restore(flags);
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if (result)
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edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n");
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/* Read out written data. ECC error caused here */
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for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++)
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if (ACCESS_ONCE(ptemp[i]) != i)
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edac_printk(KERN_ERR, EDAC_DEVICE,
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"Read doesn't match written data\n");
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if (priv->free_mem)
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priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr);
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return count;
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}
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static const struct file_operations altr_edac_device_inject_fops = {
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.open = simple_open,
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.write = altr_edac_device_trig,
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.llseek = generic_file_llseek,
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};
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static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci,
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const struct edac_device_prv_data *priv)
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{
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struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
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if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
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return;
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drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name);
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if (!drvdata->debugfs_dir)
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return;
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if (!edac_debugfs_create_file(priv->dbgfs_name, S_IWUSR,
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drvdata->debugfs_dir, edac_dci,
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&altr_edac_device_inject_fops))
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debugfs_remove_recursive(drvdata->debugfs_dir);
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}
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static const struct of_device_id altr_edac_device_of_match[] = {
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#ifdef CONFIG_EDAC_ALTERA_L2C
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{ .compatible = "altr,socfpga-l2-ecc", .data = (void *)&l2ecc_data },
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#endif
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#ifdef CONFIG_EDAC_ALTERA_OCRAM
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{ .compatible = "altr,socfpga-ocram-ecc",
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.data = (void *)&ocramecc_data },
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#endif
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{},
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};
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MODULE_DEVICE_TABLE(of, altr_edac_device_of_match);
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/*
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* altr_edac_device_probe()
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* This is a generic EDAC device driver that will support
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* various Altera memory devices such as the L2 cache ECC and
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* OCRAM ECC as well as the memories for other peripherals.
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* Module specific initialization is done by passing the
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* function index in the device tree.
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*/
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static int altr_edac_device_probe(struct platform_device *pdev)
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{
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struct edac_device_ctl_info *dci;
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struct altr_edac_device_dev *drvdata;
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struct resource *r;
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int res = 0;
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struct device_node *np = pdev->dev.of_node;
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char *ecc_name = (char *)np->name;
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static int dev_instance;
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if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
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edac_printk(KERN_ERR, EDAC_DEVICE,
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"Unable to open devm\n");
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return -ENOMEM;
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}
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r) {
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edac_printk(KERN_ERR, EDAC_DEVICE,
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"Unable to get mem resource\n");
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res = -ENODEV;
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goto fail;
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}
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if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
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dev_name(&pdev->dev))) {
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edac_printk(KERN_ERR, EDAC_DEVICE,
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"%s:Error requesting mem region\n", ecc_name);
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res = -EBUSY;
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goto fail;
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}
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dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name,
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1, ecc_name, 1, 0, NULL, 0,
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dev_instance++);
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if (!dci) {
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edac_printk(KERN_ERR, EDAC_DEVICE,
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"%s: Unable to allocate EDAC device\n", ecc_name);
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res = -ENOMEM;
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goto fail;
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}
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drvdata = dci->pvt_info;
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dci->dev = &pdev->dev;
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platform_set_drvdata(pdev, dci);
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drvdata->edac_dev_name = ecc_name;
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drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
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if (!drvdata->base)
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goto fail1;
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/* Get driver specific data for this EDAC device */
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drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
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/* Check specific dependencies for the module */
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if (drvdata->data->setup) {
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res = drvdata->data->setup(pdev, drvdata->base);
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if (res)
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goto fail1;
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}
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drvdata->sb_irq = platform_get_irq(pdev, 0);
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res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
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altr_edac_device_handler,
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0, dev_name(&pdev->dev), dci);
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if (res)
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goto fail1;
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drvdata->db_irq = platform_get_irq(pdev, 1);
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res = devm_request_irq(&pdev->dev, drvdata->db_irq,
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altr_edac_device_handler,
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0, dev_name(&pdev->dev), dci);
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if (res)
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goto fail1;
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dci->mod_name = "Altera ECC Manager";
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dci->dev_name = drvdata->edac_dev_name;
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res = edac_device_add_device(dci);
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if (res)
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goto fail1;
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altr_create_edacdev_dbgfs(dci, drvdata->data);
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devres_close_group(&pdev->dev, NULL);
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return 0;
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fail1:
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edac_device_free_ctl_info(dci);
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fail:
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devres_release_group(&pdev->dev, NULL);
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edac_printk(KERN_ERR, EDAC_DEVICE,
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"%s:Error setting up EDAC device: %d\n", ecc_name, res);
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return res;
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}
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static int altr_edac_device_remove(struct platform_device *pdev)
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{
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struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
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struct altr_edac_device_dev *drvdata = dci->pvt_info;
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debugfs_remove_recursive(drvdata->debugfs_dir);
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edac_device_del_device(&pdev->dev);
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edac_device_free_ctl_info(dci);
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return 0;
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}
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static struct platform_driver altr_edac_device_driver = {
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.probe = altr_edac_device_probe,
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.remove = altr_edac_device_remove,
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.driver = {
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.name = "altr_edac_device",
|
||||
.of_match_table = altr_edac_device_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(altr_edac_device_driver);
|
||||
|
||||
/*********************** OCRAM EDAC Device Functions *********************/
|
||||
|
||||
#ifdef CONFIG_EDAC_ALTERA_OCRAM
|
||||
|
||||
static void *ocram_alloc_mem(size_t size, void **other)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct gen_pool *gp;
|
||||
void *sram_addr;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc");
|
||||
if (!np)
|
||||
return NULL;
|
||||
|
||||
gp = of_gen_pool_get(np, "iram", 0);
|
||||
of_node_put(np);
|
||||
if (!gp)
|
||||
return NULL;
|
||||
|
||||
sram_addr = (void *)gen_pool_alloc(gp, size);
|
||||
if (!sram_addr)
|
||||
return NULL;
|
||||
|
||||
memset(sram_addr, 0, size);
|
||||
/* Ensure data is written out */
|
||||
wmb();
|
||||
|
||||
/* Remember this handle for freeing later */
|
||||
*other = gp;
|
||||
|
||||
return sram_addr;
|
||||
}
|
||||
|
||||
static void ocram_free_mem(void *p, size_t size, void *other)
|
||||
{
|
||||
gen_pool_free((struct gen_pool *)other, (u32)p, size);
|
||||
}
|
||||
|
||||
/*
|
||||
* altr_ocram_check_deps()
|
||||
* Test for OCRAM cache ECC dependencies upon entry because
|
||||
* platform specific startup should have initialized the
|
||||
* On-Chip RAM memory and enabled the ECC.
|
||||
* Can't turn on ECC here because accessing un-initialized
|
||||
* memory will cause CE/UE errors possibly causing an ABORT.
|
||||
*/
|
||||
static int altr_ocram_check_deps(struct platform_device *pdev,
|
||||
void __iomem *base)
|
||||
{
|
||||
if (readl(base) & ALTR_OCR_ECC_EN)
|
||||
return 0;
|
||||
|
||||
edac_printk(KERN_ERR, EDAC_DEVICE,
|
||||
"OCRAM: No ECC present or ECC disabled.\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
const struct edac_device_prv_data ocramecc_data = {
|
||||
.setup = altr_ocram_check_deps,
|
||||
.ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
|
||||
.ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),
|
||||
.dbgfs_name = "altr_ocram_trigger",
|
||||
.alloc_mem = ocram_alloc_mem,
|
||||
.free_mem = ocram_free_mem,
|
||||
.ecc_enable_mask = ALTR_OCR_ECC_EN,
|
||||
.ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),
|
||||
.ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),
|
||||
.trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE,
|
||||
};
|
||||
|
||||
#endif /* CONFIG_EDAC_ALTERA_OCRAM */
|
||||
|
||||
/********************* L2 Cache EDAC Device Functions ********************/
|
||||
|
||||
#ifdef CONFIG_EDAC_ALTERA_L2C
|
||||
|
||||
static void *l2_alloc_mem(size_t size, void **other)
|
||||
{
|
||||
struct device *dev = *other;
|
||||
void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL);
|
||||
|
||||
if (!ptemp)
|
||||
return NULL;
|
||||
|
||||
/* Make sure everything is written out */
|
||||
wmb();
|
||||
|
||||
/*
|
||||
* Clean all cache levels up to LoC (includes L2)
|
||||
* This ensures the corrupted data is written into
|
||||
* L2 cache for readback test (which causes ECC error).
|
||||
*/
|
||||
flush_cache_all();
|
||||
|
||||
return ptemp;
|
||||
}
|
||||
|
||||
static void l2_free_mem(void *p, size_t size, void *other)
|
||||
{
|
||||
struct device *dev = other;
|
||||
|
||||
if (dev && p)
|
||||
devm_kfree(dev, p);
|
||||
}
|
||||
|
||||
/*
|
||||
* altr_l2_check_deps()
|
||||
* Test for L2 cache ECC dependencies upon entry because
|
||||
* platform specific startup should have initialized the L2
|
||||
* memory and enabled the ECC.
|
||||
* Bail if ECC is not enabled.
|
||||
* Note that L2 Cache Enable is forced at build time.
|
||||
*/
|
||||
static int altr_l2_check_deps(struct platform_device *pdev,
|
||||
void __iomem *base)
|
||||
{
|
||||
if (readl(base) & ALTR_L2_ECC_EN)
|
||||
return 0;
|
||||
|
||||
edac_printk(KERN_ERR, EDAC_DEVICE,
|
||||
"L2: No ECC present, or ECC disabled\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
const struct edac_device_prv_data l2ecc_data = {
|
||||
.setup = altr_l2_check_deps,
|
||||
.ce_clear_mask = 0,
|
||||
.ue_clear_mask = 0,
|
||||
.dbgfs_name = "altr_l2_trigger",
|
||||
.alloc_mem = l2_alloc_mem,
|
||||
.free_mem = l2_free_mem,
|
||||
.ecc_enable_mask = ALTR_L2_ECC_EN,
|
||||
.ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS),
|
||||
.ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD),
|
||||
.trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
|
||||
};
|
||||
|
||||
#endif /* CONFIG_EDAC_ALTERA_L2C */
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_AUTHOR("Thor Thayer");
|
||||
MODULE_DESCRIPTION("EDAC Driver for Altera SDRAM Controller");
|
||||
MODULE_DESCRIPTION("EDAC Driver for Altera Memories");
|
||||
|
|
|
|||
Loading…
Reference in New Issue