intel-iommu: Tidy up iommu->gcmd handling
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
parent
462b60f6cc
commit
c416daa98a
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@ -784,7 +784,6 @@ void dmar_disable_qi(struct intel_iommu *iommu)
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cpu_relax();
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cpu_relax();
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iommu->gcmd &= ~DMA_GCMD_QIE;
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iommu->gcmd &= ~DMA_GCMD_QIE;
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writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
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writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl,
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl,
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@ -798,7 +797,7 @@ end:
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*/
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*/
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static void __dmar_enable_qi(struct intel_iommu *iommu)
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static void __dmar_enable_qi(struct intel_iommu *iommu)
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{
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{
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u32 cmd, sts;
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u32 sts;
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unsigned long flags;
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unsigned long flags;
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struct q_inval *qi = iommu->qi;
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struct q_inval *qi = iommu->qi;
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@ -812,9 +811,8 @@ static void __dmar_enable_qi(struct intel_iommu *iommu)
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dmar_writeq(iommu->reg + DMAR_IQA_REG, virt_to_phys(qi->desc));
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dmar_writeq(iommu->reg + DMAR_IQA_REG, virt_to_phys(qi->desc));
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cmd = iommu->gcmd | DMA_GCMD_QIE;
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iommu->gcmd |= DMA_GCMD_QIE;
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iommu->gcmd |= DMA_GCMD_QIE;
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writel(cmd, iommu->reg + DMAR_GCMD_REG);
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writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
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/* Make sure hardware complete it */
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/* Make sure hardware complete it */
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts);
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts);
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@ -819,7 +819,7 @@ static int iommu_alloc_root_entry(struct intel_iommu *iommu)
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static void iommu_set_root_entry(struct intel_iommu *iommu)
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static void iommu_set_root_entry(struct intel_iommu *iommu)
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{
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{
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void *addr;
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void *addr;
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u32 cmd, sts;
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u32 sts;
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unsigned long flag;
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unsigned long flag;
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addr = iommu->root_entry;
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addr = iommu->root_entry;
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@ -827,12 +827,11 @@ static void iommu_set_root_entry(struct intel_iommu *iommu)
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spin_lock_irqsave(&iommu->register_lock, flag);
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spin_lock_irqsave(&iommu->register_lock, flag);
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dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
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dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
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cmd = iommu->gcmd | DMA_GCMD_SRTP;
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writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
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writel(cmd, iommu->reg + DMAR_GCMD_REG);
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/* Make sure hardware complete it */
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/* Make sure hardware complete it */
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, (sts & DMA_GSTS_RTPS), sts);
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readl, (sts & DMA_GSTS_RTPS), sts);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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}
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@ -844,12 +843,13 @@ static void iommu_flush_write_buffer(struct intel_iommu *iommu)
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if (!rwbf_quirk && !cap_rwbf(iommu->cap))
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if (!rwbf_quirk && !cap_rwbf(iommu->cap))
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return;
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return;
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spin_lock_irqsave(&iommu->register_lock, flag);
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spin_lock_irqsave(&iommu->register_lock, flag);
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writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
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writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
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/* Make sure hardware complete it */
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/* Make sure hardware complete it */
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, (!(val & DMA_GSTS_WBFS)), val);
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readl, (!(val & DMA_GSTS_WBFS)), val);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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}
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@ -995,13 +995,13 @@ static int iommu_enable_translation(struct intel_iommu *iommu)
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unsigned long flags;
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unsigned long flags;
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spin_lock_irqsave(&iommu->register_lock, flags);
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spin_lock_irqsave(&iommu->register_lock, flags);
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writel(iommu->gcmd|DMA_GCMD_TE, iommu->reg + DMAR_GCMD_REG);
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iommu->gcmd |= DMA_GCMD_TE;
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writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
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/* Make sure hardware complete it */
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/* Make sure hardware complete it */
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, (sts & DMA_GSTS_TES), sts);
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readl, (sts & DMA_GSTS_TES), sts);
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iommu->gcmd |= DMA_GCMD_TE;
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spin_unlock_irqrestore(&iommu->register_lock, flags);
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spin_unlock_irqrestore(&iommu->register_lock, flags);
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return 0;
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return 0;
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}
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}
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@ -1017,7 +1017,7 @@ static int iommu_disable_translation(struct intel_iommu *iommu)
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/* Make sure hardware complete it */
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/* Make sure hardware complete it */
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, (!(sts & DMA_GSTS_TES)), sts);
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readl, (!(sts & DMA_GSTS_TES)), sts);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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return 0;
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return 0;
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@ -404,7 +404,7 @@ int free_irte(int irq)
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static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
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static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
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{
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{
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u64 addr;
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u64 addr;
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u32 cmd, sts;
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u32 sts;
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unsigned long flags;
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unsigned long flags;
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addr = virt_to_phys((void *)iommu->ir_table->base);
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addr = virt_to_phys((void *)iommu->ir_table->base);
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@ -415,9 +415,8 @@ static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
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(addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
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(addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
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/* Set interrupt-remapping table pointer */
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/* Set interrupt-remapping table pointer */
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cmd = iommu->gcmd | DMA_GCMD_SIRTP;
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iommu->gcmd |= DMA_GCMD_SIRTP;
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iommu->gcmd |= DMA_GCMD_SIRTP;
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writel(cmd, iommu->reg + DMAR_GCMD_REG);
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writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, (sts & DMA_GSTS_IRTPS), sts);
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readl, (sts & DMA_GSTS_IRTPS), sts);
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@ -427,9 +426,8 @@ static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
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spin_lock_irqsave(&iommu->register_lock, flags);
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spin_lock_irqsave(&iommu->register_lock, flags);
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/* enable comaptiblity format interrupt pass through */
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/* enable comaptiblity format interrupt pass through */
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cmd = iommu->gcmd | DMA_GCMD_CFI;
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iommu->gcmd |= DMA_GCMD_CFI;
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iommu->gcmd |= DMA_GCMD_CFI;
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writel(cmd, iommu->reg + DMAR_GCMD_REG);
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writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, (sts & DMA_GSTS_CFIS), sts);
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readl, (sts & DMA_GSTS_CFIS), sts);
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@ -446,9 +444,8 @@ static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
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spin_lock_irqsave(&iommu->register_lock, flags);
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spin_lock_irqsave(&iommu->register_lock, flags);
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/* Enable interrupt-remapping */
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/* Enable interrupt-remapping */
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cmd = iommu->gcmd | DMA_GCMD_IRE;
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iommu->gcmd |= DMA_GCMD_IRE;
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iommu->gcmd |= DMA_GCMD_IRE;
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writel(cmd, iommu->reg + DMAR_GCMD_REG);
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writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, (sts & DMA_GSTS_IRES), sts);
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readl, (sts & DMA_GSTS_IRES), sts);
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