USB: EHCI: Support controllers with big endian capability regs
The two first HC capability registers (CAPLENGTH and HCIVERSION) are defined as one 8-bit and one 16-bit register. Most HC implementations have selected to treat these registers as part of a 32-bit register, giving the same layout for both big and small endian systems. This patch adds a new quirk, big_endian_capbase, to support controllers with big endian register interfaces that treat HCIVERSION and CAPLENGTH as individual registers. Signed-off-by: Jan Andersson <jan@gaisler.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
parent
2ce2c3ac88
commit
c430131a02
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@ -102,6 +102,9 @@ static struct kgdb_io kgdbdbgp_io_ops;
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#define dbgp_kgdb_mode (0)
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#define dbgp_kgdb_mode (0)
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#endif
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#endif
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/* Local version of HC_LENGTH macro as ehci struct is not available here */
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#define EARLY_HC_LENGTH(p) (0x00ff & (p)) /* bits 7 : 0 */
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/*
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/*
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* USB Packet IDs (PIDs)
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* USB Packet IDs (PIDs)
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*/
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*/
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@ -892,7 +895,7 @@ int __init early_dbgp_init(char *s)
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dbgp_printk("ehci_bar: %p\n", ehci_bar);
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dbgp_printk("ehci_bar: %p\n", ehci_bar);
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ehci_caps = ehci_bar;
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ehci_caps = ehci_bar;
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ehci_regs = ehci_bar + HC_LENGTH(readl(&ehci_caps->hc_capbase));
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ehci_regs = ehci_bar + EARLY_HC_LENGTH(readl(&ehci_caps->hc_capbase));
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ehci_debug = ehci_bar + offset;
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ehci_debug = ehci_bar + offset;
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ehci_dev.bus = bus;
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ehci_dev.bus = bus;
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ehci_dev.slot = slot;
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ehci_dev.slot = slot;
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@ -44,6 +44,7 @@ static int ehci_ath79_init(struct usb_hcd *hcd)
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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struct platform_device *pdev = to_platform_device(hcd->self.controller);
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struct platform_device *pdev = to_platform_device(hcd->self.controller);
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const struct platform_device_id *id;
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const struct platform_device_id *id;
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int hclength;
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int ret;
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int ret;
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id = platform_get_device_id(pdev);
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id = platform_get_device_id(pdev);
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@ -52,21 +53,20 @@ static int ehci_ath79_init(struct usb_hcd *hcd)
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return -EINVAL;
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return -EINVAL;
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}
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}
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hclength = HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
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switch (id->driver_data) {
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switch (id->driver_data) {
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case EHCI_ATH79_IP_V1:
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case EHCI_ATH79_IP_V1:
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ehci->has_synopsys_hc_bug = 1;
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ehci->has_synopsys_hc_bug = 1;
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ehci->caps = hcd->regs;
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ehci->caps = hcd->regs;
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ehci->regs = hcd->regs +
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ehci->regs = hcd->regs + hclength;
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HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
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break;
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break;
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case EHCI_ATH79_IP_V2:
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case EHCI_ATH79_IP_V2:
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hcd->has_tt = 1;
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hcd->has_tt = 1;
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ehci->caps = hcd->regs + 0x100;
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ehci->caps = hcd->regs + 0x100;
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ehci->regs = hcd->regs + 0x100 +
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ehci->regs = hcd->regs + 0x100 + hclength;
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HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
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break;
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break;
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default:
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default:
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@ -56,7 +56,7 @@ static int ehci_atmel_setup(struct usb_hcd *hcd)
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/* registers start at offset 0x0 */
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/* registers start at offset 0x0 */
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ehci->caps = hcd->regs;
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ehci->caps = hcd->regs;
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ehci->regs = hcd->regs +
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ehci->regs = hcd->regs +
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HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
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HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
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dbg_hcs_params(ehci, "reset");
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dbg_hcs_params(ehci, "reset");
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dbg_hcc_params(ehci, "reset");
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dbg_hcc_params(ehci, "reset");
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@ -175,7 +175,8 @@ static int ehci_hcd_au1xxx_drv_probe(struct platform_device *pdev)
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ehci = hcd_to_ehci(hcd);
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ehci = hcd_to_ehci(hcd);
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ehci->caps = hcd->regs;
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ehci->caps = hcd->regs;
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ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase));
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ehci->regs = hcd->regs +
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HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase));
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/* cache this readonly data; minimize chip reads */
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/* cache this readonly data; minimize chip reads */
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ehci->hcs_params = readl(&ehci->caps->hcs_params);
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ehci->hcs_params = readl(&ehci->caps->hcs_params);
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@ -34,7 +34,7 @@ static int cns3xxx_ehci_init(struct usb_hcd *hcd)
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ehci->caps = hcd->regs;
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ehci->caps = hcd->regs;
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ehci->regs = hcd->regs
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ehci->regs = hcd->regs
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+ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
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+ HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
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ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
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ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
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hcd->has_tt = 0;
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hcd->has_tt = 0;
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@ -726,7 +726,7 @@ static ssize_t fill_registers_buffer(struct debug_buffer *buf)
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}
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}
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/* Capability Registers */
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/* Capability Registers */
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i = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
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i = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
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temp = scnprintf (next, size,
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temp = scnprintf (next, size,
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"bus %s, device %s\n"
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"bus %s, device %s\n"
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"%s\n"
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"%s\n"
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@ -324,7 +324,7 @@ static int ehci_fsl_setup(struct usb_hcd *hcd)
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/* EHCI registers start at offset 0x100 */
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/* EHCI registers start at offset 0x100 */
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ehci->caps = hcd->regs + 0x100;
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ehci->caps = hcd->regs + 0x100;
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ehci->regs = hcd->regs + 0x100 +
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ehci->regs = hcd->regs + 0x100 +
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HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
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HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
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dbg_hcs_params(ehci, "reset");
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dbg_hcs_params(ehci, "reset");
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dbg_hcc_params(ehci, "reset");
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dbg_hcc_params(ehci, "reset");
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@ -739,7 +739,7 @@ static int ehci_run (struct usb_hcd *hcd)
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up_write(&ehci_cf_port_reset_rwsem);
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up_write(&ehci_cf_port_reset_rwsem);
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ehci->last_periodic_enable = ktime_get_real();
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ehci->last_periodic_enable = ktime_get_real();
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temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
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temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
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ehci_info (ehci,
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ehci_info (ehci,
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"USB %x.%x started, EHCI %x.%02x%s\n",
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"USB %x.%x started, EHCI %x.%02x%s\n",
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((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
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((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
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@ -23,7 +23,7 @@ static int ixp4xx_ehci_init(struct usb_hcd *hcd)
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ehci->caps = hcd->regs + 0x100;
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ehci->caps = hcd->regs + 0x100;
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ehci->regs = hcd->regs + 0x100
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ehci->regs = hcd->regs + 0x100
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+ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
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+ HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
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ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
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ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
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hcd->has_tt = 1;
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hcd->has_tt = 1;
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@ -41,7 +41,7 @@ static int ehci_msm_reset(struct usb_hcd *hcd)
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ehci->caps = USB_CAPLENGTH;
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ehci->caps = USB_CAPLENGTH;
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ehci->regs = USB_CAPLENGTH +
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ehci->regs = USB_CAPLENGTH +
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HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
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HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
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dbg_hcs_params(ehci, "reset");
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dbg_hcs_params(ehci, "reset");
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dbg_hcc_params(ehci, "reset");
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dbg_hcc_params(ehci, "reset");
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@ -208,7 +208,7 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev)
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/* EHCI registers start at offset 0x100 */
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/* EHCI registers start at offset 0x100 */
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ehci->caps = hcd->regs + 0x100;
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ehci->caps = hcd->regs + 0x100;
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ehci->regs = hcd->regs + 0x100 +
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ehci->regs = hcd->regs + 0x100 +
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HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
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HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
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/* set up the PORTSCx register */
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/* set up the PORTSCx register */
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ehci_writel(ehci, pdata->portsc, &ehci->regs->port_status[0]);
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ehci_writel(ehci, pdata->portsc, &ehci->regs->port_status[0]);
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@ -151,7 +151,7 @@ static int ehci_octeon_drv_probe(struct platform_device *pdev)
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ehci->caps = hcd->regs;
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ehci->caps = hcd->regs;
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ehci->regs = hcd->regs +
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ehci->regs = hcd->regs +
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HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
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HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
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/* cache this readonly data; minimize chip reads */
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/* cache this readonly data; minimize chip reads */
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ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
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ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
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@ -188,7 +188,7 @@ static int ehci_hcd_omap_probe(struct platform_device *pdev)
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/* we know this is the memory we want, no need to ioremap again */
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/* we know this is the memory we want, no need to ioremap again */
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omap_ehci->caps = hcd->regs;
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omap_ehci->caps = hcd->regs;
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omap_ehci->regs = hcd->regs
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omap_ehci->regs = hcd->regs
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+ HC_LENGTH(readl(&omap_ehci->caps->hc_capbase));
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+ HC_LENGTH(ehci, readl(&omap_ehci->caps->hc_capbase));
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dbg_hcs_params(omap_ehci, "reset");
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dbg_hcs_params(omap_ehci, "reset");
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dbg_hcc_params(omap_ehci, "reset");
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dbg_hcc_params(omap_ehci, "reset");
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@ -251,7 +251,7 @@ static int __devinit ehci_orion_drv_probe(struct platform_device *pdev)
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ehci = hcd_to_ehci(hcd);
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ehci = hcd_to_ehci(hcd);
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ehci->caps = hcd->regs + 0x100;
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ehci->caps = hcd->regs + 0x100;
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ehci->regs = hcd->regs + 0x100 +
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ehci->regs = hcd->regs + 0x100 +
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HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
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HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
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ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
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ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
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hcd->has_tt = 1;
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hcd->has_tt = 1;
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ehci->sbrn = 0x20;
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ehci->sbrn = 0x20;
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@ -70,7 +70,7 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
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ehci->caps = hcd->regs;
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ehci->caps = hcd->regs;
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ehci->regs = hcd->regs +
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ehci->regs = hcd->regs +
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HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
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HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
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dbg_hcs_params(ehci, "reset");
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dbg_hcs_params(ehci, "reset");
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dbg_hcc_params(ehci, "reset");
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dbg_hcc_params(ehci, "reset");
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@ -83,7 +83,7 @@ static int ehci_msp_setup(struct usb_hcd *hcd)
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ehci->caps = hcd->regs;
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ehci->caps = hcd->regs;
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ehci->regs = hcd->regs +
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ehci->regs = hcd->regs +
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HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
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HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
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dbg_hcs_params(ehci, "reset");
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dbg_hcs_params(ehci, "reset");
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dbg_hcc_params(ehci, "reset");
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dbg_hcc_params(ehci, "reset");
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@ -179,7 +179,7 @@ static int __devinit ehci_hcd_ppc_of_probe(struct platform_device *op)
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ehci->caps = hcd->regs;
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ehci->caps = hcd->regs;
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ehci->regs = hcd->regs +
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ehci->regs = hcd->regs +
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HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
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HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
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/* cache this readonly data; minimize chip reads */
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/* cache this readonly data; minimize chip reads */
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ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
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ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
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@ -29,7 +29,7 @@ static int ps3_ehci_hc_reset(struct usb_hcd *hcd)
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ehci->big_endian_mmio = 1;
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ehci->big_endian_mmio = 1;
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ehci->caps = hcd->regs;
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ehci->caps = hcd->regs;
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ehci->regs = hcd->regs + HC_LENGTH(ehci_readl(ehci,
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ehci->regs = hcd->regs + HC_LENGTH(ehci, ehci_readl(ehci,
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&ehci->caps->hc_capbase));
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&ehci->caps->hc_capbase));
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dbg_hcs_params(ehci, "reset");
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dbg_hcs_params(ehci, "reset");
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@ -126,7 +126,8 @@ static int s5p_ehci_probe(struct platform_device *pdev)
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ehci = hcd_to_ehci(hcd);
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ehci = hcd_to_ehci(hcd);
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ehci->caps = hcd->regs;
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ehci->caps = hcd->regs;
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ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase));
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ehci->regs = hcd->regs +
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HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase));
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dbg_hcs_params(ehci, "reset");
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dbg_hcs_params(ehci, "reset");
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dbg_hcc_params(ehci, "reset");
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dbg_hcc_params(ehci, "reset");
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@ -23,7 +23,7 @@ static int ehci_sh_reset(struct usb_hcd *hcd)
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int ret;
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int ret;
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ehci->caps = hcd->regs;
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ehci->caps = hcd->regs;
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ehci->regs = hcd->regs + HC_LENGTH(ehci_readl(ehci,
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ehci->regs = hcd->regs + HC_LENGTH(ehci, ehci_readl(ehci,
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&ehci->caps->hc_capbase));
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&ehci->caps->hc_capbase));
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dbg_hcs_params(ehci, "reset");
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dbg_hcs_params(ehci, "reset");
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@ -38,7 +38,7 @@ static int ehci_spear_setup(struct usb_hcd *hcd)
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/* registers start at offset 0x0 */
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/* registers start at offset 0x0 */
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ehci->caps = hcd->regs;
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ehci->caps = hcd->regs;
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ehci->regs = hcd->regs + HC_LENGTH(ehci_readl(ehci,
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ehci->regs = hcd->regs + HC_LENGTH(ehci, ehci_readl(ehci,
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&ehci->caps->hc_capbase));
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&ehci->caps->hc_capbase));
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/* cache this readonly data; minimize chip reads */
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/* cache this readonly data; minimize chip reads */
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ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
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ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
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@ -400,7 +400,7 @@ static int tegra_ehci_setup(struct usb_hcd *hcd)
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/* EHCI registers start at offset 0x100 */
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/* EHCI registers start at offset 0x100 */
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ehci->caps = hcd->regs + 0x100;
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ehci->caps = hcd->regs + 0x100;
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ehci->regs = hcd->regs + 0x100 +
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ehci->regs = hcd->regs + 0x100 +
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HC_LENGTH(readl(&ehci->caps->hc_capbase));
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HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase));
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dbg_hcs_params(ehci, "reset");
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dbg_hcs_params(ehci, "reset");
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dbg_hcc_params(ehci, "reset");
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dbg_hcc_params(ehci, "reset");
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@ -121,7 +121,8 @@ static int vt8500_ehci_drv_probe(struct platform_device *pdev)
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ehci = hcd_to_ehci(hcd);
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ehci = hcd_to_ehci(hcd);
|
||||||
ehci->caps = hcd->regs;
|
ehci->caps = hcd->regs;
|
||||||
ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase));
|
ehci->regs = hcd->regs +
|
||||||
|
HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase));
|
||||||
|
|
||||||
dbg_hcs_params(ehci, "reset");
|
dbg_hcs_params(ehci, "reset");
|
||||||
dbg_hcc_params(ehci, "reset");
|
dbg_hcc_params(ehci, "reset");
|
||||||
|
|
|
@ -57,7 +57,7 @@ static int __devinit usb_w90x900_probe(const struct hc_driver *driver,
|
||||||
ehci = hcd_to_ehci(hcd);
|
ehci = hcd_to_ehci(hcd);
|
||||||
ehci->caps = hcd->regs;
|
ehci->caps = hcd->regs;
|
||||||
ehci->regs = hcd->regs +
|
ehci->regs = hcd->regs +
|
||||||
HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
|
HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
|
||||||
|
|
||||||
/* enable PHY 0,1,the regs only apply to w90p910
|
/* enable PHY 0,1,the regs only apply to w90p910
|
||||||
* 0xA4,0xA8 were offsets of PHY0 and PHY1 controller of
|
* 0xA4,0xA8 were offsets of PHY0 and PHY1 controller of
|
||||||
|
|
|
@ -220,7 +220,7 @@ static int __devinit ehci_hcd_xilinx_of_probe(struct platform_device *op)
|
||||||
*/
|
*/
|
||||||
ehci->caps = hcd->regs + 0x100;
|
ehci->caps = hcd->regs + 0x100;
|
||||||
ehci->regs = hcd->regs + 0x100 +
|
ehci->regs = hcd->regs + 0x100 +
|
||||||
HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
|
HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
|
||||||
|
|
||||||
/* cache this readonly data; minimize chip reads */
|
/* cache this readonly data; minimize chip reads */
|
||||||
ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
|
ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
|
||||||
|
|
|
@ -128,6 +128,7 @@ struct ehci_hcd { /* one per controller */
|
||||||
unsigned has_fsl_port_bug:1; /* FreeScale */
|
unsigned has_fsl_port_bug:1; /* FreeScale */
|
||||||
unsigned big_endian_mmio:1;
|
unsigned big_endian_mmio:1;
|
||||||
unsigned big_endian_desc:1;
|
unsigned big_endian_desc:1;
|
||||||
|
unsigned big_endian_capbase:1;
|
||||||
unsigned has_amcc_usb23:1;
|
unsigned has_amcc_usb23:1;
|
||||||
unsigned need_io_watchdog:1;
|
unsigned need_io_watchdog:1;
|
||||||
unsigned broken_periodic:1;
|
unsigned broken_periodic:1;
|
||||||
|
@ -605,12 +606,18 @@ ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
|
||||||
* This attempts to support either format at compile time without a
|
* This attempts to support either format at compile time without a
|
||||||
* runtime penalty, or both formats with the additional overhead
|
* runtime penalty, or both formats with the additional overhead
|
||||||
* of checking a flag bit.
|
* of checking a flag bit.
|
||||||
|
*
|
||||||
|
* ehci_big_endian_capbase is a special quirk for controllers that
|
||||||
|
* implement the HC capability registers as separate registers and not
|
||||||
|
* as fields of a 32-bit register.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
|
#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
|
||||||
#define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
|
#define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
|
||||||
|
#define ehci_big_endian_capbase(e) ((e)->big_endian_capbase)
|
||||||
#else
|
#else
|
||||||
#define ehci_big_endian_mmio(e) 0
|
#define ehci_big_endian_mmio(e) 0
|
||||||
|
#define ehci_big_endian_capbase(e) 0
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -25,10 +25,15 @@
|
||||||
struct ehci_caps {
|
struct ehci_caps {
|
||||||
/* these fields are specified as 8 and 16 bit registers,
|
/* these fields are specified as 8 and 16 bit registers,
|
||||||
* but some hosts can't perform 8 or 16 bit PCI accesses.
|
* but some hosts can't perform 8 or 16 bit PCI accesses.
|
||||||
|
* some hosts treat caplength and hciversion as parts of a 32-bit
|
||||||
|
* register, others treat them as two separate registers, this
|
||||||
|
* affects the memory map for big endian controllers.
|
||||||
*/
|
*/
|
||||||
u32 hc_capbase;
|
u32 hc_capbase;
|
||||||
#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
|
#define HC_LENGTH(ehci, p) (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
|
||||||
#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
|
(ehci_big_endian_capbase(ehci) ? 24 : 0)))
|
||||||
|
#define HC_VERSION(ehci, p) (0xffff&((p) >> /* bits 31:16 / offset 02h */ \
|
||||||
|
(ehci_big_endian_capbase(ehci) ? 0 : 16)))
|
||||||
u32 hcs_params; /* HCSPARAMS - offset 0x4 */
|
u32 hcs_params; /* HCSPARAMS - offset 0x4 */
|
||||||
#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
|
#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
|
||||||
#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
|
#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
|
||||||
|
|
Loading…
Reference in a new issue