atheros: add common debug printing
ath9k uses this for now, ath9k_htc is expected to re-use this as well. We lave ath5k as is, but it certainly can also be converted later. The ath9k module parameter and debugfs entry is kept. Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
parent
cd9bf68960
commit
c46917bb53
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@ -16,7 +16,15 @@ menuconfig ATH_COMMON
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http://wireless.kernel.org/en/users/Drivers/Atheros
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if ATH_COMMON
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config ATH_DEBUG
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bool "Atheros wireless debugging"
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---help---
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Say Y, if you want to debug atheros wireless drivers.
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Right now only ath9k makes use of this.
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source "drivers/net/wireless/ath/ath5k/Kconfig"
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source "drivers/net/wireless/ath/ath9k/Kconfig"
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source "drivers/net/wireless/ath/ar9170/Kconfig"
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endif
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@ -7,3 +7,5 @@ obj-$(CONFIG_ATH_COMMON) += ath.o
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ath-objs := main.o \
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regd.o \
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hw.o
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ath-$(CONFIG_ATH_DEBUG) += debug.o
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@ -48,11 +48,14 @@ struct ath_ops {
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struct ath_common {
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void *ah;
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struct ieee80211_hw *hw;
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int debug_mask;
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u16 cachelsz;
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u16 curaid;
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u8 macaddr[ETH_ALEN];
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u8 curbssid[ETH_ALEN];
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u8 bssidmask[ETH_ALEN];
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struct ath_regulatory regulatory;
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const struct ath_ops *ops;
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};
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@ -16,6 +16,8 @@ config ATH9K
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If you choose to build a module, it'll be called ath9k.
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if ATH_DEBUG
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config ATH9K_DEBUG
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bool "Atheros ath9k debugging"
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depends on ATH9K
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@ -26,3 +28,5 @@ config ATH9K_DEBUG
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modprobe ath9k debug=0x00000200
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Look in ath9k/debug.h for possible debug masks
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endif # ATH_DEBUG
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@ -40,8 +40,9 @@ static bool ath_ahb_eeprom_read(struct ath_hw *ah, u32 off, u16 *data)
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pdata = (struct ath9k_platform_data *) pdev->dev.platform_data;
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if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
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DPRINTF(ah, ATH_DBG_FATAL,
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"%s: flash read failed, offset %08x is out of range\n",
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ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
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"%s: flash read failed, offset %08x "
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"is out of range\n",
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__func__, off);
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return false;
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}
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@ -31,7 +31,7 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
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}
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}
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DPRINTF(ah, ATH_DBG_ANI,
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ath_print(ath9k_hw_common(ah), ATH_DBG_ANI,
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"No more channel states left. Using channel 0\n");
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return 0;
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@ -41,13 +41,14 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
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enum ath9k_ani_cmd cmd, int param)
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{
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struct ar5416AniState *aniState = ah->curani;
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struct ath_common *common = ath9k_hw_common(ah);
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switch (cmd & ah->ani_function) {
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case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
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u32 level = param;
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if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
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DPRINTF(ah, ATH_DBG_ANI,
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ath_print(common, ATH_DBG_ANI,
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"level out of range (%u > %u)\n",
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level,
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(unsigned)ARRAY_SIZE(ah->totalSizeDesired));
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@ -152,7 +153,7 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
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u32 level = param;
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if (level >= ARRAY_SIZE(firstep)) {
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DPRINTF(ah, ATH_DBG_ANI,
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ath_print(common, ATH_DBG_ANI,
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"level out of range (%u > %u)\n",
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level,
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(unsigned) ARRAY_SIZE(firstep));
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@ -174,11 +175,10 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
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u32 level = param;
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if (level >= ARRAY_SIZE(cycpwrThr1)) {
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DPRINTF(ah, ATH_DBG_ANI,
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ath_print(common, ATH_DBG_ANI,
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"level out of range (%u > %u)\n",
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level,
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(unsigned)
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ARRAY_SIZE(cycpwrThr1));
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(unsigned) ARRAY_SIZE(cycpwrThr1));
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return false;
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}
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REG_RMW_FIELD(ah, AR_PHY_TIMING5,
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@ -194,25 +194,28 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
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case ATH9K_ANI_PRESENT:
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break;
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default:
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DPRINTF(ah, ATH_DBG_ANI,
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ath_print(common, ATH_DBG_ANI,
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"invalid cmd %u\n", cmd);
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return false;
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}
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DPRINTF(ah, ATH_DBG_ANI, "ANI parameters:\n");
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DPRINTF(ah, ATH_DBG_ANI,
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ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
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ath_print(common, ATH_DBG_ANI,
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"noiseImmunityLevel=%d, spurImmunityLevel=%d, "
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"ofdmWeakSigDetectOff=%d\n",
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aniState->noiseImmunityLevel, aniState->spurImmunityLevel,
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aniState->noiseImmunityLevel,
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aniState->spurImmunityLevel,
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!aniState->ofdmWeakSigDetectOff);
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DPRINTF(ah, ATH_DBG_ANI,
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ath_print(common, ATH_DBG_ANI,
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"cckWeakSigThreshold=%d, "
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"firstepLevel=%d, listenTime=%d\n",
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aniState->cckWeakSigThreshold, aniState->firstepLevel,
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aniState->cckWeakSigThreshold,
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aniState->firstepLevel,
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aniState->listenTime);
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DPRINTF(ah, ATH_DBG_ANI,
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ath_print(common, ATH_DBG_ANI,
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"cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
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aniState->cycleCount, aniState->ofdmPhyErrCount,
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aniState->cycleCount,
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aniState->ofdmPhyErrCount,
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aniState->cckPhyErrCount);
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return true;
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@ -231,6 +234,7 @@ static void ath9k_hw_update_mibstats(struct ath_hw *ah,
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static void ath9k_ani_restart(struct ath_hw *ah)
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{
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struct ar5416AniState *aniState;
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struct ath_common *common = ath9k_hw_common(ah);
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if (!DO_ANI(ah))
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return;
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@ -240,7 +244,7 @@ static void ath9k_ani_restart(struct ath_hw *ah)
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if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
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aniState->ofdmPhyErrBase = 0;
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DPRINTF(ah, ATH_DBG_ANI,
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ath_print(common, ATH_DBG_ANI,
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"OFDM Trigger is too high for hw counters\n");
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} else {
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aniState->ofdmPhyErrBase =
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@ -248,13 +252,13 @@ static void ath9k_ani_restart(struct ath_hw *ah)
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}
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if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
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aniState->cckPhyErrBase = 0;
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DPRINTF(ah, ATH_DBG_ANI,
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ath_print(common, ATH_DBG_ANI,
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"CCK Trigger is too high for hw counters\n");
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} else {
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aniState->cckPhyErrBase =
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AR_PHY_COUNTMAX - aniState->cckTrigHigh;
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}
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DPRINTF(ah, ATH_DBG_ANI,
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ath_print(common, ATH_DBG_ANI,
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"Writing ofdmbase=%u cckbase=%u\n",
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aniState->ofdmPhyErrBase,
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aniState->cckPhyErrBase);
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@ -464,6 +468,7 @@ void ath9k_ani_reset(struct ath_hw *ah)
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{
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struct ar5416AniState *aniState;
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struct ath9k_channel *chan = ah->curchan;
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struct ath_common *common = ath9k_hw_common(ah);
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int index;
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if (!DO_ANI(ah))
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@ -475,7 +480,7 @@ void ath9k_ani_reset(struct ath_hw *ah)
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if (DO_ANI(ah) && ah->opmode != NL80211_IFTYPE_STATION
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&& ah->opmode != NL80211_IFTYPE_ADHOC) {
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DPRINTF(ah, ATH_DBG_ANI,
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ath_print(common, ATH_DBG_ANI,
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"Reset ANI state opmode %u\n", ah->opmode);
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ah->stats.ast_ani_reset++;
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@ -543,6 +548,7 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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struct ar5416AniState *aniState;
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struct ath_common *common = ath9k_hw_common(ah);
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int32_t listenTime;
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u32 phyCnt1, phyCnt2;
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u32 ofdmPhyErrCnt, cckPhyErrCnt;
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@ -569,20 +575,22 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
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if (phyCnt1 < aniState->ofdmPhyErrBase ||
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phyCnt2 < aniState->cckPhyErrBase) {
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if (phyCnt1 < aniState->ofdmPhyErrBase) {
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DPRINTF(ah, ATH_DBG_ANI,
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ath_print(common, ATH_DBG_ANI,
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"phyCnt1 0x%x, resetting "
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"counter value to 0x%x\n",
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phyCnt1, aniState->ofdmPhyErrBase);
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phyCnt1,
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aniState->ofdmPhyErrBase);
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REG_WRITE(ah, AR_PHY_ERR_1,
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aniState->ofdmPhyErrBase);
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REG_WRITE(ah, AR_PHY_ERR_MASK_1,
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AR_PHY_ERR_OFDM_TIMING);
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}
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if (phyCnt2 < aniState->cckPhyErrBase) {
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DPRINTF(ah, ATH_DBG_ANI,
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ath_print(common, ATH_DBG_ANI,
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"phyCnt2 0x%x, resetting "
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"counter value to 0x%x\n",
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phyCnt2, aniState->cckPhyErrBase);
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phyCnt2,
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aniState->cckPhyErrBase);
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REG_WRITE(ah, AR_PHY_ERR_2,
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aniState->cckPhyErrBase);
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REG_WRITE(ah, AR_PHY_ERR_MASK_2,
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@ -624,7 +632,9 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
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void ath9k_enable_mib_counters(struct ath_hw *ah)
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{
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DPRINTF(ah, ATH_DBG_ANI, "Enable MIB counters\n");
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struct ath_common *common = ath9k_hw_common(ah);
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ath_print(common, ATH_DBG_ANI, "Enable MIB counters\n");
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ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
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@ -640,7 +650,10 @@ void ath9k_enable_mib_counters(struct ath_hw *ah)
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/* Freeze the MIB counters, get the stats and then clear them */
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void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
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{
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DPRINTF(ah, ATH_DBG_ANI, "Disable MIB counters\n");
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struct ath_common *common = ath9k_hw_common(ah);
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ath_print(common, ATH_DBG_ANI, "Disable MIB counters\n");
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REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
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ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
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REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
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@ -653,6 +666,7 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah,
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u32 *rxf_pcnt,
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u32 *txf_pcnt)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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static u32 cycles, rx_clear, rx_frame, tx_frame;
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u32 good = 1;
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@ -662,7 +676,7 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah,
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u32 cc = REG_READ(ah, AR_CCCNT);
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if (cycles == 0 || cycles > cc) {
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DPRINTF(ah, ATH_DBG_ANI,
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ath_print(common, ATH_DBG_ANI,
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"cycle counter wrap. ExtBusy = 0\n");
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good = 0;
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} else {
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@ -762,9 +776,10 @@ void ath9k_hw_ani_setup(struct ath_hw *ah)
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void ath9k_hw_ani_init(struct ath_hw *ah)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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int i;
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DPRINTF(ah, ATH_DBG_ANI, "Initialize ANI\n");
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ath_print(common, ATH_DBG_ANI, "Initialize ANI\n");
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memset(ah->ani, 0, sizeof(ah->ani));
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for (i = 0; i < ARRAY_SIZE(ah->ani); i++) {
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@ -786,10 +801,10 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
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AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
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}
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DPRINTF(ah, ATH_DBG_ANI,
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ath_print(common, ATH_DBG_ANI,
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"Setting OfdmErrBase = 0x%08x\n",
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ah->ani[0].ofdmPhyErrBase);
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DPRINTF(ah, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
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ath_print(common, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
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ah->ani[0].cckPhyErrBase);
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REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase);
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@ -803,7 +818,7 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
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void ath9k_hw_ani_disable(struct ath_hw *ah)
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{
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DPRINTF(ah, ATH_DBG_ANI, "Disabling ANI\n");
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ath_print(ath9k_hw_common(ah), ATH_DBG_ANI, "Disabling ANI\n");
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ath9k_hw_disable_mib_counters(ah);
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REG_WRITE(ah, AR_PHY_ERR_1, 0);
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@ -26,6 +26,7 @@
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#include "rc.h"
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#include "debug.h"
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#include "../ath.h"
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#include "../debug.h"
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struct ath_node;
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@ -26,6 +26,7 @@
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static int ath_beaconq_config(struct ath_softc *sc)
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{
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struct ath_hw *ah = sc->sc_ah;
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath9k_tx_queue_info qi;
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ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi);
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@ -42,7 +43,7 @@ static int ath_beaconq_config(struct ath_softc *sc)
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}
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if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) {
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DPRINTF(ah, ATH_DBG_FATAL,
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ath_print(common, ATH_DBG_FATAL,
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"Unable to update h/w beacon queue parameters\n");
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return 0;
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} else {
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@ -119,6 +120,7 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
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{
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struct ath_wiphy *aphy = hw->priv;
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struct ath_softc *sc = aphy->sc;
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struct ath_common *common = ath9k_hw_common(sc->sc_ah);
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struct ath_buf *bf;
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struct ath_vif *avp;
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struct sk_buff *skb;
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@ -172,7 +174,8 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
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if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
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dev_kfree_skb_any(skb);
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bf->bf_mpdu = NULL;
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DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "dma_mapping_error on beaconing\n");
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ath_print(common, ATH_DBG_FATAL,
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"dma_mapping_error on beaconing\n");
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return NULL;
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}
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@ -192,7 +195,7 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
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if (skb && cabq_depth) {
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if (sc->nvifs > 1) {
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DPRINTF(sc->sc_ah, ATH_DBG_BEACON,
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ath_print(common, ATH_DBG_BEACON,
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"Flushing previous cabq traffic\n");
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ath_draintxq(sc, cabq, false);
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}
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@ -216,6 +219,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc,
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struct ieee80211_vif *vif)
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{
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struct ath_hw *ah = sc->sc_ah;
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath_buf *bf;
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struct ath_vif *avp;
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struct sk_buff *skb;
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@ -233,7 +237,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc,
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/* NB: caller is known to have already stopped tx dma */
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ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bf->bf_daddr);
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ath9k_hw_txstart(ah, sc->beacon.beaconq);
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DPRINTF(ah, ATH_DBG_BEACON, "TXDP%u = %llx (%p)\n",
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ath_print(common, ATH_DBG_BEACON, "TXDP%u = %llx (%p)\n",
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sc->beacon.beaconq, ito64(bf->bf_daddr), bf->bf_desc);
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}
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@ -252,6 +256,7 @@ int ath_beaconq_setup(struct ath_hw *ah)
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int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
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{
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struct ath_softc *sc = aphy->sc;
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struct ath_common *common = ath9k_hw_common(sc->sc_ah);
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struct ath_vif *avp;
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struct ath_buf *bf;
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struct sk_buff *skb;
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||||
|
@ -309,7 +314,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
|
|||
/* NB: the beacon data buffer must be 32-bit aligned. */
|
||||
skb = ieee80211_beacon_get(sc->hw, vif);
|
||||
if (skb == NULL) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_BEACON, "cannot get skb\n");
|
||||
ath_print(common, ATH_DBG_BEACON, "cannot get skb\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
|
@ -333,8 +338,9 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
|
|||
tsfadjust = intval * avp->av_bslot / ATH_BCBUF;
|
||||
avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust));
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_BEACON,
|
||||
"stagger beacons, bslot %d intval %u tsfadjust %llu\n",
|
||||
ath_print(common, ATH_DBG_BEACON,
|
||||
"stagger beacons, bslot %d intval "
|
||||
"%u tsfadjust %llu\n",
|
||||
avp->av_bslot, intval, (unsigned long long)tsfadjust);
|
||||
|
||||
((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp =
|
||||
|
@ -349,7 +355,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
|
|||
if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
|
||||
dev_kfree_skb_any(skb);
|
||||
bf->bf_mpdu = NULL;
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"dma_mapping_error on beacon alloc\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
@ -386,6 +392,7 @@ void ath_beacon_tasklet(unsigned long data)
|
|||
{
|
||||
struct ath_softc *sc = (struct ath_softc *)data;
|
||||
struct ath_hw *ah = sc->sc_ah;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
struct ath_buf *bf = NULL;
|
||||
struct ieee80211_vif *vif;
|
||||
struct ath_wiphy *aphy;
|
||||
|
@ -405,11 +412,11 @@ void ath_beacon_tasklet(unsigned long data)
|
|||
sc->beacon.bmisscnt++;
|
||||
|
||||
if (sc->beacon.bmisscnt < BSTUCK_THRESH) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_BEACON,
|
||||
ath_print(common, ATH_DBG_BEACON,
|
||||
"missed %u consecutive beacons\n",
|
||||
sc->beacon.bmisscnt);
|
||||
} else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_BEACON,
|
||||
ath_print(common, ATH_DBG_BEACON,
|
||||
"beacon is officially stuck\n");
|
||||
sc->sc_flags |= SC_OP_TSF_RESET;
|
||||
ath_reset(sc, false);
|
||||
|
@ -419,7 +426,7 @@ void ath_beacon_tasklet(unsigned long data)
|
|||
}
|
||||
|
||||
if (sc->beacon.bmisscnt != 0) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_BEACON,
|
||||
ath_print(common, ATH_DBG_BEACON,
|
||||
"resume beacon xmit after %u misses\n",
|
||||
sc->beacon.bmisscnt);
|
||||
sc->beacon.bmisscnt = 0;
|
||||
|
@ -447,7 +454,7 @@ void ath_beacon_tasklet(unsigned long data)
|
|||
vif = sc->beacon.bslot[slot];
|
||||
aphy = sc->beacon.bslot_aphy[slot];
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_BEACON,
|
||||
ath_print(common, ATH_DBG_BEACON,
|
||||
"slot %d [tsf %llu tsftu %u intval %u] vif %p\n",
|
||||
slot, tsf, tsftu, intval, vif);
|
||||
|
||||
|
@ -490,7 +497,7 @@ void ath_beacon_tasklet(unsigned long data)
|
|||
* are still pending on the queue.
|
||||
*/
|
||||
if (!ath9k_hw_stoptxdma(ah, sc->beacon.beaconq)) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"beacon queue %u did not stop?\n", sc->beacon.beaconq);
|
||||
}
|
||||
|
||||
|
@ -568,6 +575,7 @@ static void ath_beacon_config_ap(struct ath_softc *sc,
|
|||
static void ath_beacon_config_sta(struct ath_softc *sc,
|
||||
struct ath_beacon_config *conf)
|
||||
{
|
||||
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
||||
struct ath9k_beacon_state bs;
|
||||
int dtimperiod, dtimcount, sleepduration;
|
||||
int cfpperiod, cfpcount;
|
||||
|
@ -664,8 +672,8 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
|
|||
/* TSF out of range threshold fixed at 1 second */
|
||||
bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD;
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_BEACON,
|
||||
ath_print(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
|
||||
ath_print(common, ATH_DBG_BEACON,
|
||||
"bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
|
||||
bs.bs_bmissthreshold, bs.bs_sleepduration,
|
||||
bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
|
||||
|
@ -682,6 +690,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
|
|||
struct ath_beacon_config *conf,
|
||||
struct ieee80211_vif *vif)
|
||||
{
|
||||
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
||||
u64 tsf;
|
||||
u32 tsftu, intval, nexttbtt;
|
||||
|
||||
|
@ -702,7 +711,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
|
|||
nexttbtt += intval;
|
||||
} while (nexttbtt < tsftu);
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_BEACON,
|
||||
ath_print(common, ATH_DBG_BEACON,
|
||||
"IBSS nexttbtt %u intval %u (%u)\n",
|
||||
nexttbtt, intval, conf->beacon_interval);
|
||||
|
||||
|
@ -732,6 +741,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
|
|||
void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
|
||||
{
|
||||
struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
|
||||
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
||||
enum nl80211_iftype iftype;
|
||||
|
||||
/* Setup the beacon configuration parameters */
|
||||
|
@ -772,7 +782,7 @@ void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
|
|||
ath_beacon_config_sta(sc, cur_conf);
|
||||
break;
|
||||
default:
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
|
||||
ath_print(common, ATH_DBG_CONFIG,
|
||||
"Unsupported beaconing mode\n");
|
||||
return;
|
||||
}
|
||||
|
|
|
@ -15,6 +15,7 @@
|
|||
*/
|
||||
|
||||
#include "ath9k.h"
|
||||
#include "hw.h"
|
||||
|
||||
/* We can tune this as we go by monitoring really low values */
|
||||
#define ATH9K_NF_TOO_LOW -60
|
||||
|
@ -26,7 +27,7 @@
|
|||
static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf)
|
||||
{
|
||||
if (nf > ATH9K_NF_TOO_LOW) {
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
|
||||
"noise floor value detected (%d) is "
|
||||
"lower than what we think is a "
|
||||
"reasonable value (%d)\n",
|
||||
|
@ -89,6 +90,7 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
|
|||
static void ath9k_hw_do_getnf(struct ath_hw *ah,
|
||||
int16_t nfarray[NUM_NF_READINGS])
|
||||
{
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
int16_t nf;
|
||||
|
||||
if (AR_SREV_9280_10_OR_LATER(ah))
|
||||
|
@ -98,7 +100,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
|
|||
|
||||
if (nf & 0x100)
|
||||
nf = 0 - ((nf ^ 0x1ff) + 1);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"NF calibrated [ctl] [chain 0] is %d\n", nf);
|
||||
nfarray[0] = nf;
|
||||
|
||||
|
@ -112,7 +114,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
|
|||
|
||||
if (nf & 0x100)
|
||||
nf = 0 - ((nf ^ 0x1ff) + 1);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"NF calibrated [ctl] [chain 1] is %d\n", nf);
|
||||
nfarray[1] = nf;
|
||||
|
||||
|
@ -121,7 +123,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
|
|||
AR_PHY_CH2_MINCCA_PWR);
|
||||
if (nf & 0x100)
|
||||
nf = 0 - ((nf ^ 0x1ff) + 1);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"NF calibrated [ctl] [chain 2] is %d\n", nf);
|
||||
nfarray[2] = nf;
|
||||
}
|
||||
|
@ -136,7 +138,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
|
|||
|
||||
if (nf & 0x100)
|
||||
nf = 0 - ((nf ^ 0x1ff) + 1);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"NF calibrated [ext] [chain 0] is %d\n", nf);
|
||||
nfarray[3] = nf;
|
||||
|
||||
|
@ -150,7 +152,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
|
|||
|
||||
if (nf & 0x100)
|
||||
nf = 0 - ((nf ^ 0x1ff) + 1);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"NF calibrated [ext] [chain 1] is %d\n", nf);
|
||||
nfarray[4] = nf;
|
||||
|
||||
|
@ -159,7 +161,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
|
|||
AR_PHY_CH2_EXT_MINCCA_PWR);
|
||||
if (nf & 0x100)
|
||||
nf = 0 - ((nf ^ 0x1ff) + 1);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"NF calibrated [ext] [chain 2] is %d\n", nf);
|
||||
nfarray[5] = nf;
|
||||
}
|
||||
|
@ -188,6 +190,8 @@ static bool getNoiseFloorThresh(struct ath_hw *ah,
|
|||
static void ath9k_hw_setup_calibration(struct ath_hw *ah,
|
||||
struct ath9k_cal_list *currCal)
|
||||
{
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
|
||||
REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
|
||||
AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
|
||||
currCal->calData->calCountMax);
|
||||
|
@ -195,22 +199,22 @@ static void ath9k_hw_setup_calibration(struct ath_hw *ah,
|
|||
switch (currCal->calData->calType) {
|
||||
case IQ_MISMATCH_CAL:
|
||||
REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"starting IQ Mismatch Calibration\n");
|
||||
break;
|
||||
case ADC_GAIN_CAL:
|
||||
REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"starting ADC Gain Calibration\n");
|
||||
break;
|
||||
case ADC_DC_CAL:
|
||||
REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"starting ADC DC Calibration\n");
|
||||
break;
|
||||
case ADC_DC_INIT_CAL:
|
||||
REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"starting Init ADC DC Calibration\n");
|
||||
break;
|
||||
}
|
||||
|
@ -304,7 +308,7 @@ static void ath9k_hw_iqcal_collect(struct ath_hw *ah)
|
|||
REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
|
||||
ah->totalIqCorrMeas[i] +=
|
||||
(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
|
||||
"%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
|
||||
ah->cal_samples, i, ah->totalPowerMeasI[i],
|
||||
ah->totalPowerMeasQ[i],
|
||||
|
@ -326,7 +330,7 @@ static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah)
|
|||
ah->totalAdcQEvenPhase[i] +=
|
||||
REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
|
||||
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
|
||||
"%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
|
||||
"oddq=0x%08x; evenq=0x%08x;\n",
|
||||
ah->cal_samples, i,
|
||||
|
@ -351,7 +355,7 @@ static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
|
|||
ah->totalAdcDcOffsetQEvenPhase[i] +=
|
||||
(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
|
||||
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
|
||||
"%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
|
||||
"oddq=0x%08x; evenq=0x%08x;\n",
|
||||
ah->cal_samples, i,
|
||||
|
@ -364,6 +368,7 @@ static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
|
|||
|
||||
static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
|
||||
{
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
u32 powerMeasQ, powerMeasI, iqCorrMeas;
|
||||
u32 qCoffDenom, iCoffDenom;
|
||||
int32_t qCoff, iCoff;
|
||||
|
@ -374,11 +379,11 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
|
|||
powerMeasQ = ah->totalPowerMeasQ[i];
|
||||
iqCorrMeas = ah->totalIqCorrMeas[i];
|
||||
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"Starting IQ Cal and Correction for Chain %d\n",
|
||||
i);
|
||||
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"Orignal: Chn %diq_corr_meas = 0x%08x\n",
|
||||
i, ah->totalIqCorrMeas[i]);
|
||||
|
||||
|
@ -389,11 +394,11 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
|
|||
iqCorrNeg = 1;
|
||||
}
|
||||
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
|
||||
ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
|
||||
iqCorrNeg);
|
||||
|
||||
iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
|
||||
|
@ -402,13 +407,13 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
|
|||
if (powerMeasQ != 0) {
|
||||
iCoff = iqCorrMeas / iCoffDenom;
|
||||
qCoff = powerMeasI / qCoffDenom - 64;
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"Chn %d iCoff = 0x%08x\n", i, iCoff);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"Chn %d qCoff = 0x%08x\n", i, qCoff);
|
||||
|
||||
iCoff = iCoff & 0x3f;
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"New: Chn %d iCoff = 0x%08x\n", i, iCoff);
|
||||
if (iqCorrNeg == 0x0)
|
||||
iCoff = 0x40 - iCoff;
|
||||
|
@ -418,7 +423,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
|
|||
else if (qCoff <= -16)
|
||||
qCoff = 16;
|
||||
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
|
||||
i, iCoff, qCoff);
|
||||
|
||||
|
@ -428,7 +433,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
|
|||
REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
|
||||
AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
|
||||
qCoff);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"IQ Cal and Correction done for Chain %d\n",
|
||||
i);
|
||||
}
|
||||
|
@ -440,6 +445,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
|
|||
|
||||
static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
|
||||
{
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
|
||||
u32 qGainMismatch, iGainMismatch, val, i;
|
||||
|
||||
|
@ -449,19 +455,19 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
|
|||
qOddMeasOffset = ah->totalAdcQOddPhase[i];
|
||||
qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
|
||||
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"Starting ADC Gain Cal for Chain %d\n", i);
|
||||
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"Chn %d pwr_meas_odd_i = 0x%08x\n", i,
|
||||
iOddMeasOffset);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"Chn %d pwr_meas_even_i = 0x%08x\n", i,
|
||||
iEvenMeasOffset);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"Chn %d pwr_meas_odd_q = 0x%08x\n", i,
|
||||
qOddMeasOffset);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"Chn %d pwr_meas_even_q = 0x%08x\n", i,
|
||||
qEvenMeasOffset);
|
||||
|
||||
|
@ -473,10 +479,10 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
|
|||
((qOddMeasOffset * 32) /
|
||||
qEvenMeasOffset) & 0x3f;
|
||||
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"Chn %d gain_mismatch_i = 0x%08x\n", i,
|
||||
iGainMismatch);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"Chn %d gain_mismatch_q = 0x%08x\n", i,
|
||||
qGainMismatch);
|
||||
|
||||
|
@ -485,7 +491,7 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
|
|||
val |= (qGainMismatch) | (iGainMismatch << 6);
|
||||
REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
|
||||
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"ADC Gain Cal done for Chain %d\n", i);
|
||||
}
|
||||
}
|
||||
|
@ -497,6 +503,7 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
|
|||
|
||||
static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
|
||||
{
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
u32 iOddMeasOffset, iEvenMeasOffset, val, i;
|
||||
int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
|
||||
const struct ath9k_percal_data *calData =
|
||||
|
@ -510,19 +517,19 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
|
|||
qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
|
||||
qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
|
||||
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"Starting ADC DC Offset Cal for Chain %d\n", i);
|
||||
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"Chn %d pwr_meas_odd_i = %d\n", i,
|
||||
iOddMeasOffset);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"Chn %d pwr_meas_even_i = %d\n", i,
|
||||
iEvenMeasOffset);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"Chn %d pwr_meas_odd_q = %d\n", i,
|
||||
qOddMeasOffset);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"Chn %d pwr_meas_even_q = %d\n", i,
|
||||
qEvenMeasOffset);
|
||||
|
||||
|
@ -531,10 +538,10 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
|
|||
qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
|
||||
numSamples) & 0x1ff;
|
||||
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
|
||||
iDcMismatch);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
|
||||
qDcMismatch);
|
||||
|
||||
|
@ -543,7 +550,7 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
|
|||
val |= (qDcMismatch << 12) | (iDcMismatch << 21);
|
||||
REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
|
||||
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"ADC DC Offset Cal done for Chain %d\n", i);
|
||||
}
|
||||
|
||||
|
@ -555,7 +562,8 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
|
|||
/* This is done for the currently configured channel */
|
||||
bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
|
||||
{
|
||||
struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
struct ieee80211_conf *conf = &common->hw->conf;
|
||||
struct ath9k_cal_list *currCal = ah->cal_list_curr;
|
||||
|
||||
if (!ah->curchan)
|
||||
|
@ -568,7 +576,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
|
|||
return true;
|
||||
|
||||
if (currCal->calState != CAL_DONE) {
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"Calibration state incorrect, %d\n",
|
||||
currCal->calState);
|
||||
return true;
|
||||
|
@ -577,7 +585,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
|
|||
if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType))
|
||||
return true;
|
||||
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"Resetting Cal %d state for channel %u\n",
|
||||
currCal->calData->calType, conf->channel->center_freq);
|
||||
|
||||
|
@ -665,6 +673,7 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
|
|||
int16_t ath9k_hw_getnf(struct ath_hw *ah,
|
||||
struct ath9k_channel *chan)
|
||||
{
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
int16_t nf, nfThresh;
|
||||
int16_t nfarray[NUM_NF_READINGS] = { 0 };
|
||||
struct ath9k_nfcal_hist *h;
|
||||
|
@ -672,7 +681,7 @@ int16_t ath9k_hw_getnf(struct ath_hw *ah,
|
|||
|
||||
chan->channelFlags &= (~CHANNEL_CW_INT);
|
||||
if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"NF did not complete in calibration window\n");
|
||||
nf = 0;
|
||||
chan->rawNoiseFloor = nf;
|
||||
|
@ -682,7 +691,7 @@ int16_t ath9k_hw_getnf(struct ath_hw *ah,
|
|||
nf = nfarray[0];
|
||||
if (getNoiseFloorThresh(ah, c->band, &nfThresh)
|
||||
&& nf > nfThresh) {
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"noise floor failed detected; "
|
||||
"detected %d, threshold %d\n",
|
||||
nf, nfThresh);
|
||||
|
@ -875,7 +884,7 @@ static void ath9k_hw_9271_pa_cal(struct ath_hw *ah)
|
|||
|
||||
static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
|
||||
{
|
||||
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
u32 regVal;
|
||||
int i, offset, offs_6_1, offs_0;
|
||||
u32 ccomp_org, reg_field;
|
||||
|
@ -889,7 +898,7 @@ static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
|
|||
{ 0x7838, 0 },
|
||||
};
|
||||
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
|
||||
ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
|
||||
|
||||
/* PA CAL is not needed for high power solution */
|
||||
if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
|
||||
|
@ -1039,6 +1048,8 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
|
|||
|
||||
static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
|
||||
{
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
|
||||
REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
|
||||
if (IS_CHAN_HT20(chan)) {
|
||||
REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
|
||||
|
@ -1049,7 +1060,7 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
|
|||
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
|
||||
if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
|
||||
AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE, "offset "
|
||||
ath_print(common, ATH_DBG_CALIBRATE, "offset "
|
||||
"calibration failed to complete in "
|
||||
"1ms; noisy ??\n");
|
||||
return false;
|
||||
|
@ -1064,7 +1075,7 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
|
|||
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
|
||||
if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
|
||||
0, AH_WAIT_TIMEOUT)) {
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE, "offset calibration "
|
||||
ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
|
||||
"failed to complete in 1ms; noisy ??\n");
|
||||
return false;
|
||||
}
|
||||
|
@ -1078,6 +1089,8 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
|
|||
|
||||
bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
|
||||
{
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
|
||||
if (AR_SREV_9285_12_OR_LATER(ah)) {
|
||||
if (!ar9285_clc(ah, chan))
|
||||
return false;
|
||||
|
@ -1098,9 +1111,9 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
|
|||
/* Poll for offset calibration complete */
|
||||
if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
|
||||
0, AH_WAIT_TIMEOUT)) {
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
"offset calibration failed to complete in 1ms; "
|
||||
"noisy environment?\n");
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"offset calibration failed to "
|
||||
"complete in 1ms; noisy environment?\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
|
@ -1128,19 +1141,19 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
|
|||
if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
|
||||
INIT_CAL(&ah->adcgain_caldata);
|
||||
INSERT_CAL(ah, &ah->adcgain_caldata);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"enabling ADC Gain Calibration.\n");
|
||||
}
|
||||
if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
|
||||
INIT_CAL(&ah->adcdc_caldata);
|
||||
INSERT_CAL(ah, &ah->adcdc_caldata);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"enabling ADC DC Calibration.\n");
|
||||
}
|
||||
if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
|
||||
INIT_CAL(&ah->iq_caldata);
|
||||
INSERT_CAL(ah, &ah->iq_caldata);
|
||||
DPRINTF(ah, ATH_DBG_CALIBRATE,
|
||||
ath_print(common, ATH_DBG_CALIBRATE,
|
||||
"enabling IQ Calibration.\n");
|
||||
}
|
||||
|
||||
|
|
|
@ -17,6 +17,8 @@
|
|||
#ifndef CALIB_H
|
||||
#define CALIB_H
|
||||
|
||||
#include "hw.h"
|
||||
|
||||
extern const struct ath9k_percal_data iq_cal_multi_sample;
|
||||
extern const struct ath9k_percal_data iq_cal_single_sample;
|
||||
extern const struct ath9k_percal_data adc_gain_cal_multi_sample;
|
||||
|
|
|
@ -18,26 +18,11 @@
|
|||
|
||||
#include "ath9k.h"
|
||||
|
||||
static unsigned int ath9k_debug = DBG_DEFAULT;
|
||||
static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
|
||||
module_param_named(debug, ath9k_debug, uint, 0);
|
||||
|
||||
static struct dentry *ath9k_debugfs_root;
|
||||
|
||||
void DPRINTF(struct ath_hw *ah, int dbg_mask, const char *fmt, ...)
|
||||
{
|
||||
if (!ah->ah_sc)
|
||||
return;
|
||||
|
||||
if (ah->ah_sc->debug.debug_mask & dbg_mask) {
|
||||
va_list args;
|
||||
|
||||
va_start(args, fmt);
|
||||
printk(KERN_DEBUG "ath9k: ");
|
||||
vprintk(fmt, args);
|
||||
va_end(args);
|
||||
}
|
||||
}
|
||||
|
||||
static int ath9k_debugfs_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
file->private_data = inode->i_private;
|
||||
|
@ -48,10 +33,11 @@ static ssize_t read_file_debug(struct file *file, char __user *user_buf,
|
|||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct ath_softc *sc = file->private_data;
|
||||
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
||||
char buf[32];
|
||||
unsigned int len;
|
||||
|
||||
len = snprintf(buf, sizeof(buf), "0x%08x\n", sc->debug.debug_mask);
|
||||
len = snprintf(buf, sizeof(buf), "0x%08x\n", common->debug_mask);
|
||||
return simple_read_from_buffer(user_buf, count, ppos, buf, len);
|
||||
}
|
||||
|
||||
|
@ -59,6 +45,7 @@ static ssize_t write_file_debug(struct file *file, const char __user *user_buf,
|
|||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct ath_softc *sc = file->private_data;
|
||||
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
||||
unsigned long mask;
|
||||
char buf[32];
|
||||
ssize_t len;
|
||||
|
@ -71,7 +58,7 @@ static ssize_t write_file_debug(struct file *file, const char __user *user_buf,
|
|||
if (strict_strtoul(buf, 0, &mask))
|
||||
return -EINVAL;
|
||||
|
||||
sc->debug.debug_mask = mask;
|
||||
common->debug_mask = mask;
|
||||
return count;
|
||||
}
|
||||
|
||||
|
@ -571,8 +558,9 @@ static const struct file_operations fops_xmit = {
|
|||
int ath9k_init_debug(struct ath_hw *ah)
|
||||
{
|
||||
struct ath_softc *sc = ah->ah_sc;
|
||||
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
||||
|
||||
sc->debug.debug_mask = ath9k_debug;
|
||||
common->debug_mask = ath9k_debug;
|
||||
|
||||
if (!ath9k_debugfs_root)
|
||||
return -ENOENT;
|
||||
|
|
|
@ -19,26 +19,6 @@
|
|||
|
||||
#include "hw.h"
|
||||
|
||||
enum ATH_DEBUG {
|
||||
ATH_DBG_RESET = 0x00000001,
|
||||
ATH_DBG_QUEUE = 0x00000002,
|
||||
ATH_DBG_EEPROM = 0x00000004,
|
||||
ATH_DBG_CALIBRATE = 0x00000008,
|
||||
ATH_DBG_INTERRUPT = 0x00000010,
|
||||
ATH_DBG_REGULATORY = 0x00000020,
|
||||
ATH_DBG_ANI = 0x00000040,
|
||||
ATH_DBG_XMIT = 0x00000080,
|
||||
ATH_DBG_BEACON = 0x00000100,
|
||||
ATH_DBG_CONFIG = 0x00000200,
|
||||
ATH_DBG_FATAL = 0x00000400,
|
||||
ATH_DBG_PS = 0x00000800,
|
||||
ATH_DBG_HWTIMER = 0x00001000,
|
||||
ATH_DBG_BTCOEX = 0x00002000,
|
||||
ATH_DBG_ANY = 0xffffffff
|
||||
};
|
||||
|
||||
#define DBG_DEFAULT (ATH_DBG_FATAL)
|
||||
|
||||
struct ath_txq;
|
||||
struct ath_buf;
|
||||
|
||||
|
@ -142,7 +122,6 @@ struct ath_stats {
|
|||
};
|
||||
|
||||
struct ath9k_debug {
|
||||
int debug_mask;
|
||||
struct dentry *debugfs_phy;
|
||||
struct dentry *debugfs_debug;
|
||||
struct dentry *debugfs_dma;
|
||||
|
@ -153,7 +132,6 @@ struct ath9k_debug {
|
|||
struct ath_stats stats;
|
||||
};
|
||||
|
||||
void DPRINTF(struct ath_hw *ah, int dbg_mask, const char *fmt, ...);
|
||||
int ath9k_init_debug(struct ath_hw *ah);
|
||||
void ath9k_exit_debug(struct ath_hw *ah);
|
||||
|
||||
|
@ -168,11 +146,6 @@ void ath_debug_stat_retries(struct ath_softc *sc, int rix,
|
|||
|
||||
#else
|
||||
|
||||
static inline void DPRINTF(struct ath_hw *ah, int dbg_mask,
|
||||
const char *fmt, ...)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int ath9k_init_debug(struct ath_hw *ah)
|
||||
{
|
||||
return 0;
|
||||
|
|
|
@ -15,6 +15,7 @@
|
|||
*/
|
||||
|
||||
#include "ath9k.h"
|
||||
#include "hw.h"
|
||||
|
||||
static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
|
||||
{
|
||||
|
@ -29,19 +30,20 @@ static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
|
|||
static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
|
||||
{
|
||||
#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
u16 *eep_data = (u16 *)&ah->eeprom.map4k;
|
||||
int addr, eep_start_loc = 0;
|
||||
|
||||
eep_start_loc = 64;
|
||||
|
||||
if (!ath9k_hw_use_flash(ah)) {
|
||||
DPRINTF(ah, ATH_DBG_EEPROM,
|
||||
ath_print(common, ATH_DBG_EEPROM,
|
||||
"Reading from EEPROM, not flash\n");
|
||||
}
|
||||
|
||||
for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
|
||||
if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
|
||||
DPRINTF(ah, ATH_DBG_EEPROM,
|
||||
ath_print(common, ATH_DBG_EEPROM,
|
||||
"Unable to read eeprom region \n");
|
||||
return false;
|
||||
}
|
||||
|
@ -55,6 +57,7 @@ static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
|
|||
static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
|
||||
{
|
||||
#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
struct ar5416_eeprom_4k *eep =
|
||||
(struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
|
||||
u16 *eepdata, temp, magic, magic2;
|
||||
|
@ -66,12 +69,12 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
|
|||
if (!ath9k_hw_use_flash(ah)) {
|
||||
if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
|
||||
&magic)) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Reading Magic # failed\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
DPRINTF(ah, ATH_DBG_EEPROM,
|
||||
ath_print(common, ATH_DBG_EEPROM,
|
||||
"Read Magic = 0x%04X\n", magic);
|
||||
|
||||
if (magic != AR5416_EEPROM_MAGIC) {
|
||||
|
@ -87,7 +90,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
|
|||
eepdata++;
|
||||
}
|
||||
} else {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Invalid EEPROM Magic. "
|
||||
"endianness mismatch.\n");
|
||||
return -EINVAL;
|
||||
|
@ -95,7 +98,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
|
|||
}
|
||||
}
|
||||
|
||||
DPRINTF(ah, ATH_DBG_EEPROM, "need_swap = %s.\n",
|
||||
ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
|
||||
need_swap ? "True" : "False");
|
||||
|
||||
if (need_swap)
|
||||
|
@ -117,7 +120,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
|
|||
u32 integer;
|
||||
u16 word;
|
||||
|
||||
DPRINTF(ah, ATH_DBG_EEPROM,
|
||||
ath_print(common, ATH_DBG_EEPROM,
|
||||
"EEPROM Endianness is not native.. Changing\n");
|
||||
|
||||
word = swab16(eep->baseEepHeader.length);
|
||||
|
@ -160,7 +163,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
|
|||
|
||||
if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
|
||||
ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Bad EEPROM checksum 0x%x or revision 0x%04x\n",
|
||||
sum, ah->eep_ops->get_eeprom_ver(ah));
|
||||
return -EINVAL;
|
||||
|
@ -385,6 +388,7 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
|
|||
struct ath9k_channel *chan,
|
||||
int16_t *pTxPowerIndexOffset)
|
||||
{
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
|
||||
struct cal_data_per_freq_4k *pRawDataset;
|
||||
u8 *pCalBChans = NULL;
|
||||
|
@ -470,11 +474,11 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
|
|||
((pdadcValues[4 * j + 3] & 0xFF) << 24);
|
||||
REG_WRITE(ah, regOffset, reg32);
|
||||
|
||||
DPRINTF(ah, ATH_DBG_EEPROM,
|
||||
ath_print(common, ATH_DBG_EEPROM,
|
||||
"PDADC (%d,%4x): %4.4x %8.8x\n",
|
||||
i, regChainOffset, regOffset,
|
||||
reg32);
|
||||
DPRINTF(ah, ATH_DBG_EEPROM,
|
||||
ath_print(common, ATH_DBG_EEPROM,
|
||||
"PDADC: Chain %d | "
|
||||
"PDADC %3d Value %3d | "
|
||||
"PDADC %3d Value %3d | "
|
||||
|
@ -1148,10 +1152,11 @@ static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
|
|||
{
|
||||
#define EEP_MAP4K_SPURCHAN \
|
||||
(ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
|
||||
u16 spur_val = AR_NO_SPUR;
|
||||
|
||||
DPRINTF(ah, ATH_DBG_ANI,
|
||||
ath_print(common, ATH_DBG_ANI,
|
||||
"Getting spur idx %d is2Ghz. %d val %x\n",
|
||||
i, is2GHz, ah->config.spurchans[i][is2GHz]);
|
||||
|
||||
|
@ -1160,7 +1165,7 @@ static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
|
|||
break;
|
||||
case SPUR_ENABLE_IOCTL:
|
||||
spur_val = ah->config.spurchans[i][is2GHz];
|
||||
DPRINTF(ah, ATH_DBG_ANI,
|
||||
ath_print(common, ATH_DBG_ANI,
|
||||
"Getting spur val from new loc. %d\n", spur_val);
|
||||
break;
|
||||
case SPUR_ENABLE_EEPROM:
|
||||
|
|
|
@ -15,6 +15,7 @@
|
|||
*/
|
||||
|
||||
#include "ath9k.h"
|
||||
#include "hw.h"
|
||||
|
||||
static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah)
|
||||
{
|
||||
|
@ -29,19 +30,20 @@ static int ath9k_hw_AR9287_get_eeprom_rev(struct ath_hw *ah)
|
|||
static bool ath9k_hw_AR9287_fill_eeprom(struct ath_hw *ah)
|
||||
{
|
||||
struct ar9287_eeprom *eep = &ah->eeprom.map9287;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
u16 *eep_data;
|
||||
int addr, eep_start_loc = AR9287_EEP_START_LOC;
|
||||
eep_data = (u16 *)eep;
|
||||
|
||||
if (!ath9k_hw_use_flash(ah)) {
|
||||
DPRINTF(ah, ATH_DBG_EEPROM,
|
||||
ath_print(common, ATH_DBG_EEPROM,
|
||||
"Reading from EEPROM, not flash\n");
|
||||
}
|
||||
|
||||
for (addr = 0; addr < sizeof(struct ar9287_eeprom) / sizeof(u16);
|
||||
addr++) {
|
||||
if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
|
||||
DPRINTF(ah, ATH_DBG_EEPROM,
|
||||
ath_print(common, ATH_DBG_EEPROM,
|
||||
"Unable to read eeprom region \n");
|
||||
return false;
|
||||
}
|
||||
|
@ -57,16 +59,17 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
|
|||
int i, addr;
|
||||
bool need_swap = false;
|
||||
struct ar9287_eeprom *eep = &ah->eeprom.map9287;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
|
||||
if (!ath9k_hw_use_flash(ah)) {
|
||||
if (!ath9k_hw_nvram_read
|
||||
(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Reading Magic # failed\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
DPRINTF(ah, ATH_DBG_EEPROM,
|
||||
ath_print(common, ATH_DBG_EEPROM,
|
||||
"Read Magic = 0x%04X\n", magic);
|
||||
if (magic != AR5416_EEPROM_MAGIC) {
|
||||
magic2 = swab16(magic);
|
||||
|
@ -83,14 +86,14 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
|
|||
eepdata++;
|
||||
}
|
||||
} else {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Invalid EEPROM Magic. "
|
||||
"endianness mismatch.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
}
|
||||
DPRINTF(ah, ATH_DBG_EEPROM, "need_swap = %s.\n", need_swap ?
|
||||
ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n", need_swap ?
|
||||
"True" : "False");
|
||||
|
||||
if (need_swap)
|
||||
|
@ -148,7 +151,7 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
|
|||
|
||||
if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER
|
||||
|| ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Bad EEPROM checksum 0x%x or revision 0x%04x\n",
|
||||
sum, ah->eep_ops->get_eeprom_ver(ah));
|
||||
return -EINVAL;
|
||||
|
@ -436,6 +439,7 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
|
|||
struct ath9k_channel *chan,
|
||||
int16_t *pTxPowerIndexOffset)
|
||||
{
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
struct cal_data_per_freq_ar9287 *pRawDataset;
|
||||
struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
|
||||
u8 *pCalBChans = NULL;
|
||||
|
@ -564,12 +568,13 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
|
|||
& 0xFF) << 24) ;
|
||||
REG_WRITE(ah, regOffset, reg32);
|
||||
|
||||
DPRINTF(ah, ATH_DBG_EEPROM,
|
||||
"PDADC (%d,%4x): %4.4x %8.8x\n",
|
||||
ath_print(common, ATH_DBG_EEPROM,
|
||||
"PDADC (%d,%4x): %4.4x "
|
||||
"%8.8x\n",
|
||||
i, regChainOffset, regOffset,
|
||||
reg32);
|
||||
|
||||
DPRINTF(ah, ATH_DBG_EEPROM,
|
||||
ath_print(common, ATH_DBG_EEPROM,
|
||||
"PDADC: Chain %d | "
|
||||
"PDADC %3d Value %3d | "
|
||||
"PDADC %3d Value %3d | "
|
||||
|
@ -831,6 +836,7 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
|
|||
{
|
||||
#define INCREASE_MAXPOW_BY_TWO_CHAIN 6
|
||||
#define INCREASE_MAXPOW_BY_THREE_CHAIN 10
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
|
||||
struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
|
||||
struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader;
|
||||
|
@ -966,7 +972,7 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
|
|||
INCREASE_MAXPOW_BY_THREE_CHAIN;
|
||||
break;
|
||||
default:
|
||||
DPRINTF(ah, ATH_DBG_EEPROM,
|
||||
ath_print(common, ATH_DBG_EEPROM,
|
||||
"Invalid chainmask configuration\n");
|
||||
break;
|
||||
}
|
||||
|
@ -1138,9 +1144,10 @@ static u16 ath9k_hw_AR9287_get_spur_channel(struct ath_hw *ah,
|
|||
{
|
||||
#define EEP_MAP9287_SPURCHAN \
|
||||
(ah->eeprom.map9287.modalHeader.spurChans[i].spurChan)
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
u16 spur_val = AR_NO_SPUR;
|
||||
|
||||
DPRINTF(ah, ATH_DBG_ANI,
|
||||
ath_print(common, ATH_DBG_ANI,
|
||||
"Getting spur idx %d is2Ghz. %d val %x\n",
|
||||
i, is2GHz, ah->config.spurchans[i][is2GHz]);
|
||||
|
||||
|
@ -1149,7 +1156,7 @@ static u16 ath9k_hw_AR9287_get_spur_channel(struct ath_hw *ah,
|
|||
break;
|
||||
case SPUR_ENABLE_IOCTL:
|
||||
spur_val = ah->config.spurchans[i][is2GHz];
|
||||
DPRINTF(ah, ATH_DBG_ANI,
|
||||
ath_print(common, ATH_DBG_ANI,
|
||||
"Getting spur val from new loc. %d\n", spur_val);
|
||||
break;
|
||||
case SPUR_ENABLE_EEPROM:
|
||||
|
|
|
@ -15,6 +15,7 @@
|
|||
*/
|
||||
|
||||
#include "ath9k.h"
|
||||
#include "hw.h"
|
||||
|
||||
static void ath9k_get_txgain_index(struct ath_hw *ah,
|
||||
struct ath9k_channel *chan,
|
||||
|
@ -95,7 +96,7 @@ static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
|
|||
for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
|
||||
if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
|
||||
eep_data)) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
|
||||
"Unable to read eeprom region\n");
|
||||
return false;
|
||||
}
|
||||
|
@ -109,18 +110,19 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
|
|||
{
|
||||
struct ar5416_eeprom_def *eep =
|
||||
(struct ar5416_eeprom_def *) &ah->eeprom.def;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
u16 *eepdata, temp, magic, magic2;
|
||||
u32 sum = 0, el;
|
||||
bool need_swap = false;
|
||||
int i, addr, size;
|
||||
|
||||
if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL, "Reading Magic # failed\n");
|
||||
ath_print(common, ATH_DBG_FATAL, "Reading Magic # failed\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!ath9k_hw_use_flash(ah)) {
|
||||
DPRINTF(ah, ATH_DBG_EEPROM,
|
||||
ath_print(common, ATH_DBG_EEPROM,
|
||||
"Read Magic = 0x%04X\n", magic);
|
||||
|
||||
if (magic != AR5416_EEPROM_MAGIC) {
|
||||
|
@ -137,7 +139,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
|
|||
eepdata++;
|
||||
}
|
||||
} else {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Invalid EEPROM Magic. "
|
||||
"Endianness mismatch.\n");
|
||||
return -EINVAL;
|
||||
|
@ -145,7 +147,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
|
|||
}
|
||||
}
|
||||
|
||||
DPRINTF(ah, ATH_DBG_EEPROM, "need_swap = %s.\n",
|
||||
ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
|
||||
need_swap ? "True" : "False");
|
||||
|
||||
if (need_swap)
|
||||
|
@ -167,7 +169,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
|
|||
u32 integer, j;
|
||||
u16 word;
|
||||
|
||||
DPRINTF(ah, ATH_DBG_EEPROM,
|
||||
ath_print(common, ATH_DBG_EEPROM,
|
||||
"EEPROM Endianness is not native.. Changing.\n");
|
||||
|
||||
word = swab16(eep->baseEepHeader.length);
|
||||
|
@ -214,7 +216,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
|
|||
|
||||
if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
|
||||
ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Bad EEPROM checksum 0x%x or revision 0x%04x\n",
|
||||
sum, ah->eep_ops->get_eeprom_ver(ah));
|
||||
return -EINVAL;
|
||||
|
@ -746,7 +748,7 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
|
|||
#define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
|
||||
#define SM_PDGAIN_B(x, y) \
|
||||
SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
|
||||
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
|
||||
struct cal_data_per_freq *pRawDataset;
|
||||
u8 *pCalBChans = NULL;
|
||||
|
@ -870,11 +872,11 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
|
|||
((pdadcValues[4 * j + 3] & 0xFF) << 24);
|
||||
REG_WRITE(ah, regOffset, reg32);
|
||||
|
||||
DPRINTF(ah, ATH_DBG_EEPROM,
|
||||
ath_print(common, ATH_DBG_EEPROM,
|
||||
"PDADC (%d,%4x): %4.4x %8.8x\n",
|
||||
i, regChainOffset, regOffset,
|
||||
reg32);
|
||||
DPRINTF(ah, ATH_DBG_EEPROM,
|
||||
ath_print(common, ATH_DBG_EEPROM,
|
||||
"PDADC: Chain %d | PDADC %3d "
|
||||
"Value %3d | PDADC %3d Value %3d | "
|
||||
"PDADC %3d Value %3d | PDADC %3d "
|
||||
|
@ -1311,7 +1313,7 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
|
|||
regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
|
||||
break;
|
||||
default:
|
||||
DPRINTF(ah, ATH_DBG_EEPROM,
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_EEPROM,
|
||||
"Invalid chainmask configuration\n");
|
||||
break;
|
||||
}
|
||||
|
@ -1349,10 +1351,11 @@ static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
|
|||
{
|
||||
#define EEP_DEF_SPURCHAN \
|
||||
(ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
|
||||
u16 spur_val = AR_NO_SPUR;
|
||||
|
||||
DPRINTF(ah, ATH_DBG_ANI,
|
||||
ath_print(common, ATH_DBG_ANI,
|
||||
"Getting spur idx %d is2Ghz. %d val %x\n",
|
||||
i, is2GHz, ah->config.spurchans[i][is2GHz]);
|
||||
|
||||
|
@ -1361,7 +1364,7 @@ static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
|
|||
break;
|
||||
case SPUR_ENABLE_IOCTL:
|
||||
spur_val = ah->config.spurchans[i][is2GHz];
|
||||
DPRINTF(ah, ATH_DBG_ANI,
|
||||
ath_print(common, ATH_DBG_ANI,
|
||||
"Getting spur val from new loc. %d\n", spur_val);
|
||||
break;
|
||||
case SPUR_ENABLE_EEPROM:
|
||||
|
|
|
@ -94,7 +94,7 @@ bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
|
|||
udelay(AH_TIME_QUANTUM);
|
||||
}
|
||||
|
||||
DPRINTF(ah, ATH_DBG_ANY,
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
|
||||
"timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
|
||||
timeout, reg, REG_READ(ah, reg), mask, val);
|
||||
|
||||
|
@ -178,7 +178,7 @@ u16 ath9k_hw_computetxtime(struct ath_hw *ah,
|
|||
}
|
||||
break;
|
||||
default:
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
|
||||
"Unknown phy %u (rate ix %u)\n",
|
||||
rates->info[rateix].phy, rateix);
|
||||
txTime = 0;
|
||||
|
@ -285,6 +285,7 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
|
|||
|
||||
static bool ath9k_hw_chip_test(struct ath_hw *ah)
|
||||
{
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
|
||||
u32 regHold[2];
|
||||
u32 patternData[4] = { 0x55555555,
|
||||
|
@ -303,9 +304,10 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
|
|||
REG_WRITE(ah, addr, wrData);
|
||||
rdData = REG_READ(ah, addr);
|
||||
if (rdData != wrData) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"address test failed "
|
||||
"addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
|
||||
"addr: 0x%08x - wr:0x%08x != "
|
||||
"rd:0x%08x\n",
|
||||
addr, wrData, rdData);
|
||||
return false;
|
||||
}
|
||||
|
@ -315,9 +317,10 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
|
|||
REG_WRITE(ah, addr, wrData);
|
||||
rdData = REG_READ(ah, addr);
|
||||
if (wrData != rdData) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"address test failed "
|
||||
"addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
|
||||
"addr: 0x%08x - wr:0x%08x != "
|
||||
"rd:0x%08x\n",
|
||||
addr, wrData, rdData);
|
||||
return false;
|
||||
}
|
||||
|
@ -440,7 +443,7 @@ static int ath9k_hw_rfattach(struct ath_hw *ah)
|
|||
|
||||
rfStatus = ath9k_hw_init_rf(ah, &ecode);
|
||||
if (!rfStatus) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
|
||||
"RF setup failed, status: %u\n", ecode);
|
||||
return ecode;
|
||||
}
|
||||
|
@ -465,7 +468,7 @@ static int ath9k_hw_rf_claim(struct ath_hw *ah)
|
|||
case AR_RAD2122_SREV_MAJOR:
|
||||
break;
|
||||
default:
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
|
||||
"Radio Chip Rev 0x%02X not supported\n",
|
||||
val & AR_RADIO_SREV_MAJOR);
|
||||
return -EOPNOTSUPP;
|
||||
|
@ -559,8 +562,10 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
|
|||
if (ecode != 0)
|
||||
return ecode;
|
||||
|
||||
DPRINTF(ah, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
|
||||
ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
|
||||
"Eeprom VER: %d, REV: %d\n",
|
||||
ah->eep_ops->get_eeprom_ver(ah),
|
||||
ah->eep_ops->get_eeprom_rev(ah));
|
||||
|
||||
ecode = ath9k_hw_rfattach(ah);
|
||||
if (ecode != 0)
|
||||
|
@ -874,6 +879,7 @@ static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
|
|||
|
||||
int ath9k_hw_init(struct ath_hw *ah)
|
||||
{
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
int r = 0;
|
||||
|
||||
if (!ath9k_hw_devid_supported(ah->hw_version.devid))
|
||||
|
@ -883,12 +889,13 @@ int ath9k_hw_init(struct ath_hw *ah)
|
|||
ath9k_hw_init_config(ah);
|
||||
|
||||
if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL, "Couldn't reset chip\n");
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Couldn't reset chip\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
|
||||
ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
|
@ -903,11 +910,11 @@ int ath9k_hw_init(struct ath_hw *ah)
|
|||
}
|
||||
}
|
||||
|
||||
DPRINTF(ah, ATH_DBG_RESET, "serialize_regmode is %d\n",
|
||||
ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
|
||||
ah->config.serialize_regmode);
|
||||
|
||||
if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Mac Chip Rev 0x%02x.%x is not supported by "
|
||||
"this driver\n", ah->hw_version.macVersion,
|
||||
ah->hw_version.macRev);
|
||||
|
@ -948,7 +955,7 @@ int ath9k_hw_init(struct ath_hw *ah)
|
|||
|
||||
r = ath9k_hw_init_macaddr(ah);
|
||||
if (r) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Failed to initialize MAC address\n");
|
||||
return r;
|
||||
}
|
||||
|
@ -1133,7 +1140,8 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
|
|||
static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
|
||||
{
|
||||
if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
|
||||
DPRINTF(ah, ATH_DBG_RESET, "bad ack timeout %u\n", us);
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
|
||||
"bad ack timeout %u\n", us);
|
||||
ah->acktimeout = (u32) -1;
|
||||
return false;
|
||||
} else {
|
||||
|
@ -1147,7 +1155,8 @@ static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
|
|||
static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
|
||||
{
|
||||
if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
|
||||
DPRINTF(ah, ATH_DBG_RESET, "bad cts timeout %u\n", us);
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
|
||||
"bad cts timeout %u\n", us);
|
||||
ah->ctstimeout = (u32) -1;
|
||||
return false;
|
||||
} else {
|
||||
|
@ -1161,7 +1170,7 @@ static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
|
|||
static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
|
||||
{
|
||||
if (tu > 0xFFFF) {
|
||||
DPRINTF(ah, ATH_DBG_XMIT,
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
|
||||
"bad global tx timeout %u\n", tu);
|
||||
ah->globaltxtimeout = (u32) -1;
|
||||
return false;
|
||||
|
@ -1174,7 +1183,7 @@ static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
|
|||
|
||||
static void ath9k_hw_init_user_settings(struct ath_hw *ah)
|
||||
{
|
||||
DPRINTF(ah, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
|
||||
ah->misc_mode);
|
||||
|
||||
if (ah->misc_mode != 0)
|
||||
|
@ -1267,27 +1276,28 @@ static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
|
|||
u32 reg, u32 value)
|
||||
{
|
||||
struct base_eep_header *pBase = &(pEepData->baseEepHeader);
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
|
||||
switch (ah->hw_version.devid) {
|
||||
case AR9280_DEVID_PCI:
|
||||
if (reg == 0x7894) {
|
||||
DPRINTF(ah, ATH_DBG_EEPROM,
|
||||
ath_print(common, ATH_DBG_EEPROM,
|
||||
"ini VAL: %x EEPROM: %x\n", value,
|
||||
(pBase->version & 0xff));
|
||||
|
||||
if ((pBase->version & 0xff) > 0x0a) {
|
||||
DPRINTF(ah, ATH_DBG_EEPROM,
|
||||
ath_print(common, ATH_DBG_EEPROM,
|
||||
"PWDCLKIND: %d\n",
|
||||
pBase->pwdclkind);
|
||||
value &= ~AR_AN_TOP2_PWDCLKIND;
|
||||
value |= AR_AN_TOP2_PWDCLKIND &
|
||||
(pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
|
||||
} else {
|
||||
DPRINTF(ah, ATH_DBG_EEPROM,
|
||||
ath_print(common, ATH_DBG_EEPROM,
|
||||
"PWDCLKIND Earlier Rev\n");
|
||||
}
|
||||
|
||||
DPRINTF(ah, ATH_DBG_EEPROM,
|
||||
ath_print(common, ATH_DBG_EEPROM,
|
||||
"final ini VAL: %x\n", value);
|
||||
}
|
||||
break;
|
||||
|
@ -1460,7 +1470,7 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
|
|||
(u32) regulatory->power_limit));
|
||||
|
||||
if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
|
||||
"ar5416SetRfRegs failed\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
@ -1666,7 +1676,7 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
|
|||
|
||||
REG_WRITE(ah, AR_RTC_RC, 0);
|
||||
if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
|
||||
DPRINTF(ah, ATH_DBG_RESET,
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
|
||||
"RTC stuck in MAC reset\n");
|
||||
return false;
|
||||
}
|
||||
|
@ -1703,7 +1713,8 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
|
|||
AR_RTC_STATUS_M,
|
||||
AR_RTC_STATUS_ON,
|
||||
AH_WAIT_TIMEOUT)) {
|
||||
DPRINTF(ah, ATH_DBG_RESET, "RTC not waking up\n");
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
|
||||
"RTC not waking up\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
|
@ -1783,13 +1794,15 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
|
|||
enum ath9k_ht_macmode macmode)
|
||||
{
|
||||
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
struct ieee80211_channel *channel = chan->chan;
|
||||
u32 synthDelay, qnum;
|
||||
|
||||
for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
|
||||
if (ath9k_hw_numtxpending(ah, qnum)) {
|
||||
DPRINTF(ah, ATH_DBG_QUEUE,
|
||||
"Transmit frames pending on queue %d\n", qnum);
|
||||
ath_print(common, ATH_DBG_QUEUE,
|
||||
"Transmit frames pending on "
|
||||
"queue %d\n", qnum);
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
@ -1797,7 +1810,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
|
|||
REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
|
||||
if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
|
||||
AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Could not kill baseband RX\n");
|
||||
return false;
|
||||
}
|
||||
|
@ -1808,7 +1821,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
|
|||
ath9k_hw_ar9280_set_channel(ah, chan);
|
||||
} else {
|
||||
if (!(ath9k_hw_set_channel(ah, chan))) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Failed to set channel\n");
|
||||
return false;
|
||||
}
|
||||
|
@ -2370,7 +2383,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
|
|||
}
|
||||
|
||||
if (!ath9k_hw_chip_reset(ah, chan)) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL, "Chip reset failed\n");
|
||||
ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
@ -2525,13 +2538,13 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
|
|||
u32 mask;
|
||||
mask = REG_READ(ah, AR_CFG);
|
||||
if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
|
||||
DPRINTF(ah, ATH_DBG_RESET,
|
||||
ath_print(common, ATH_DBG_RESET,
|
||||
"CFG Byte Swap Set 0x%x\n", mask);
|
||||
} else {
|
||||
mask =
|
||||
INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
|
||||
REG_WRITE(ah, AR_CFG, mask);
|
||||
DPRINTF(ah, ATH_DBG_RESET,
|
||||
ath_print(common, ATH_DBG_RESET,
|
||||
"Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
|
||||
}
|
||||
} else {
|
||||
|
@ -2559,7 +2572,7 @@ bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
|
|||
u32 keyType;
|
||||
|
||||
if (entry >= ah->caps.keycache_size) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
|
||||
"keychache entry %u out of range\n", entry);
|
||||
return false;
|
||||
}
|
||||
|
@ -2593,7 +2606,7 @@ bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
|
|||
u32 macHi, macLo;
|
||||
|
||||
if (entry >= ah->caps.keycache_size) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
|
||||
"keychache entry %u out of range\n", entry);
|
||||
return false;
|
||||
}
|
||||
|
@ -2621,11 +2634,12 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
|
|||
const u8 *mac)
|
||||
{
|
||||
const struct ath9k_hw_capabilities *pCap = &ah->caps;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
u32 key0, key1, key2, key3, key4;
|
||||
u32 keyType;
|
||||
|
||||
if (entry >= pCap->keycache_size) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"keycache entry %u out of range\n", entry);
|
||||
return false;
|
||||
}
|
||||
|
@ -2636,7 +2650,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
|
|||
break;
|
||||
case ATH9K_CIPHER_AES_CCM:
|
||||
if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
|
||||
DPRINTF(ah, ATH_DBG_ANY,
|
||||
ath_print(common, ATH_DBG_ANY,
|
||||
"AES-CCM not supported by mac rev 0x%x\n",
|
||||
ah->hw_version.macRev);
|
||||
return false;
|
||||
|
@ -2647,14 +2661,14 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
|
|||
keyType = AR_KEYTABLE_TYPE_TKIP;
|
||||
if (ATH9K_IS_MIC_ENABLED(ah)
|
||||
&& entry + 64 >= pCap->keycache_size) {
|
||||
DPRINTF(ah, ATH_DBG_ANY,
|
||||
ath_print(common, ATH_DBG_ANY,
|
||||
"entry %u inappropriate for TKIP\n", entry);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case ATH9K_CIPHER_WEP:
|
||||
if (k->kv_len < WLAN_KEY_LEN_WEP40) {
|
||||
DPRINTF(ah, ATH_DBG_ANY,
|
||||
ath_print(common, ATH_DBG_ANY,
|
||||
"WEP key length %u too small\n", k->kv_len);
|
||||
return false;
|
||||
}
|
||||
|
@ -2669,7 +2683,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
|
|||
keyType = AR_KEYTABLE_TYPE_CLR;
|
||||
break;
|
||||
default:
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"cipher %u not supported\n", k->kv_type);
|
||||
return false;
|
||||
}
|
||||
|
@ -2887,8 +2901,9 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
|
|||
AR_RTC_FORCE_WAKE_EN);
|
||||
}
|
||||
if (i == 0) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
"Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
|
||||
"Failed to wakeup in %uus\n",
|
||||
POWER_UP_TIME / 20);
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
@ -2900,6 +2915,7 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
|
|||
|
||||
bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
|
||||
{
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
int status = true, setChip = true;
|
||||
static const char *modes[] = {
|
||||
"AWAKE",
|
||||
|
@ -2911,7 +2927,7 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
|
|||
if (ah->power_mode == mode)
|
||||
return status;
|
||||
|
||||
DPRINTF(ah, ATH_DBG_RESET, "%s -> %s\n",
|
||||
ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
|
||||
modes[ah->power_mode], modes[mode]);
|
||||
|
||||
switch (mode) {
|
||||
|
@ -2926,7 +2942,7 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
|
|||
ath9k_set_power_network_sleep(ah, setChip);
|
||||
break;
|
||||
default:
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Unknown power mode %u\n", mode);
|
||||
return false;
|
||||
}
|
||||
|
@ -3097,6 +3113,7 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
|
|||
struct ath9k_hw_capabilities *pCap = &ah->caps;
|
||||
u32 sync_cause = 0;
|
||||
bool fatal_int = false;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
|
||||
if (!AR_SREV_9100(ah)) {
|
||||
if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
|
||||
|
@ -3170,7 +3187,7 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
|
|||
}
|
||||
|
||||
if (isr & AR_ISR_RXORN) {
|
||||
DPRINTF(ah, ATH_DBG_INTERRUPT,
|
||||
ath_print(common, ATH_DBG_INTERRUPT,
|
||||
"receive FIFO overrun interrupt\n");
|
||||
}
|
||||
|
||||
|
@ -3213,24 +3230,24 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
|
|||
|
||||
if (fatal_int) {
|
||||
if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
|
||||
DPRINTF(ah, ATH_DBG_ANY,
|
||||
ath_print(common, ATH_DBG_ANY,
|
||||
"received PCI FATAL interrupt\n");
|
||||
}
|
||||
if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
|
||||
DPRINTF(ah, ATH_DBG_ANY,
|
||||
ath_print(common, ATH_DBG_ANY,
|
||||
"received PCI PERR interrupt\n");
|
||||
}
|
||||
*masked |= ATH9K_INT_FATAL;
|
||||
}
|
||||
if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
|
||||
DPRINTF(ah, ATH_DBG_INTERRUPT,
|
||||
ath_print(common, ATH_DBG_INTERRUPT,
|
||||
"AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
|
||||
REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
|
||||
REG_WRITE(ah, AR_RC, 0);
|
||||
*masked |= ATH9K_INT_FATAL;
|
||||
}
|
||||
if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
|
||||
DPRINTF(ah, ATH_DBG_INTERRUPT,
|
||||
ath_print(common, ATH_DBG_INTERRUPT,
|
||||
"AR_INTR_SYNC_LOCAL_TIMEOUT\n");
|
||||
}
|
||||
|
||||
|
@ -3246,11 +3263,12 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
|
|||
u32 omask = ah->mask_reg;
|
||||
u32 mask, mask2;
|
||||
struct ath9k_hw_capabilities *pCap = &ah->caps;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
|
||||
DPRINTF(ah, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
|
||||
ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
|
||||
|
||||
if (omask & ATH9K_INT_GLOBAL) {
|
||||
DPRINTF(ah, ATH_DBG_INTERRUPT, "disable IER\n");
|
||||
ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
|
||||
REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
|
||||
(void) REG_READ(ah, AR_IER);
|
||||
if (!AR_SREV_9100(ah)) {
|
||||
|
@ -3307,7 +3325,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
|
|||
mask2 |= AR_IMR_S2_CST;
|
||||
}
|
||||
|
||||
DPRINTF(ah, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
|
||||
ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
|
||||
REG_WRITE(ah, AR_IMR, mask);
|
||||
mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
|
||||
AR_IMR_S2_DTIM |
|
||||
|
@ -3327,7 +3345,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
|
|||
}
|
||||
|
||||
if (ints & ATH9K_INT_GLOBAL) {
|
||||
DPRINTF(ah, ATH_DBG_INTERRUPT, "enable IER\n");
|
||||
ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
|
||||
REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
|
||||
if (!AR_SREV_9100(ah)) {
|
||||
REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
|
||||
|
@ -3340,7 +3358,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
|
|||
REG_WRITE(ah, AR_INTR_SYNC_MASK,
|
||||
AR_INTR_SYNC_DEFAULT);
|
||||
}
|
||||
DPRINTF(ah, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
|
||||
ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
|
||||
REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
|
||||
}
|
||||
|
||||
|
@ -3388,7 +3406,7 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
|
|||
AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
|
||||
break;
|
||||
default:
|
||||
DPRINTF(ah, ATH_DBG_BEACON,
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
|
||||
"%s: unsupported opmode: %d\n",
|
||||
__func__, ah->opmode);
|
||||
return;
|
||||
|
@ -3414,6 +3432,7 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
|
|||
{
|
||||
u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
|
||||
struct ath9k_hw_capabilities *pCap = &ah->caps;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
|
||||
REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
|
||||
|
||||
|
@ -3439,10 +3458,10 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
|
|||
else
|
||||
nextTbtt = bs->bs_nexttbtt;
|
||||
|
||||
DPRINTF(ah, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
|
||||
DPRINTF(ah, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
|
||||
DPRINTF(ah, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
|
||||
DPRINTF(ah, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
|
||||
ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
|
||||
ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
|
||||
ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
|
||||
ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
|
||||
|
||||
REG_WRITE(ah, AR_NEXT_DTIM,
|
||||
TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
|
||||
|
@ -3479,6 +3498,7 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah)
|
|||
{
|
||||
struct ath9k_hw_capabilities *pCap = &ah->caps;
|
||||
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
|
||||
|
||||
u16 capField = 0, eeval;
|
||||
|
@ -3500,7 +3520,7 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah)
|
|||
regulatory->current_rd += 5;
|
||||
else if (regulatory->current_rd == 0x41)
|
||||
regulatory->current_rd = 0x43;
|
||||
DPRINTF(ah, ATH_DBG_REGULATORY,
|
||||
ath_print(common, ATH_DBG_REGULATORY,
|
||||
"regdomain mapped to 0x%x\n", regulatory->current_rd);
|
||||
}
|
||||
|
||||
|
@ -4019,7 +4039,7 @@ void ath9k_hw_reset_tsf(struct ath_hw *ah)
|
|||
{
|
||||
if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
|
||||
AH_TSF_WRITE_TIMEOUT))
|
||||
DPRINTF(ah, ATH_DBG_RESET,
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
|
||||
"AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
|
||||
|
||||
REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
|
||||
|
@ -4036,7 +4056,8 @@ void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
|
|||
bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
|
||||
{
|
||||
if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
|
||||
DPRINTF(ah, ATH_DBG_RESET, "bad slot time %u\n", us);
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
|
||||
"bad slot time %u\n", us);
|
||||
ah->slottime = (u32) -1;
|
||||
return false;
|
||||
} else {
|
||||
|
@ -4121,7 +4142,8 @@ struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
|
|||
timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
|
||||
|
||||
if (timer == NULL) {
|
||||
printk(KERN_DEBUG "Failed to allocate memory"
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
|
||||
"Failed to allocate memory"
|
||||
"for hw timer[%d]\n", timer_index);
|
||||
return NULL;
|
||||
}
|
||||
|
@ -4150,7 +4172,8 @@ void ath9k_hw_gen_timer_start(struct ath_hw *ah,
|
|||
|
||||
tsf = ath9k_hw_gettsf32(ah);
|
||||
|
||||
DPRINTF(ah, ATH_DBG_HWTIMER, "curent tsf %x period %x"
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
|
||||
"curent tsf %x period %x"
|
||||
"timer_next %x\n", tsf, timer_period, timer_next);
|
||||
|
||||
/*
|
||||
|
@ -4213,6 +4236,7 @@ void ath_gen_timer_isr(struct ath_hw *ah)
|
|||
{
|
||||
struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
|
||||
struct ath_gen_timer *timer;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
u32 trigger_mask, thresh_mask, index;
|
||||
|
||||
/* get hardware generic timer interrupt status */
|
||||
|
@ -4227,7 +4251,7 @@ void ath_gen_timer_isr(struct ath_hw *ah)
|
|||
index = rightmost_index(timer_table, &thresh_mask);
|
||||
timer = timer_table->timers[index];
|
||||
BUG_ON(!timer);
|
||||
DPRINTF(ah, ATH_DBG_HWTIMER,
|
||||
ath_print(common, ATH_DBG_HWTIMER,
|
||||
"TSF overflow for Gen timer %d\n", index);
|
||||
timer->overflow(timer->arg);
|
||||
}
|
||||
|
@ -4236,7 +4260,7 @@ void ath_gen_timer_isr(struct ath_hw *ah)
|
|||
index = rightmost_index(timer_table, &trigger_mask);
|
||||
timer = timer_table->timers[index];
|
||||
BUG_ON(!timer);
|
||||
DPRINTF(ah, ATH_DBG_HWTIMER,
|
||||
ath_print(common, ATH_DBG_HWTIMER,
|
||||
"Gen timer[%d] trigger\n", index);
|
||||
timer->trigger(timer->arg);
|
||||
}
|
||||
|
|
|
@ -30,6 +30,7 @@
|
|||
#include "btcoex.h"
|
||||
|
||||
#include "../regd.h"
|
||||
#include "../debug.h"
|
||||
|
||||
#define ATHEROS_VENDOR_ID 0x168c
|
||||
#define AR5416_DEVID_PCI 0x0023
|
||||
|
|
|
@ -15,11 +15,12 @@
|
|||
*/
|
||||
|
||||
#include "ath9k.h"
|
||||
#include "hw.h"
|
||||
|
||||
static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
|
||||
struct ath9k_tx_queue_info *qi)
|
||||
{
|
||||
DPRINTF(ah, ATH_DBG_INTERRUPT,
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_INTERRUPT,
|
||||
"tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
|
||||
ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
|
||||
ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
|
||||
|
@ -47,7 +48,8 @@ void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
|
|||
|
||||
void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
|
||||
{
|
||||
DPRINTF(ah, ATH_DBG_QUEUE, "Enable TXE on queue: %u\n", q);
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_QUEUE,
|
||||
"Enable TXE on queue: %u\n", q);
|
||||
REG_WRITE(ah, AR_Q_TXE, 1 << q);
|
||||
}
|
||||
|
||||
|
@ -98,21 +100,21 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
|
|||
{
|
||||
#define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */
|
||||
#define ATH9K_TIME_QUANTUM 100 /* usec */
|
||||
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
struct ath9k_hw_capabilities *pCap = &ah->caps;
|
||||
struct ath9k_tx_queue_info *qi;
|
||||
u32 tsfLow, j, wait;
|
||||
u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
|
||||
|
||||
if (q >= pCap->total_queues) {
|
||||
DPRINTF(ah, ATH_DBG_QUEUE, "Stopping TX DMA, "
|
||||
ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
|
||||
"invalid queue: %u\n", q);
|
||||
return false;
|
||||
}
|
||||
|
||||
qi = &ah->txq[q];
|
||||
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
|
||||
DPRINTF(ah, ATH_DBG_QUEUE, "Stopping TX DMA, "
|
||||
ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
|
||||
"inactive queue: %u\n", q);
|
||||
return false;
|
||||
}
|
||||
|
@ -126,7 +128,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
|
|||
}
|
||||
|
||||
if (ath9k_hw_numtxpending(ah, q)) {
|
||||
DPRINTF(ah, ATH_DBG_QUEUE,
|
||||
ath_print(common, ATH_DBG_QUEUE,
|
||||
"%s: Num of pending TX Frames %d on Q %d\n",
|
||||
__func__, ath9k_hw_numtxpending(ah, q), q);
|
||||
|
||||
|
@ -142,7 +144,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
|
|||
if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))
|
||||
break;
|
||||
|
||||
DPRINTF(ah, ATH_DBG_QUEUE,
|
||||
ath_print(common, ATH_DBG_QUEUE,
|
||||
"TSF has moved while trying to set "
|
||||
"quiet time TSF: 0x%08x\n", tsfLow);
|
||||
}
|
||||
|
@ -155,7 +157,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
|
|||
wait = wait_time;
|
||||
while (ath9k_hw_numtxpending(ah, q)) {
|
||||
if ((--wait) == 0) {
|
||||
DPRINTF(ah, ATH_DBG_QUEUE,
|
||||
ath_print(common, ATH_DBG_QUEUE,
|
||||
"Failed to stop TX DMA in 100 "
|
||||
"msec after killing last frame\n");
|
||||
break;
|
||||
|
@ -445,23 +447,24 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
|
|||
const struct ath9k_tx_queue_info *qinfo)
|
||||
{
|
||||
u32 cw;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
struct ath9k_hw_capabilities *pCap = &ah->caps;
|
||||
struct ath9k_tx_queue_info *qi;
|
||||
|
||||
if (q >= pCap->total_queues) {
|
||||
DPRINTF(ah, ATH_DBG_QUEUE, "Set TXQ properties, "
|
||||
ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
|
||||
"invalid queue: %u\n", q);
|
||||
return false;
|
||||
}
|
||||
|
||||
qi = &ah->txq[q];
|
||||
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
|
||||
DPRINTF(ah, ATH_DBG_QUEUE, "Set TXQ properties, "
|
||||
ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
|
||||
"inactive queue: %u\n", q);
|
||||
return false;
|
||||
}
|
||||
|
||||
DPRINTF(ah, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
|
||||
ath_print(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
|
||||
|
||||
qi->tqi_ver = qinfo->tqi_ver;
|
||||
qi->tqi_subtype = qinfo->tqi_subtype;
|
||||
|
@ -514,18 +517,19 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
|
|||
bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
|
||||
struct ath9k_tx_queue_info *qinfo)
|
||||
{
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
struct ath9k_hw_capabilities *pCap = &ah->caps;
|
||||
struct ath9k_tx_queue_info *qi;
|
||||
|
||||
if (q >= pCap->total_queues) {
|
||||
DPRINTF(ah, ATH_DBG_QUEUE, "Get TXQ properties, "
|
||||
ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
|
||||
"invalid queue: %u\n", q);
|
||||
return false;
|
||||
}
|
||||
|
||||
qi = &ah->txq[q];
|
||||
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
|
||||
DPRINTF(ah, ATH_DBG_QUEUE, "Get TXQ properties, "
|
||||
ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
|
||||
"inactive queue: %u\n", q);
|
||||
return false;
|
||||
}
|
||||
|
@ -551,6 +555,7 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
|
|||
int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
|
||||
const struct ath9k_tx_queue_info *qinfo)
|
||||
{
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
struct ath9k_tx_queue_info *qi;
|
||||
struct ath9k_hw_capabilities *pCap = &ah->caps;
|
||||
int q;
|
||||
|
@ -574,22 +579,22 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
|
|||
ATH9K_TX_QUEUE_INACTIVE)
|
||||
break;
|
||||
if (q == pCap->total_queues) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"No available TX queue\n");
|
||||
return -1;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
DPRINTF(ah, ATH_DBG_FATAL, "Invalid TX queue type: %u\n",
|
||||
type);
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Invalid TX queue type: %u\n", type);
|
||||
return -1;
|
||||
}
|
||||
|
||||
DPRINTF(ah, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
|
||||
ath_print(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
|
||||
|
||||
qi = &ah->txq[q];
|
||||
if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"TX queue: %u already active\n", q);
|
||||
return -1;
|
||||
}
|
||||
|
@ -617,21 +622,22 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
|
|||
bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
|
||||
{
|
||||
struct ath9k_hw_capabilities *pCap = &ah->caps;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
struct ath9k_tx_queue_info *qi;
|
||||
|
||||
if (q >= pCap->total_queues) {
|
||||
DPRINTF(ah, ATH_DBG_QUEUE, "Release TXQ, "
|
||||
ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
|
||||
"invalid queue: %u\n", q);
|
||||
return false;
|
||||
}
|
||||
qi = &ah->txq[q];
|
||||
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
|
||||
DPRINTF(ah, ATH_DBG_QUEUE, "Release TXQ, "
|
||||
ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
|
||||
"inactive queue: %u\n", q);
|
||||
return false;
|
||||
}
|
||||
|
||||
DPRINTF(ah, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
|
||||
ath_print(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
|
||||
|
||||
qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
|
||||
ah->txok_interrupt_mask &= ~(1 << q);
|
||||
|
@ -647,24 +653,25 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
|
|||
bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
|
||||
{
|
||||
struct ath9k_hw_capabilities *pCap = &ah->caps;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
struct ath9k_channel *chan = ah->curchan;
|
||||
struct ath9k_tx_queue_info *qi;
|
||||
u32 cwMin, chanCwMin, value;
|
||||
|
||||
if (q >= pCap->total_queues) {
|
||||
DPRINTF(ah, ATH_DBG_QUEUE, "Reset TXQ, "
|
||||
ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
|
||||
"invalid queue: %u\n", q);
|
||||
return false;
|
||||
}
|
||||
|
||||
qi = &ah->txq[q];
|
||||
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
|
||||
DPRINTF(ah, ATH_DBG_QUEUE, "Reset TXQ, "
|
||||
ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
|
||||
"inactive queue: %u\n", q);
|
||||
return true;
|
||||
}
|
||||
|
||||
DPRINTF(ah, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
|
||||
ath_print(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
|
||||
|
||||
if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
|
||||
if (chan && IS_CHAN_B(chan))
|
||||
|
@ -911,8 +918,9 @@ bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
|
|||
AR_DIAG_RX_ABORT));
|
||||
|
||||
reg = REG_READ(ah, AR_OBS_BUS_1);
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
"RX failed to go idle in 10 ms RXSM=0x%x\n", reg);
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
|
||||
"RX failed to go idle in 10 ms RXSM=0x%x\n",
|
||||
reg);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
@ -954,7 +962,7 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
|
|||
{
|
||||
#define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
|
||||
#define AH_RX_TIME_QUANTUM 100 /* usec */
|
||||
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
int i;
|
||||
|
||||
REG_WRITE(ah, AR_CR, AR_CR_RXD);
|
||||
|
@ -967,7 +975,7 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
|
|||
}
|
||||
|
||||
if (i == 0) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"DMA failed to stop in %d ms "
|
||||
"AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
|
||||
AH_RX_STOP_DMA_TIMEOUT / 1000,
|
||||
|
|
|
@ -225,7 +225,8 @@ static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
|
|||
}
|
||||
sband->n_bitrates++;
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
|
||||
ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
|
||||
"Rate: %2dMbps, ratecode: %2d\n",
|
||||
rate[i].bitrate / 10, rate[i].hw_value);
|
||||
}
|
||||
}
|
||||
|
@ -297,6 +298,7 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
|
|||
struct ath9k_channel *hchan)
|
||||
{
|
||||
struct ath_hw *ah = sc->sc_ah;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
bool fastcc = true, stopped;
|
||||
struct ieee80211_channel *channel = hw->conf.channel;
|
||||
int r;
|
||||
|
@ -326,7 +328,7 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
|
|||
if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
|
||||
fastcc = false;
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
|
||||
ath_print(common, ATH_DBG_CONFIG,
|
||||
"(%u MHz) -> (%u MHz), chanwidth: %d\n",
|
||||
sc->sc_ah->curchan->channel,
|
||||
channel->center_freq, sc->tx_chan_width);
|
||||
|
@ -335,7 +337,7 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
|
|||
|
||||
r = ath9k_hw_reset(ah, hchan, fastcc);
|
||||
if (r) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Unable to reset channel (%u Mhz) "
|
||||
"reset status %d\n",
|
||||
channel->center_freq, r);
|
||||
|
@ -347,7 +349,7 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
|
|||
sc->sc_flags &= ~SC_OP_FULL_RESET;
|
||||
|
||||
if (ath_startrecv(sc) != 0) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Unable to restart recv logic\n");
|
||||
r = -EIO;
|
||||
goto ps_restore;
|
||||
|
@ -373,6 +375,7 @@ static void ath_ani_calibrate(unsigned long data)
|
|||
{
|
||||
struct ath_softc *sc = (struct ath_softc *)data;
|
||||
struct ath_hw *ah = sc->sc_ah;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
bool longcal = false;
|
||||
bool shortcal = false;
|
||||
bool aniflag = false;
|
||||
|
@ -399,7 +402,7 @@ static void ath_ani_calibrate(unsigned long data)
|
|||
/* Long calibration runs independently of short calibration. */
|
||||
if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
|
||||
longcal = true;
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
|
||||
ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
|
||||
sc->ani.longcal_timer = timestamp;
|
||||
}
|
||||
|
||||
|
@ -407,7 +410,8 @@ static void ath_ani_calibrate(unsigned long data)
|
|||
if (!sc->ani.caldone) {
|
||||
if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
|
||||
shortcal = true;
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
|
||||
ath_print(common, ATH_DBG_ANI,
|
||||
"shortcal @%lu\n", jiffies);
|
||||
sc->ani.shortcal_timer = timestamp;
|
||||
sc->ani.resetcal_timer = timestamp;
|
||||
}
|
||||
|
@ -441,8 +445,10 @@ static void ath_ani_calibrate(unsigned long data)
|
|||
sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
|
||||
ah->curchan);
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
|
||||
ah->curchan->channel, ah->curchan->channelFlags,
|
||||
ath_print(common, ATH_DBG_ANI,
|
||||
" calibrate chan %u/%x nf: %d\n",
|
||||
ah->curchan->channel,
|
||||
ah->curchan->channelFlags,
|
||||
sc->ani.noise_floor);
|
||||
}
|
||||
}
|
||||
|
@ -496,7 +502,8 @@ void ath_update_chainmask(struct ath_softc *sc, int is_ht)
|
|||
sc->rx_chainmask = 1;
|
||||
}
|
||||
|
||||
DPRINTF(ah, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
|
||||
"tx chmask: %d, rx chmask: %d\n",
|
||||
sc->tx_chainmask, sc->rx_chainmask);
|
||||
}
|
||||
|
||||
|
@ -527,6 +534,7 @@ static void ath9k_tasklet(unsigned long data)
|
|||
{
|
||||
struct ath_softc *sc = (struct ath_softc *)data;
|
||||
struct ath_hw *ah = sc->sc_ah;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
|
||||
u32 status = sc->intrstatus;
|
||||
|
||||
|
@ -552,7 +560,8 @@ static void ath9k_tasklet(unsigned long data)
|
|||
* TSF sync does not look correct; remain awake to sync with
|
||||
* the next Beacon.
|
||||
*/
|
||||
DPRINTF(ah, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
|
||||
ath_print(common, ATH_DBG_PS,
|
||||
"TSFOOR - Sync with next Beacon\n");
|
||||
sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
|
||||
}
|
||||
|
||||
|
@ -752,7 +761,7 @@ static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
|
|||
memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
|
||||
if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
|
||||
/* TX MIC entry failed. No need to proceed further */
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
|
||||
ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
|
||||
"Setting TX MIC Key Failed\n");
|
||||
return 0;
|
||||
}
|
||||
|
@ -957,7 +966,8 @@ static void setup_ht_cap(struct ath_softc *sc,
|
|||
rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
|
||||
|
||||
if (tx_streams != rx_streams) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
|
||||
ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
|
||||
"TX streams %d, RX streams: %d\n",
|
||||
tx_streams, rx_streams);
|
||||
ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
|
||||
ht_info->mcs.tx_params |= ((tx_streams - 1) <<
|
||||
|
@ -979,7 +989,8 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
|
|||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
|
||||
if (bss_conf->assoc) {
|
||||
DPRINTF(ah, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
|
||||
ath_print(common, ATH_DBG_CONFIG,
|
||||
"Bss Info ASSOC %d, bssid: %pM\n",
|
||||
bss_conf->aid, common->curbssid);
|
||||
|
||||
/* New association, store aid */
|
||||
|
@ -1001,7 +1012,7 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
|
|||
|
||||
ath_start_ani(sc);
|
||||
} else {
|
||||
DPRINTF(ah, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
|
||||
ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
|
||||
common->curaid = 0;
|
||||
/* Stop ANI */
|
||||
del_timer_sync(&sc->ani.timer);
|
||||
|
@ -1094,7 +1105,7 @@ static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
|
|||
|
||||
ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
|
||||
if (ret)
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
|
||||
ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
|
||||
"Failed to register led:%s", led->name);
|
||||
else
|
||||
led->registered = 1;
|
||||
|
@ -1179,6 +1190,7 @@ fail:
|
|||
void ath_radio_enable(struct ath_softc *sc)
|
||||
{
|
||||
struct ath_hw *ah = sc->sc_ah;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
struct ieee80211_channel *channel = sc->hw->conf.channel;
|
||||
int r;
|
||||
|
||||
|
@ -1191,7 +1203,7 @@ void ath_radio_enable(struct ath_softc *sc)
|
|||
spin_lock_bh(&sc->sc_resetlock);
|
||||
r = ath9k_hw_reset(ah, ah->curchan, false);
|
||||
if (r) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Unable to reset channel %u (%uMhz) ",
|
||||
"reset status %d\n",
|
||||
channel->center_freq, r);
|
||||
|
@ -1200,7 +1212,7 @@ void ath_radio_enable(struct ath_softc *sc)
|
|||
|
||||
ath_update_txpow(sc);
|
||||
if (ath_startrecv(sc) != 0) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Unable to restart recv logic\n");
|
||||
return;
|
||||
}
|
||||
|
@ -1246,7 +1258,7 @@ void ath_radio_disable(struct ath_softc *sc)
|
|||
spin_lock_bh(&sc->sc_resetlock);
|
||||
r = ath9k_hw_reset(ah, ah->curchan, false);
|
||||
if (r) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
|
||||
ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
|
||||
"Unable to reset channel %u (%uMhz) "
|
||||
"reset status %d\n",
|
||||
channel->center_freq, r);
|
||||
|
@ -1367,7 +1379,7 @@ static void ath_detect_bt_priority(struct ath_softc *sc)
|
|||
if (time_after(jiffies, btcoex->bt_priority_time +
|
||||
msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
|
||||
if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_BTCOEX,
|
||||
ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
|
||||
"BT priority traffic detected");
|
||||
sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
|
||||
} else {
|
||||
|
@ -1401,7 +1413,8 @@ static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
|
|||
AR_STOMP_NONE_WLAN_WGHT);
|
||||
break;
|
||||
default:
|
||||
DPRINTF(ah, ATH_DBG_BTCOEX, "Invalid Stomptype\n");
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
|
||||
"Invalid Stomptype\n");
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -1481,7 +1494,8 @@ static void ath_btcoex_no_stomp_timer(void *arg)
|
|||
struct ath_hw *ah = sc->sc_ah;
|
||||
struct ath_btcoex *btcoex = &sc->btcoex;
|
||||
|
||||
DPRINTF(ah, ATH_DBG_BTCOEX, "no stomp timer running \n");
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
|
||||
"no stomp timer running \n");
|
||||
|
||||
spin_lock_bh(&btcoex->btcoex_lock);
|
||||
|
||||
|
@ -1614,7 +1628,7 @@ static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
|
|||
|
||||
r = ath9k_hw_init(ah);
|
||||
if (r) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Unable to initialize hardware; "
|
||||
"initialization status: %d\n", r);
|
||||
goto bad;
|
||||
|
@ -1623,7 +1637,7 @@ static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
|
|||
/* Get the hardware key cache size. */
|
||||
sc->keymax = ah->caps.keycache_size;
|
||||
if (sc->keymax > ATH_KEYMAX) {
|
||||
DPRINTF(ah, ATH_DBG_ANY,
|
||||
ath_print(common, ATH_DBG_ANY,
|
||||
"Warning, using only %u entries in %u key cache\n",
|
||||
ATH_KEYMAX, sc->keymax);
|
||||
sc->keymax = ATH_KEYMAX;
|
||||
|
@ -1653,14 +1667,14 @@ static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
|
|||
*/
|
||||
sc->beacon.beaconq = ath_beaconq_setup(ah);
|
||||
if (sc->beacon.beaconq == -1) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Unable to setup a beacon xmit queue\n");
|
||||
r = -EIO;
|
||||
goto bad2;
|
||||
}
|
||||
sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
|
||||
if (sc->beacon.cabq == NULL) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Unable to setup CAB xmit queue\n");
|
||||
r = -EIO;
|
||||
goto bad2;
|
||||
|
@ -1675,26 +1689,26 @@ static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
|
|||
/* Setup data queues */
|
||||
/* NB: ensure BK queue is the lowest priority h/w queue */
|
||||
if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Unable to setup xmit queue for BK traffic\n");
|
||||
r = -EIO;
|
||||
goto bad2;
|
||||
}
|
||||
|
||||
if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Unable to setup xmit queue for BE traffic\n");
|
||||
r = -EIO;
|
||||
goto bad2;
|
||||
}
|
||||
if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Unable to setup xmit queue for VI traffic\n");
|
||||
r = -EIO;
|
||||
goto bad2;
|
||||
}
|
||||
if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Unable to setup xmit queue for VO traffic\n");
|
||||
r = -EIO;
|
||||
goto bad2;
|
||||
|
@ -1933,6 +1947,7 @@ error_attach:
|
|||
int ath_reset(struct ath_softc *sc, bool retry_tx)
|
||||
{
|
||||
struct ath_hw *ah = sc->sc_ah;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
struct ieee80211_hw *hw = sc->hw;
|
||||
int r;
|
||||
|
||||
|
@ -1944,12 +1959,13 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
|
|||
spin_lock_bh(&sc->sc_resetlock);
|
||||
r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
|
||||
if (r)
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Unable to reset hardware; reset status %d\n", r);
|
||||
spin_unlock_bh(&sc->sc_resetlock);
|
||||
|
||||
if (ath_startrecv(sc) != 0)
|
||||
DPRINTF(ah, ATH_DBG_FATAL, "Unable to start recv logic\n");
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Unable to start recv logic\n");
|
||||
|
||||
/*
|
||||
* We may be doing a reset in response to a request
|
||||
|
@ -1992,18 +2008,19 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
|
|||
((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
|
||||
#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
|
||||
#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
|
||||
|
||||
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
||||
struct ath_desc *ds;
|
||||
struct ath_buf *bf;
|
||||
int i, bsize, error;
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
|
||||
ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
|
||||
name, nbuf, ndesc);
|
||||
|
||||
INIT_LIST_HEAD(head);
|
||||
/* ath_desc must be a multiple of DWORDs */
|
||||
if ((sizeof(struct ath_desc) % 4) != 0) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"ath_desc not DWORD aligned\n");
|
||||
ASSERT((sizeof(struct ath_desc) % 4) == 0);
|
||||
error = -ENOMEM;
|
||||
goto fail;
|
||||
|
@ -2037,7 +2054,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
|
|||
goto fail;
|
||||
}
|
||||
ds = dd->dd_desc;
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
|
||||
ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
|
||||
name, ds, (u32) dd->dd_desc_len,
|
||||
ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
|
||||
|
||||
|
@ -2189,7 +2206,8 @@ static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
|
|||
struct ath_btcoex *btcoex = &sc->btcoex;
|
||||
struct ath_hw *ah = sc->sc_ah;
|
||||
|
||||
DPRINTF(ah, ATH_DBG_BTCOEX, "Starting btcoex timers");
|
||||
ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
|
||||
"Starting btcoex timers");
|
||||
|
||||
/* make sure duty cycle timer is also stopped when resuming */
|
||||
if (btcoex->hw_timer_enabled)
|
||||
|
@ -2207,12 +2225,14 @@ static int ath9k_start(struct ieee80211_hw *hw)
|
|||
struct ath_wiphy *aphy = hw->priv;
|
||||
struct ath_softc *sc = aphy->sc;
|
||||
struct ath_hw *ah = sc->sc_ah;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
struct ieee80211_channel *curchan = hw->conf.channel;
|
||||
struct ath9k_channel *init_channel;
|
||||
int r;
|
||||
|
||||
DPRINTF(ah, ATH_DBG_CONFIG, "Starting driver with "
|
||||
"initial channel: %d MHz\n", curchan->center_freq);
|
||||
ath_print(common, ATH_DBG_CONFIG,
|
||||
"Starting driver with initial channel: %d MHz\n",
|
||||
curchan->center_freq);
|
||||
|
||||
mutex_lock(&sc->mutex);
|
||||
|
||||
|
@ -2256,7 +2276,7 @@ static int ath9k_start(struct ieee80211_hw *hw)
|
|||
spin_lock_bh(&sc->sc_resetlock);
|
||||
r = ath9k_hw_reset(ah, init_channel, false);
|
||||
if (r) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Unable to reset hardware; reset status %d "
|
||||
"(freq %u MHz)\n", r,
|
||||
curchan->center_freq);
|
||||
|
@ -2279,7 +2299,8 @@ static int ath9k_start(struct ieee80211_hw *hw)
|
|||
* here except setup the interrupt mask.
|
||||
*/
|
||||
if (ath_startrecv(sc) != 0) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL, "Unable to start recv logic\n");
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Unable to start recv logic\n");
|
||||
r = -EIO;
|
||||
goto mutex_unlock;
|
||||
}
|
||||
|
@ -2331,11 +2352,13 @@ static int ath9k_tx(struct ieee80211_hw *hw,
|
|||
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
|
||||
struct ath_wiphy *aphy = hw->priv;
|
||||
struct ath_softc *sc = aphy->sc;
|
||||
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
||||
struct ath_tx_control txctl;
|
||||
int hdrlen, padsize;
|
||||
|
||||
if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
|
||||
printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
|
||||
ath_print(common, ATH_DBG_XMIT,
|
||||
"ath9k: %s: TX in unexpected wiphy state "
|
||||
"%d\n", wiphy_name(hw->wiphy), aphy->state);
|
||||
goto exit;
|
||||
}
|
||||
|
@ -2349,7 +2372,7 @@ static int ath9k_tx(struct ieee80211_hw *hw,
|
|||
if (ieee80211_is_data(hdr->frame_control) &&
|
||||
!ieee80211_is_nullfunc(hdr->frame_control) &&
|
||||
!ieee80211_has_pm(hdr->frame_control)) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_PS, "Add PM=1 for a TX frame "
|
||||
ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
|
||||
"while in PS mode\n");
|
||||
hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
|
||||
}
|
||||
|
@ -2365,11 +2388,12 @@ static int ath9k_tx(struct ieee80211_hw *hw,
|
|||
ath9k_ps_wakeup(sc);
|
||||
ath9k_hw_setrxabort(sc->sc_ah, 0);
|
||||
if (ieee80211_is_pspoll(hdr->frame_control)) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_PS, "Sending PS-Poll to pick a "
|
||||
"buffered frame\n");
|
||||
ath_print(common, ATH_DBG_PS,
|
||||
"Sending PS-Poll to pick a buffered frame\n");
|
||||
sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
|
||||
} else {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_PS, "Wake up to complete TX\n");
|
||||
ath_print(common, ATH_DBG_PS,
|
||||
"Wake up to complete TX\n");
|
||||
sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
|
||||
}
|
||||
/*
|
||||
|
@ -2411,10 +2435,10 @@ static int ath9k_tx(struct ieee80211_hw *hw,
|
|||
if (!txctl.txq)
|
||||
goto exit;
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
|
||||
ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
|
||||
|
||||
if (ath_tx_start(hw, skb, &txctl) != 0) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "TX failed\n");
|
||||
ath_print(common, ATH_DBG_XMIT, "TX failed\n");
|
||||
goto exit;
|
||||
}
|
||||
|
||||
|
@ -2445,6 +2469,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
|
|||
struct ath_wiphy *aphy = hw->priv;
|
||||
struct ath_softc *sc = aphy->sc;
|
||||
struct ath_hw *ah = sc->sc_ah;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
|
||||
mutex_lock(&sc->mutex);
|
||||
|
||||
|
@ -2459,7 +2484,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
|
|||
}
|
||||
|
||||
if (sc->sc_flags & SC_OP_INVALID) {
|
||||
DPRINTF(ah, ATH_DBG_ANY, "Device not present\n");
|
||||
ath_print(common, ATH_DBG_ANY, "Device not present\n");
|
||||
mutex_unlock(&sc->mutex);
|
||||
return;
|
||||
}
|
||||
|
@ -2495,7 +2520,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
|
|||
|
||||
mutex_unlock(&sc->mutex);
|
||||
|
||||
DPRINTF(ah, ATH_DBG_CONFIG, "Driver halt\n");
|
||||
ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
|
||||
}
|
||||
|
||||
static int ath9k_add_interface(struct ieee80211_hw *hw,
|
||||
|
@ -2503,6 +2528,7 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
|
|||
{
|
||||
struct ath_wiphy *aphy = hw->priv;
|
||||
struct ath_softc *sc = aphy->sc;
|
||||
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
||||
struct ath_vif *avp = (void *)conf->vif->drv_priv;
|
||||
enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
|
||||
int ret = 0;
|
||||
|
@ -2529,13 +2555,14 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
|
|||
ic_opmode = conf->type;
|
||||
break;
|
||||
default:
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Interface type %d not yet supported\n", conf->type);
|
||||
ret = -EOPNOTSUPP;
|
||||
goto out;
|
||||
}
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
|
||||
ath_print(common, ATH_DBG_CONFIG,
|
||||
"Attach a VIF of type: %d\n", ic_opmode);
|
||||
|
||||
/* Set the VIF opmode */
|
||||
avp->av_opmode = ic_opmode;
|
||||
|
@ -2585,10 +2612,11 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw,
|
|||
{
|
||||
struct ath_wiphy *aphy = hw->priv;
|
||||
struct ath_softc *sc = aphy->sc;
|
||||
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
||||
struct ath_vif *avp = (void *)conf->vif->drv_priv;
|
||||
int i;
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Detach Interface\n");
|
||||
ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
|
||||
|
||||
mutex_lock(&sc->mutex);
|
||||
|
||||
|
@ -2623,6 +2651,7 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
|
|||
{
|
||||
struct ath_wiphy *aphy = hw->priv;
|
||||
struct ath_softc *sc = aphy->sc;
|
||||
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
||||
struct ieee80211_conf *conf = &hw->conf;
|
||||
struct ath_hw *ah = sc->sc_ah;
|
||||
bool all_wiphys_idle = false, disable_radio = false;
|
||||
|
@ -2642,7 +2671,7 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
|
|||
}
|
||||
else if (all_wiphys_idle) {
|
||||
ath_radio_enable(sc);
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
|
||||
ath_print(common, ATH_DBG_CONFIG,
|
||||
"not-idle: enabling radio\n");
|
||||
}
|
||||
}
|
||||
|
@ -2696,7 +2725,7 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
|
|||
goto skip_chan_change;
|
||||
}
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
|
||||
ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
|
||||
curchan->center_freq);
|
||||
|
||||
/* XXX: remove me eventualy */
|
||||
|
@ -2705,7 +2734,8 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
|
|||
ath_update_chainmask(sc, conf_is_ht(conf));
|
||||
|
||||
if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unable to set channel\n");
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Unable to set channel\n");
|
||||
mutex_unlock(&sc->mutex);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
@ -2716,7 +2746,7 @@ skip_chan_change:
|
|||
sc->config.txpowlimit = 2 * conf->power_level;
|
||||
|
||||
if (disable_radio) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "idle: disabling radio\n");
|
||||
ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
|
||||
ath_radio_disable(sc);
|
||||
}
|
||||
|
||||
|
@ -2753,7 +2783,8 @@ static void ath9k_configure_filter(struct ieee80211_hw *hw,
|
|||
ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
|
||||
ath9k_ps_restore(sc);
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", rfilt);
|
||||
ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
|
||||
"Set HW RX filter: 0x%x\n", rfilt);
|
||||
}
|
||||
|
||||
static void ath9k_sta_notify(struct ieee80211_hw *hw,
|
||||
|
@ -2781,6 +2812,7 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
|
|||
{
|
||||
struct ath_wiphy *aphy = hw->priv;
|
||||
struct ath_softc *sc = aphy->sc;
|
||||
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
||||
struct ath9k_tx_queue_info qi;
|
||||
int ret = 0, qnum;
|
||||
|
||||
|
@ -2797,7 +2829,7 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
|
|||
qi.tqi_burstTime = params->txop;
|
||||
qnum = ath_get_hal_qnum(queue, sc);
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
|
||||
ath_print(common, ATH_DBG_CONFIG,
|
||||
"Configure tx [queue/halq] [%d/%d], "
|
||||
"aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
|
||||
queue, qnum, params->aifs, params->cw_min,
|
||||
|
@ -2805,7 +2837,7 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
|
|||
|
||||
ret = ath_txq_update(sc, qnum, &qi);
|
||||
if (ret)
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "TXQ Update failed\n");
|
||||
ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
|
||||
|
||||
mutex_unlock(&sc->mutex);
|
||||
|
||||
|
@ -2820,6 +2852,7 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
|
|||
{
|
||||
struct ath_wiphy *aphy = hw->priv;
|
||||
struct ath_softc *sc = aphy->sc;
|
||||
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
||||
int ret = 0;
|
||||
|
||||
if (modparam_nohwcrypt)
|
||||
|
@ -2827,7 +2860,7 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
|
|||
|
||||
mutex_lock(&sc->mutex);
|
||||
ath9k_ps_wakeup(sc);
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW Key\n");
|
||||
ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
|
||||
|
||||
switch (cmd) {
|
||||
case SET_KEY:
|
||||
|
@ -2902,7 +2935,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
|
|||
/* Set aggregation protection mode parameters */
|
||||
sc->config.ath_aggr_prot = 0;
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
|
||||
ath_print(common, ATH_DBG_CONFIG,
|
||||
"RX filter 0x%x bssid %pM aid 0x%x\n",
|
||||
rfilt, common->curbssid, common->curaid);
|
||||
|
||||
|
@ -2951,7 +2984,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
|
|||
ath_update_chainmask(sc, 0);
|
||||
|
||||
if (changed & BSS_CHANGED_ERP_PREAMBLE) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
|
||||
ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
|
||||
bss_conf->use_short_preamble);
|
||||
if (bss_conf->use_short_preamble)
|
||||
sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
|
||||
|
@ -2960,7 +2993,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
|
|||
}
|
||||
|
||||
if (changed & BSS_CHANGED_ERP_CTS_PROT) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
|
||||
ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
|
||||
bss_conf->use_cts_prot);
|
||||
if (bss_conf->use_cts_prot &&
|
||||
hw->conf.channel->band != IEEE80211_BAND_5GHZ)
|
||||
|
@ -2970,7 +3003,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
|
|||
}
|
||||
|
||||
if (changed & BSS_CHANGED_ASSOC) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
|
||||
ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
|
||||
bss_conf->assoc);
|
||||
ath9k_bss_assoc_info(sc, vif, bss_conf);
|
||||
}
|
||||
|
@ -3055,7 +3088,8 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
|
|||
ath_tx_aggr_resume(sc, sta, tid);
|
||||
break;
|
||||
default:
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unknown AMPDU action\n");
|
||||
ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
|
||||
"Unknown AMPDU action\n");
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
|
@ -26,6 +26,7 @@ ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex,
|
|||
bool
|
||||
ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
|
||||
{
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
u32 channelSel = 0;
|
||||
u32 bModeSynth = 0;
|
||||
u32 aModeRefSel = 0;
|
||||
|
@ -46,7 +47,7 @@ ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
|
|||
channelSel = ((freq - 704) * 2 - 3040) / 10;
|
||||
bModeSynth = 1;
|
||||
} else {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Invalid channel %u MHz\n", freq);
|
||||
return false;
|
||||
}
|
||||
|
@ -79,7 +80,7 @@ ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
|
|||
channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
|
||||
aModeRefSel = ath9k_hw_reverse_bits(1, 2);
|
||||
} else {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Invalid channel %u MHz\n", freq);
|
||||
return false;
|
||||
}
|
||||
|
@ -285,6 +286,8 @@ ath9k_hw_rf_free(struct ath_hw *ah)
|
|||
|
||||
bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
|
||||
{
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
|
||||
if (!AR_SREV_9280_10_OR_LATER(ah)) {
|
||||
ah->analogBank0Data =
|
||||
kzalloc((sizeof(u32) *
|
||||
|
@ -315,7 +318,7 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
|
|||
|| ah->analogBank6Data == NULL
|
||||
|| ah->analogBank6TPCData == NULL
|
||||
|| ah->analogBank7Data == NULL) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Cannot allocate RF banks\n");
|
||||
*status = -ENOMEM;
|
||||
return false;
|
||||
|
@ -326,7 +329,7 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
|
|||
ah->iniAddac.ia_rows *
|
||||
ah->iniAddac.ia_columns), GFP_KERNEL);
|
||||
if (ah->addac5416_21 == NULL) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Cannot allocate addac5416_21\n");
|
||||
*status = -ENOMEM;
|
||||
return false;
|
||||
|
@ -336,7 +339,7 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
|
|||
kzalloc((sizeof(u32) *
|
||||
ah->iniBank6.ia_rows), GFP_KERNEL);
|
||||
if (ah->bank6Temp == NULL) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Cannot allocate bank6Temp\n");
|
||||
*status = -ENOMEM;
|
||||
return false;
|
||||
|
|
|
@ -1160,6 +1160,7 @@ struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc,
|
|||
bool is_cw_40)
|
||||
{
|
||||
int mode = 0;
|
||||
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
||||
|
||||
switch(band) {
|
||||
case IEEE80211_BAND_2GHZ:
|
||||
|
@ -1177,13 +1178,13 @@ struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc,
|
|||
mode = ATH9K_MODE_11NA_HT40PLUS;
|
||||
break;
|
||||
default:
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Invalid band\n");
|
||||
ath_print(common, ATH_DBG_CONFIG, "Invalid band\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
BUG_ON(mode >= ATH9K_MODE_MAX);
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
|
||||
ath_print(common, ATH_DBG_CONFIG,
|
||||
"Choosing rate table for mode: %d\n", mode);
|
||||
return sc->hw_rate_table[mode];
|
||||
}
|
||||
|
@ -1195,11 +1196,12 @@ static void ath_rc_init(struct ath_softc *sc,
|
|||
const struct ath_rate_table *rate_table)
|
||||
{
|
||||
struct ath_rateset *rateset = &ath_rc_priv->neg_rates;
|
||||
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
||||
u8 *ht_mcs = (u8 *)&ath_rc_priv->neg_ht_rates;
|
||||
u8 i, j, k, hi = 0, hthi = 0;
|
||||
|
||||
if (!rate_table) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Rate table not initialized\n");
|
||||
return;
|
||||
}
|
||||
|
@ -1263,7 +1265,7 @@ static void ath_rc_init(struct ath_softc *sc,
|
|||
ath_rc_priv->rate_max_phy = ath_rc_priv->valid_rate_index[k-4];
|
||||
sc->cur_rate_table = rate_table;
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
|
||||
ath_print(common, ATH_DBG_CONFIG,
|
||||
"RC Initialized with capabilities: 0x%x\n",
|
||||
ath_rc_priv->ht_cap);
|
||||
}
|
||||
|
@ -1441,7 +1443,7 @@ static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband,
|
|||
oper_cw40, oper_sgi40);
|
||||
ath_rc_init(sc, priv_sta, sband, sta, rate_table);
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
|
||||
ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
|
||||
"Operating HT Bandwidth changed to: %d\n",
|
||||
sc->hw->conf.channel_type);
|
||||
}
|
||||
|
@ -1466,7 +1468,7 @@ static void *ath_rate_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp
|
|||
|
||||
rate_priv = kzalloc(sizeof(struct ath_rate_priv), gfp);
|
||||
if (!rate_priv) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
|
||||
ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
|
||||
"Unable to allocate private rc structure\n");
|
||||
return NULL;
|
||||
}
|
||||
|
|
|
@ -309,7 +309,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
|
|||
sc->rx.bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
|
||||
min(common->cachelsz, (u16)64));
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
|
||||
ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
|
||||
common->cachelsz, sc->rx.bufsize);
|
||||
|
||||
/* Initialize rx descriptors */
|
||||
|
@ -317,7 +317,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
|
|||
error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
|
||||
"rx", nbufs, 1);
|
||||
if (error != 0) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"failed to allocate rx descriptors: %d\n", error);
|
||||
goto err;
|
||||
}
|
||||
|
@ -337,7 +337,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
|
|||
bf->bf_buf_addr))) {
|
||||
dev_kfree_skb_any(skb);
|
||||
bf->bf_mpdu = NULL;
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"dma_mapping_error() on RX init\n");
|
||||
error = -ENOMEM;
|
||||
goto err;
|
||||
|
@ -543,7 +543,8 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
|
|||
|
||||
if (sc->sc_flags & SC_OP_BEACON_SYNC) {
|
||||
sc->sc_flags &= ~SC_OP_BEACON_SYNC;
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_PS, "Reconfigure Beacon timers based on "
|
||||
ath_print(common, ATH_DBG_PS,
|
||||
"Reconfigure Beacon timers based on "
|
||||
"timestamp from the AP\n");
|
||||
ath_beacon_config(sc, NULL);
|
||||
}
|
||||
|
@ -556,7 +557,7 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
|
|||
* a backup trigger for returning into NETWORK SLEEP state,
|
||||
* so we are waiting for it as well.
|
||||
*/
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_PS, "Received DTIM beacon indicating "
|
||||
ath_print(common, ATH_DBG_PS, "Received DTIM beacon indicating "
|
||||
"buffered broadcast/multicast frame(s)\n");
|
||||
sc->sc_flags |= SC_OP_WAIT_FOR_CAB | SC_OP_WAIT_FOR_BEACON;
|
||||
return;
|
||||
|
@ -569,13 +570,15 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
|
|||
* been delivered.
|
||||
*/
|
||||
sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB;
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_PS, "PS wait for CAB frames timed out\n");
|
||||
ath_print(common, ATH_DBG_PS,
|
||||
"PS wait for CAB frames timed out\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
|
||||
{
|
||||
struct ieee80211_hdr *hdr;
|
||||
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
||||
|
||||
hdr = (struct ieee80211_hdr *)skb->data;
|
||||
|
||||
|
@ -593,14 +596,15 @@ static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
|
|||
* point.
|
||||
*/
|
||||
sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB;
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_PS, "All PS CAB frames received, back to "
|
||||
"sleep\n");
|
||||
ath_print(common, ATH_DBG_PS,
|
||||
"All PS CAB frames received, back to sleep\n");
|
||||
} else if ((sc->sc_flags & SC_OP_WAIT_FOR_PSPOLL_DATA) &&
|
||||
!is_multicast_ether_addr(hdr->addr1) &&
|
||||
!ieee80211_has_morefrags(hdr->frame_control)) {
|
||||
sc->sc_flags &= ~SC_OP_WAIT_FOR_PSPOLL_DATA;
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_PS, "Going back to sleep after having "
|
||||
"received PS-Poll data (0x%x)\n",
|
||||
ath_print(common, ATH_DBG_PS,
|
||||
"Going back to sleep after having received "
|
||||
"PS-Poll data (0x%x)\n",
|
||||
sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
|
||||
SC_OP_WAIT_FOR_CAB |
|
||||
SC_OP_WAIT_FOR_PSPOLL_DATA |
|
||||
|
@ -816,7 +820,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
|
|||
bf->bf_buf_addr))) {
|
||||
dev_kfree_skb_any(requeue_skb);
|
||||
bf->bf_mpdu = NULL;
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"dma_mapping_error() on RX\n");
|
||||
ath_rx_send_to_mac80211(sc, skb, &rx_status);
|
||||
break;
|
||||
|
|
|
@ -815,6 +815,7 @@ static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
|
|||
struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
|
||||
{
|
||||
struct ath_hw *ah = sc->sc_ah;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
struct ath9k_tx_queue_info qi;
|
||||
int qnum;
|
||||
|
||||
|
@ -854,7 +855,7 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
|
|||
return NULL;
|
||||
}
|
||||
if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
|
||||
DPRINTF(ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"qnum %u out of range, max %u!\n",
|
||||
qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
|
||||
ath9k_hw_releasetxqueue(ah, qnum);
|
||||
|
@ -884,7 +885,7 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
|
|||
switch (qtype) {
|
||||
case ATH9K_TX_QUEUE_DATA:
|
||||
if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
|
||||
ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
|
||||
"HAL AC %u out of range, max %zu!\n",
|
||||
haltype, ARRAY_SIZE(sc->tx.hwq_map));
|
||||
return -1;
|
||||
|
@ -914,7 +915,7 @@ struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
|
|||
spin_lock_bh(&txq->axq_lock);
|
||||
|
||||
if (txq->axq_depth >= (ATH_TXBUF - 20)) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_XMIT,
|
||||
ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_XMIT,
|
||||
"TX queue: %d is full, depth: %d\n",
|
||||
qnum, txq->axq_depth);
|
||||
ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
|
||||
|
@ -955,7 +956,7 @@ int ath_txq_update(struct ath_softc *sc, int qnum,
|
|||
qi.tqi_readyTime = qinfo->tqi_readyTime;
|
||||
|
||||
if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
|
||||
ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
|
||||
"Unable to update hardware queue %u!\n", qnum);
|
||||
error = -EIO;
|
||||
} else {
|
||||
|
@ -1055,6 +1056,7 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
|
|||
void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
|
||||
{
|
||||
struct ath_hw *ah = sc->sc_ah;
|
||||
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
||||
struct ath_txq *txq;
|
||||
int i, npend = 0;
|
||||
|
||||
|
@ -1076,12 +1078,13 @@ void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
|
|||
if (npend) {
|
||||
int r;
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n");
|
||||
ath_print(common, ATH_DBG_XMIT,
|
||||
"Unable to stop TxDMA. Reset HAL!\n");
|
||||
|
||||
spin_lock_bh(&sc->sc_resetlock);
|
||||
r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true);
|
||||
if (r)
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Unable to reset hardware; reset status %d\n",
|
||||
r);
|
||||
spin_unlock_bh(&sc->sc_resetlock);
|
||||
|
@ -1147,7 +1150,7 @@ int ath_tx_setup(struct ath_softc *sc, int haltype)
|
|||
struct ath_txq *txq;
|
||||
|
||||
if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
|
||||
ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
|
||||
"HAL AC %u out of range, max %zu!\n",
|
||||
haltype, ARRAY_SIZE(sc->tx.hwq_map));
|
||||
return 0;
|
||||
|
@ -1172,6 +1175,7 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
|
|||
struct list_head *head)
|
||||
{
|
||||
struct ath_hw *ah = sc->sc_ah;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
struct ath_buf *bf;
|
||||
|
||||
/*
|
||||
|
@ -1188,17 +1192,17 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
|
|||
txq->axq_depth++;
|
||||
txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_QUEUE,
|
||||
ath_print(common, ATH_DBG_QUEUE,
|
||||
"qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
|
||||
|
||||
if (txq->axq_link == NULL) {
|
||||
ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_XMIT,
|
||||
ath_print(common, ATH_DBG_XMIT,
|
||||
"TXDP[%u] = %llx (%p)\n",
|
||||
txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
|
||||
} else {
|
||||
*txq->axq_link = bf->bf_daddr;
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
|
||||
ath_print(common, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
|
||||
txq->axq_qnum, txq->axq_link,
|
||||
ito64(bf->bf_daddr), bf->bf_desc);
|
||||
}
|
||||
|
@ -1587,7 +1591,7 @@ static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
|
|||
bf->bf_mpdu = NULL;
|
||||
kfree(tx_info_priv);
|
||||
tx_info->rate_driver_data[0] = NULL;
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
|
||||
ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
|
||||
"dma_mapping_error() on TX\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
@ -1670,12 +1674,13 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
|
|||
{
|
||||
struct ath_wiphy *aphy = hw->priv;
|
||||
struct ath_softc *sc = aphy->sc;
|
||||
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
||||
struct ath_buf *bf;
|
||||
int r;
|
||||
|
||||
bf = ath_tx_get_buffer(sc);
|
||||
if (!bf) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "TX buffers are full\n");
|
||||
ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
@ -1683,7 +1688,7 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
|
|||
if (unlikely(r)) {
|
||||
struct ath_txq *txq = txctl->txq;
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "TX mem alloc failure\n");
|
||||
ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n");
|
||||
|
||||
/* upon ath_tx_processq() this TX queue will be resumed, we
|
||||
* guarantee this will happen by knowing beforehand that
|
||||
|
@ -1713,6 +1718,7 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
|
|||
{
|
||||
struct ath_wiphy *aphy = hw->priv;
|
||||
struct ath_softc *sc = aphy->sc;
|
||||
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
||||
int hdrlen, padsize;
|
||||
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
|
||||
struct ath_tx_control txctl;
|
||||
|
@ -1737,7 +1743,7 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
|
|||
if (hdrlen & 3) {
|
||||
padsize = hdrlen % 4;
|
||||
if (skb_headroom(skb) < padsize) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_XMIT,
|
||||
ath_print(common, ATH_DBG_XMIT,
|
||||
"TX CABQ padding failed\n");
|
||||
dev_kfree_skb_any(skb);
|
||||
return;
|
||||
|
@ -1748,10 +1754,11 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
|
|||
|
||||
txctl.txq = sc->beacon.cabq;
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb);
|
||||
ath_print(common, ATH_DBG_XMIT,
|
||||
"transmitting CABQ packet, skb: %p\n", skb);
|
||||
|
||||
if (ath_tx_start(hw, skb, &txctl) != 0) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "CABQ TX failed\n");
|
||||
ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n");
|
||||
goto exit;
|
||||
}
|
||||
|
||||
|
@ -1770,10 +1777,11 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
|
|||
struct ieee80211_hw *hw = sc->hw;
|
||||
struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
|
||||
struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
|
||||
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
||||
int hdrlen, padsize;
|
||||
int frame_type = ATH9K_NOT_INTERNAL;
|
||||
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
|
||||
ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
|
||||
|
||||
if (tx_info_priv) {
|
||||
hw = tx_info_priv->aphy->hw;
|
||||
|
@ -1807,7 +1815,8 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
|
|||
|
||||
if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) {
|
||||
sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK;
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_PS, "Going back to sleep after having "
|
||||
ath_print(common, ATH_DBG_PS,
|
||||
"Going back to sleep after having "
|
||||
"received TX status (0x%x)\n",
|
||||
sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
|
||||
SC_OP_WAIT_FOR_CAB |
|
||||
|
@ -1938,13 +1947,14 @@ static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
|
|||
static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
|
||||
{
|
||||
struct ath_hw *ah = sc->sc_ah;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
struct ath_buf *bf, *lastbf, *bf_held = NULL;
|
||||
struct list_head bf_head;
|
||||
struct ath_desc *ds;
|
||||
int txok;
|
||||
int status;
|
||||
|
||||
DPRINTF(ah, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
|
||||
ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
|
||||
txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
|
||||
txq->axq_link);
|
||||
|
||||
|
@ -2066,7 +2076,8 @@ static void ath_tx_complete_poll_work(struct work_struct *work)
|
|||
}
|
||||
|
||||
if (needreset) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_RESET, "tx hung, resetting the chip\n");
|
||||
ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
|
||||
"tx hung, resetting the chip\n");
|
||||
ath_reset(sc, false);
|
||||
}
|
||||
|
||||
|
@ -2095,6 +2106,7 @@ void ath_tx_tasklet(struct ath_softc *sc)
|
|||
|
||||
int ath_tx_init(struct ath_softc *sc, int nbufs)
|
||||
{
|
||||
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
||||
int error = 0;
|
||||
|
||||
spin_lock_init(&sc->tx.txbuflock);
|
||||
|
@ -2102,7 +2114,7 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
|
|||
error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
|
||||
"tx", nbufs, 1);
|
||||
if (error != 0) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Failed to allocate tx descriptors: %d\n", error);
|
||||
goto err;
|
||||
}
|
||||
|
@ -2110,7 +2122,7 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
|
|||
error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
|
||||
"beacon", ATH_BCBUF, 1);
|
||||
if (error != 0) {
|
||||
DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
|
||||
ath_print(common, ATH_DBG_FATAL,
|
||||
"Failed to allocate beacon descriptors: %d\n", error);
|
||||
goto err;
|
||||
}
|
||||
|
|
32
drivers/net/wireless/ath/debug.c
Normal file
32
drivers/net/wireless/ath/debug.c
Normal file
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright (c) 2009 Atheros Communications Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "ath.h"
|
||||
#include "debug.h"
|
||||
|
||||
void ath_print(struct ath_common *common, int dbg_mask, const char *fmt, ...)
|
||||
{
|
||||
va_list args;
|
||||
|
||||
if (likely(!(common->debug_mask & dbg_mask)))
|
||||
return;
|
||||
|
||||
va_start(args, fmt);
|
||||
printk(KERN_DEBUG "ath: ");
|
||||
vprintk(fmt, args);
|
||||
va_end(args);
|
||||
}
|
||||
EXPORT_SYMBOL(ath_print);
|
77
drivers/net/wireless/ath/debug.h
Normal file
77
drivers/net/wireless/ath/debug.h
Normal file
|
@ -0,0 +1,77 @@
|
|||
/*
|
||||
* Copyright (c) 2008-2009 Atheros Communications Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef ATH_DEBUG_H
|
||||
#define ATH_DEBUG_H
|
||||
|
||||
#include "ath.h"
|
||||
|
||||
/**
|
||||
* enum ath_debug_level - atheros wireless debug level
|
||||
*
|
||||
* @ATH_DBG_RESET: reset processing
|
||||
* @ATH_DBG_QUEUE: hardware queue management
|
||||
* @ATH_DBG_EEPROM: eeprom processing
|
||||
* @ATH_DBG_CALIBRATE: periodic calibration
|
||||
* @ATH_DBG_INTERRUPT: interrupt processing
|
||||
* @ATH_DBG_REGULATORY: regulatory processing
|
||||
* @ATH_DBG_ANI: adaptive noise immunitive processing
|
||||
* @ATH_DBG_XMIT: basic xmit operation
|
||||
* @ATH_DBG_BEACON: beacon handling
|
||||
* @ATH_DBG_CONFIG: configuration of the hardware
|
||||
* @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
|
||||
* @ATH_DBG_PS: power save processing
|
||||
* @ATH_DBG_HWTIMER: hardware timer handling
|
||||
* @ATH_DBG_BTCOEX: bluetooth coexistance
|
||||
* @ATH_DBG_ANY: enable all debugging
|
||||
*
|
||||
* The debug level is used to control the amount and type of debugging output
|
||||
* we want to see. Each driver has its own method for enabling debugging and
|
||||
* modifying debug level states -- but this is typically done through a
|
||||
* module parameter 'debug' along with a respective 'debug' debugfs file
|
||||
* entry.
|
||||
*/
|
||||
enum ATH_DEBUG {
|
||||
ATH_DBG_RESET = 0x00000001,
|
||||
ATH_DBG_QUEUE = 0x00000002,
|
||||
ATH_DBG_EEPROM = 0x00000004,
|
||||
ATH_DBG_CALIBRATE = 0x00000008,
|
||||
ATH_DBG_INTERRUPT = 0x00000010,
|
||||
ATH_DBG_REGULATORY = 0x00000020,
|
||||
ATH_DBG_ANI = 0x00000040,
|
||||
ATH_DBG_XMIT = 0x00000080,
|
||||
ATH_DBG_BEACON = 0x00000100,
|
||||
ATH_DBG_CONFIG = 0x00000200,
|
||||
ATH_DBG_FATAL = 0x00000400,
|
||||
ATH_DBG_PS = 0x00000800,
|
||||
ATH_DBG_HWTIMER = 0x00001000,
|
||||
ATH_DBG_BTCOEX = 0x00002000,
|
||||
ATH_DBG_ANY = 0xffffffff
|
||||
};
|
||||
|
||||
#define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
|
||||
|
||||
#ifdef CONFIG_ATH_DEBUG
|
||||
void ath_print(struct ath_common *common, int dbg_mask, const char *fmt, ...);
|
||||
#else
|
||||
static inline void ath_print(struct ath_common *common,
|
||||
int dbg_mask,
|
||||
const char *fmt, ...)
|
||||
{
|
||||
}
|
||||
#endif /* CONFIG_ATH_DEBUG */
|
||||
|
||||
#endif /* ATH_DEBUG_H */
|
Loading…
Reference in a new issue