mtd: spi-nor: Recover from Spansion/Cypress errors
S25FL{128|256|512}S datasheets say: "When P_ERR or E_ERR bits are set to one, the WIP bit will remain set to one indicating the device remains busy and unable to receive new operation commands. A Clear Status Register (CLSR) command must be received to return the device to standby mode." Current spi-nor code works until first error occurs, but write/erase errors are not just rare hardware failures, they also occur if user tries to flash write-protected areas. After such attempt no SPI command can be executed any more and even read fails. This patch adds support for P_ERR and E_ERR bits in Status Register 1 (so that operation fails immediately and not after a long timeout) and proper recovery from the error condition. Tested on Spansion S25FS128S, which is supported by S25FL129P entry. Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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@ -88,6 +88,7 @@ struct flash_info {
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*/
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#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
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#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
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#define USE_CLSR BIT(14) /* use CLSR command */
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};
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#define JEDEC_MFR(info) ((info)->id[0])
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@ -308,8 +309,18 @@ static inline int spi_nor_sr_ready(struct spi_nor *nor)
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int sr = read_sr(nor);
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if (sr < 0)
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return sr;
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else
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return !(sr & SR_WIP);
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if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
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if (sr & SR_E_ERR)
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dev_err(nor->dev, "Erase Error occurred\n");
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else
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dev_err(nor->dev, "Programming Error occurred\n");
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nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
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return -EIO;
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}
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return !(sr & SR_WIP);
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}
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static inline int spi_nor_fsr_ready(struct spi_nor *nor)
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@ -1043,15 +1054,15 @@ static const struct flash_info spi_nor_ids[] = {
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*/
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{ "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
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{ "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
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{ "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
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{ "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
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{ "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
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{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
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{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
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{ "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
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{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
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{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
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{ "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
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{ "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
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{ "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
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@ -2707,6 +2718,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
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nor->flags |= SNOR_F_HAS_SR_TB;
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if (info->flags & NO_CHIP_ERASE)
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nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
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if (info->flags & USE_CLSR)
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nor->flags |= SNOR_F_USE_CLSR;
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if (info->flags & SPI_NOR_NO_ERASE)
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mtd->flags |= MTD_NO_ERASE;
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@ -105,6 +105,7 @@
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/* Used for Spansion flashes only. */
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#define SPINOR_OP_BRWR 0x17 /* Bank register write */
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#define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
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/* Used for Micron flashes only. */
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#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
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@ -119,6 +120,9 @@
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#define SR_BP2 BIT(4) /* Block protect 2 */
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#define SR_TB BIT(5) /* Top/Bottom protect */
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#define SR_SRWD BIT(7) /* SR write protect */
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/* Spansion/Cypress specific status bits */
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#define SR_E_ERR BIT(5)
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#define SR_P_ERR BIT(6)
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#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
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@ -224,6 +228,7 @@ enum spi_nor_option_flags {
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SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
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SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
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SNOR_F_READY_XSR_RDY = BIT(4),
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SNOR_F_USE_CLSR = BIT(5),
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};
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/**
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