clk: uniphier: add LD11/LD20 stream demux system clock
Add clock for MPEG2 transport stream I/O and demux system (HSC) on UniPhier LD11/LD20 SoCs. Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -51,6 +51,9 @@
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#define UNIPHIER_LD11_SYS_CLK_STDMAC(idx) \
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UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8)
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#define UNIPHIER_LD11_SYS_CLK_HSC(idx) \
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UNIPHIER_CLK_GATE("hsc", (idx), NULL, 0x210c, 9)
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#define UNIPHIER_PRO4_SYS_CLK_GIO(idx) \
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UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6)
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@ -182,6 +185,7 @@ const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
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/* Index 5 reserved for eMMC PHY */
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UNIPHIER_LD11_SYS_CLK_ETHER(6),
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UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC, MIO */
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UNIPHIER_LD11_SYS_CLK_HSC(9),
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UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
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UNIPHIER_LD11_SYS_CLK_AIO(40),
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UNIPHIER_LD11_SYS_CLK_EVEA(41),
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@ -215,6 +219,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
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UNIPHIER_LD20_SYS_CLK_SD,
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UNIPHIER_LD11_SYS_CLK_ETHER(6),
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UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC */
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UNIPHIER_LD11_SYS_CLK_HSC(9),
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/* GIO is always clock-enabled: no function for 0x210c bit5 */
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/*
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* clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15.
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