[PATCH] ppc32: Fix PPC440SP SRAM controller DCRs
Fixes the incorrect DCR base value for the 440SP SRAM controller. Signed-off-by: Matt Porter <mporter@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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@ -423,11 +423,7 @@
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#define MQ0_CONFIG_SIZE_2G 0x0000c000
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#define MQ0_CONFIG_SIZE_2G 0x0000c000
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/* Internal SRAM Controller 440GX/440SP */
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/* Internal SRAM Controller 440GX/440SP */
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#ifdef CONFIG_440SP
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#define DCRN_SRAM0_BASE 0x100
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#else /* 440GX */
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#define DCRN_SRAM0_BASE 0x000
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#define DCRN_SRAM0_BASE 0x000
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#endif
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#define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020)
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#define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020)
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#define DCRN_SRAM0_SB1CR (DCRN_SRAM0_BASE + 0x021)
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#define DCRN_SRAM0_SB1CR (DCRN_SRAM0_BASE + 0x021)
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