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LF-2943 crypto: caam - optimize RNG sample size 

TRNG "sample size" (the total number of entropy samples that will be taken
during entropy generation) default / POR value is very conservatively
set to 2500.

Let's set it to 512, the same as the caam driver in U-boot
(drivers/crypto/fsl_caam.c) does.

This solves the issue of RNG performance dropping after a suspend/resume
cycle on parts where caam loses power, since the initial U-boot setttings
are lost and kernel does not restore them when resuming.

Note: when changing the sample size, the self-test parameters need to be
updated accordingly.

Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Iuliana Prodan <iuliana.prodan@nxp.com>
zero-colors
Horia Geantă 2020-11-27 17:21:36 +02:00
parent 5693782341
commit c705bfcb03
2 changed files with 22 additions and 4 deletions
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16
drivers/crypto/caam/ctrl.c
View File

@ -376,14 +376,24 @@ static void kick_trng(struct device *dev, int ent_delay)
if (ent_delay <= val)
goto start_rng;
val = rd_reg32(&r4tst->rtsdctl);
val = (val & ~RTSDCTL_ENT_DLY_MASK) |
(ent_delay << RTSDCTL_ENT_DLY_SHIFT);
val = (ent_delay << RTSDCTL_ENT_DLY_SHIFT) | 512;
wr_reg32(&r4tst->rtsdctl, val);
/* min. freq. count, equal to 1/4 of the entropy sample length */
wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
/* max. freq. count, equal to 16 times the entropy sample length */
wr_reg32(&r4tst->rtfrqmax, ent_delay << 4);
wr_reg32(&r4tst->rtscmisc, (2 << 16) | 32);
wr_reg32(&r4tst->rtpkrrng, 570);
wr_reg32(&r4tst->rtpkrmax, 1600);
wr_reg32(&r4tst->rtscml, (122 << 16) | 317);
wr_reg32(&r4tst->rtscrl[0],(80 << 16) | 107);
wr_reg32(&r4tst->rtscrl[1],(57 << 16) | 62);
wr_reg32(&r4tst->rtscrl[2],(39 << 16) | 39);
wr_reg32(&r4tst->rtscrl[3],(27 << 16) | 26);
wr_reg32(&r4tst->rtscrl[4],(19 << 16) | 18);
wr_reg32(&r4tst->rtscrl[5],(18 << 16) | 17);
start_rng:
/*
* select raw sampling in both entropy shifter

10
drivers/crypto/caam/regs.h
View File

@ -587,7 +587,15 @@ struct rng4tst {
u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */
u32 rtfrqcnt; /* PRGM=0: freq. count register */
};
u32 rsvd1[40];
union {
u32 rtscmc; /* statistical check run monobit count */
u32 rtscml; /* statistical check run monobit limit */
};
union {
u32 rtscrc[6]; /* statistical check run length count */
u32 rtscrl[6]; /* statistical check run length limit */
};
u32 rsvd1[33];
#define RDSTA_SKVT 0x80000000
#define RDSTA_SKVN 0x40000000
#define RDSTA_PR0 BIT(4)