mfd: Remove db8500-prcmu U8400 legacy
This removes the U8400 legacy from PRCMU and cpufreq drivers. This platform has no current in-kernel users. Signed-off-by: Daniel Willerud <daniel.willerud@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
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@ -22,11 +22,11 @@ static struct cpufreq_frequency_table freq_table[] = {
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},
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[1] = {
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.index = 1,
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.frequency = 300000,
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.frequency = 400000,
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},
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[2] = {
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.index = 2,
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.frequency = 600000,
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.frequency = 800000,
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},
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[3] = {
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/* Used for MAX_OPP, if available */
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@ -113,12 +113,9 @@ static int __cpuinit db8500_cpufreq_init(struct cpufreq_policy *policy)
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BUILD_BUG_ON(ARRAY_SIZE(idx2opp) + 1 != ARRAY_SIZE(freq_table));
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if (!prcmu_is_u8400()) {
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freq_table[1].frequency = 400000;
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freq_table[2].frequency = 800000;
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if (prcmu_has_arm_maxopp())
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freq_table[3].frequency = 1000000;
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}
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if (prcmu_has_arm_maxopp())
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freq_table[3].frequency = 1000000;
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pr_info("db8500-cpufreq : Available frequencies:\n");
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for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
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pr_info(" %d Mhz\n", freq_table[i].frequency/1000);
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@ -503,9 +503,6 @@ static const char *hwacc_ret_regulator_name[NUM_HW_ACC] = {
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/* PLLDIV=12, PLLSW=4 (PLLDDR) */
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#define PRCMU_DSI_CLOCK_SETTING 0x0000008C
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/* PLLDIV=8, PLLSW=4 (PLLDDR) */
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#define PRCMU_DSI_CLOCK_SETTING_U8400 0x00000088
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/* DPI 50000000 Hz */
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#define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
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(16 << PRCMU_CLK_PLL_DIV_SHIFT))
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@ -514,9 +511,6 @@ static const char *hwacc_ret_regulator_name[NUM_HW_ACC] = {
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/* D=101, N=1, R=4, SELDIV2=0 */
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#define PRCMU_PLLDSI_FREQ_SETTING 0x00040165
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/* D=70, N=1, R=3, SELDIV2=0 */
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#define PRCMU_PLLDSI_FREQ_SETTING_U8400 0x00030146
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#define PRCMU_ENABLE_PLLDSI 0x00000001
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#define PRCMU_DISABLE_PLLDSI 0x00000000
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#define PRCMU_RELEASE_RESET_DSS 0x0000400C
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@ -539,19 +533,14 @@ static struct {
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int db8500_prcmu_enable_dsipll(void)
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{
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int i;
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unsigned int plldsifreq;
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/* Clear DSIPLL_RESETN */
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writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
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/* Unclamp DSIPLL in/out */
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writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
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if (prcmu_is_u8400())
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plldsifreq = PRCMU_PLLDSI_FREQ_SETTING_U8400;
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else
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plldsifreq = PRCMU_PLLDSI_FREQ_SETTING;
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/* Set DSI PLL FREQ */
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writel(plldsifreq, PRCM_PLLDSI_FREQ);
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writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
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writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);
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/* Enable Escape clocks */
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writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
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@ -583,12 +572,6 @@ int db8500_prcmu_disable_dsipll(void)
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int db8500_prcmu_set_display_clocks(void)
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{
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unsigned long flags;
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unsigned int dsiclk;
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if (prcmu_is_u8400())
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dsiclk = PRCMU_DSI_CLOCK_SETTING_U8400;
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else
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dsiclk = PRCMU_DSI_CLOCK_SETTING;
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spin_lock_irqsave(&clk_mgt_lock, flags);
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@ -596,7 +579,7 @@ int db8500_prcmu_set_display_clocks(void)
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while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
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cpu_relax();
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writel(dsiclk, PRCM_HDMICLK_MGT);
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writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT);
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writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT);
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writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT);
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@ -642,11 +625,6 @@ bool prcmu_has_arm_maxopp(void)
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PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
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}
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bool prcmu_is_u8400(void)
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{
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return prcmu_version.project_number == PRCMU_PROJECT_ID_8400V2_0;
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}
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/**
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* prcmu_get_boot_status - PRCMU boot status checking
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* Returns: the current PRCMU boot status
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@ -500,7 +500,6 @@ int prcmu_set_rc_a2p(enum romcode_write);
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enum romcode_read prcmu_get_rc_p2a(void);
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enum ap_pwrst prcmu_get_xp70_current_state(void);
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bool prcmu_has_arm_maxopp(void);
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bool prcmu_is_u8400(void);
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int prcmu_set_ape_opp(u8 opp);
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int prcmu_get_ape_opp(void);
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int prcmu_request_ape_opp_100_voltage(bool enable);
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@ -574,11 +573,6 @@ static inline bool prcmu_has_arm_maxopp(void)
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return false;
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}
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static inline bool prcmu_is_u8400(void)
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{
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return false;
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}
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static inline int prcmu_set_ape_opp(u8 opp)
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{
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return 0;
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