[ARM] nommu: rename compressed/head.S symbols to a new style
This patch renames symbols to a new style to prepare mpu support code merging. e.g. __armv4_cache_on --> __armv4_mmu_cache_on Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>wifi-calibration
Hyok S. Choi
Russell King
parent
48fa14f761
commit
c76b6b41d0
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@ -358,7 +358,7 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size
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str r1, [r0]
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mov pc, lr
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__armv4_cache_on:
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__armv4_mmu_cache_on:
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mov r12, lr
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bl __setup_mmu
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mov r0, #0
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@ -367,24 +367,24 @@ __armv4_cache_on:
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mrc p15, 0, r0, c1, c0, 0 @ read control reg
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orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
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orr r0, r0, #0x0030
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bl __common_cache_on
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bl __common_mmu_cache_on
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mov r0, #0
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mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
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mov pc, r12
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__arm6_cache_on:
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__arm6_mmu_cache_on:
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mov r12, lr
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bl __setup_mmu
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mov r0, #0
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mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
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mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
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mov r0, #0x30
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bl __common_cache_on
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bl __common_mmu_cache_on
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mov r0, #0
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mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
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mov pc, r12
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__common_cache_on:
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__common_mmu_cache_on:
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#ifndef DEBUG
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orr r0, r0, #0x000d @ Write buffer, mmu
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#endif
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@ -471,12 +471,12 @@ call_cache_fn: adr r12, proc_types
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proc_types:
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.word 0x41560600 @ ARM6/610
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.word 0xffffffe0
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b __arm6_cache_off @ works, but slow
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b __arm6_cache_off
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b __arm6_mmu_cache_off @ works, but slow
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b __arm6_mmu_cache_off
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mov pc, lr
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@ b __arm6_cache_on @ untested
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@ b __arm6_cache_off
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@ b __armv3_cache_flush
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@ b __arm6_mmu_cache_on @ untested
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@ b __arm6_mmu_cache_off
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@ b __armv3_mmu_cache_flush
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.word 0x00000000 @ old ARM ID
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.word 0x0000f000
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@ -486,14 +486,14 @@ proc_types:
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.word 0x41007000 @ ARM7/710
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.word 0xfff8fe00
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b __arm7_cache_off
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b __arm7_cache_off
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b __arm7_mmu_cache_off
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b __arm7_mmu_cache_off
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mov pc, lr
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.word 0x41807200 @ ARM720T (writethrough)
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.word 0xffffff00
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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mov pc, lr
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.word 0x00007000 @ ARM7 IDs
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@ -506,41 +506,41 @@ proc_types:
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.word 0x4401a100 @ sa110 / sa1100
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.word 0xffffffe0
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_cache_flush
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv4_mmu_cache_flush
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.word 0x6901b110 @ sa1110
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.word 0xfffffff0
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_cache_flush
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv4_mmu_cache_flush
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@ These match on the architecture ID
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.word 0x00020000 @ ARMv4T
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.word 0x000f0000
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_cache_flush
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv4_mmu_cache_flush
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.word 0x00050000 @ ARMv5TE
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.word 0x000f0000
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_cache_flush
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv4_mmu_cache_flush
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.word 0x00060000 @ ARMv5TEJ
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.word 0x000f0000
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_cache_flush
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv4_mmu_cache_flush
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.word 0x00070000 @ ARMv6
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.word 0x000f0000
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv6_cache_flush
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv6_mmu_cache_flush
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.word 0 @ unrecognised type
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.word 0
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@ -562,7 +562,7 @@ proc_types:
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cache_off: mov r3, #12 @ cache_off function
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b call_cache_fn
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__armv4_cache_off:
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__armv4_mmu_cache_off:
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mrc p15, 0, r0, c1, c0
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bic r0, r0, #0x000d
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mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
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@ -571,15 +571,15 @@ __armv4_cache_off:
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mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
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mov pc, lr
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__arm6_cache_off:
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__arm6_mmu_cache_off:
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mov r0, #0x00000030 @ ARM6 control reg.
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b __armv3_cache_off
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b __armv3_mmu_cache_off
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__arm7_cache_off:
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__arm7_mmu_cache_off:
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mov r0, #0x00000070 @ ARM7 control reg.
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b __armv3_cache_off
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b __armv3_mmu_cache_off
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__armv3_cache_off:
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__armv3_mmu_cache_off:
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mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
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mov r0, #0
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mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
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@ -601,7 +601,7 @@ cache_clean_flush:
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mov r3, #16
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b call_cache_fn
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__armv6_cache_flush:
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__armv6_mmu_cache_flush:
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mov r1, #0
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mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
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mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
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@ -609,7 +609,7 @@ __armv6_cache_flush:
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mcr p15, 0, r1, c7, c10, 4 @ drain WB
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mov pc, lr
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__armv4_cache_flush:
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__armv4_mmu_cache_flush:
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mov r2, #64*1024 @ default: 32K dcache size (*2)
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mov r11, #32 @ default: 32 byte line size
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mrc p15, 0, r3, c0, c0, 1 @ read cache type
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@ -637,7 +637,7 @@ no_cache_id:
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mcr p15, 0, r1, c7, c10, 4 @ drain WB
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mov pc, lr
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__armv3_cache_flush:
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__armv3_mmu_cache_flush:
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mov r1, #0
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mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
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mov pc, lr
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