[BNX2]: Add support for a new tx ring.
To separate TX IRQs into a different MSIX vector, we need to support a new tx ring. The original tx ring will still be used when not using MSIX. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -2378,7 +2378,10 @@ bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
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{
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u16 cons;
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cons = bnapi->status_blk->status_tx_quick_consumer_index0;
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if (bnapi->int_num == 0)
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cons = bnapi->status_blk->status_tx_quick_consumer_index0;
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else
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cons = bnapi->status_blk_msix->status_tx_quick_consumer_index;
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if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
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cons++;
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@ -2389,7 +2392,6 @@ static void
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bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
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{
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u16 hw_cons, sw_cons, sw_ring_cons;
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int tx_free_bd = 0;
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hw_cons = bnx2_get_hw_tx_cons(bnapi);
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sw_cons = bnapi->tx_cons;
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@ -2439,8 +2441,6 @@ bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
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sw_cons = NEXT_TX_BD(sw_cons);
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tx_free_bd += last + 1;
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dev_kfree_skb(skb);
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hw_cons = bnx2_get_hw_tx_cons(bnapi);
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@ -4369,6 +4369,24 @@ bnx2_init_chip(struct bnx2 *bp)
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BNX2_HC_CONFIG_COLLECT_STATS;
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}
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if (bp->flags & USING_MSIX_FLAG) {
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REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
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BNX2_HC_MSIX_BIT_VECTOR_VAL);
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REG_WR(bp, BNX2_HC_SB_CONFIG_1,
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BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
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BNX2_HC_SB_CONFIG_1_ONE_SHOT);
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REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP_1,
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(bp->tx_quick_cons_trip_int << 16) |
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bp->tx_quick_cons_trip);
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REG_WR(bp, BNX2_HC_TX_TICKS_1,
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(bp->tx_ticks_int << 16) | bp->tx_ticks);
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val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
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}
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if (bp->flags & ONE_SHOT_MSI_FLAG)
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val |= BNX2_HC_CONFIG_ONE_SHOT;
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@ -4400,6 +4418,25 @@ bnx2_init_chip(struct bnx2 *bp)
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return rc;
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}
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static void
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bnx2_clear_ring_states(struct bnx2 *bp)
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{
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struct bnx2_napi *bnapi;
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int i;
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for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
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bnapi = &bp->bnx2_napi[i];
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bnapi->tx_cons = 0;
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bnapi->hw_tx_cons = 0;
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bnapi->rx_prod_bseq = 0;
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bnapi->rx_prod = 0;
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bnapi->rx_cons = 0;
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bnapi->rx_pg_prod = 0;
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bnapi->rx_pg_cons = 0;
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}
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}
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static void
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bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
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{
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@ -4433,8 +4470,17 @@ static void
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bnx2_init_tx_ring(struct bnx2 *bp)
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{
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struct tx_bd *txbd;
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u32 cid;
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struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
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u32 cid = TX_CID;
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struct bnx2_napi *bnapi;
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bp->tx_vec = 0;
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if (bp->flags & USING_MSIX_FLAG) {
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cid = TX_TSS_CID;
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bp->tx_vec = BNX2_TX_VEC;
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REG_WR(bp, BNX2_TSCH_TSS_CFG, BNX2_TX_INT_NUM |
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(TX_TSS_CID << 7));
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}
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bnapi = &bp->bnx2_napi[bp->tx_vec];
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bp->tx_wake_thresh = bp->tx_ring_size / 2;
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@ -4444,11 +4490,8 @@ bnx2_init_tx_ring(struct bnx2 *bp)
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txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
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bp->tx_prod = 0;
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bnapi->tx_cons = 0;
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bnapi->hw_tx_cons = 0;
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bp->tx_prod_bseq = 0;
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cid = TX_CID;
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bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
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bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
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@ -4487,12 +4530,6 @@ bnx2_init_rx_ring(struct bnx2 *bp)
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u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
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struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
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bnapi->rx_prod = 0;
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bnapi->rx_cons = 0;
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bnapi->rx_prod_bseq = 0;
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bnapi->rx_pg_prod = 0;
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bnapi->rx_pg_cons = 0;
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bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping,
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bp->rx_buf_use_size, bp->rx_max_ring);
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@ -4694,6 +4731,7 @@ bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
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if ((rc = bnx2_init_chip(bp)) != 0)
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return rc;
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bnx2_clear_ring_states(bp);
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bnx2_init_tx_ring(bp);
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bnx2_init_rx_ring(bp);
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return 0;
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@ -4965,7 +5003,11 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
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struct sw_bd *rx_buf;
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struct l2_fhdr *rx_hdr;
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int ret = -ENODEV;
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struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
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struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
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tx_napi = bnapi;
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if (bp->flags & USING_MSIX_FLAG)
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tx_napi = &bp->bnx2_napi[BNX2_TX_VEC];
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if (loopback_mode == BNX2_MAC_LOOPBACK) {
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bp->loopback = MAC_LOOPBACK;
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@ -5030,7 +5072,7 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
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pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
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dev_kfree_skb(skb);
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if (bnx2_get_hw_tx_cons(bnapi) != bp->tx_prod)
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if (bnx2_get_hw_tx_cons(tx_napi) != bp->tx_prod)
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goto loopback_test_done;
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rx_idx = bnx2_get_hw_rx_cons(bnapi);
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@ -5324,7 +5366,7 @@ bnx2_request_irq(struct bnx2 *bp)
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for (i = 0; i < bp->irq_nvecs; i++) {
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irq = &bp->irq_tbl[i];
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rc = request_irq(irq->vector, irq->handler, flags, dev->name,
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rc = request_irq(irq->vector, irq->handler, flags, irq->name,
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dev);
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if (rc)
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break;
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@ -6529,6 +6529,9 @@ struct flash_spec {
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#define BNX2_MAX_MSIX_HW_VEC 9
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#define BNX2_MAX_MSIX_VEC 1
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#define BNX2_BASE_VEC 0
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#define BNX2_TX_VEC 1
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#define BNX2_TX_INT_NUM (BNX2_TX_VEC << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT)
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struct bnx2_irq {
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irq_handler_t handler;
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@ -6541,6 +6544,7 @@ struct bnx2_napi {
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struct napi_struct napi ____cacheline_aligned;
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struct bnx2 *bp;
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struct status_block *status_blk;
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struct status_block_msix *status_blk_msix;
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u32 last_status_idx;
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u32 int_num;
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@ -6583,6 +6587,7 @@ struct bnx2 {
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u32 tx_prod_bseq __attribute__((aligned(L1_CACHE_BYTES)));
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u16 tx_prod;
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u8 tx_vec;
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u32 tx_bidx_addr;
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u32 tx_bseq_addr;
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