arch/tile: Split the icache flush code off to a generic <arch> header.
This code is used in other places in our system than in Linux, so to share it we now implement it as an inline function in our low-level <arch> headers, and instantiate it in one file in Linux's arch/tile/lib. The file is now cacheflush.c and is C code rather than the strangely-named and assembler-implemented __invalidate_icache.S. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Arnd Bergmann <arnd@arndb.de>wifi-calibration
Chris Metcalf
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2db0982781
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c78095bd8c
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/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*
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*/
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/**
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* @file
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*
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* Support for invalidating bytes in the instruction
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*/
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#ifndef __ARCH_ICACHE_H__
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#define __ARCH_ICACHE_H__
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#include <arch/chip.h>
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/**
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* Invalidate the instruction cache for the given range of memory.
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*
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* @param addr The start of memory to be invalidated.
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* @param size The number of bytes to be invalidated.
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* @param page_size The system's page size, typically the PAGE_SIZE constant
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* in sys/page.h. This value must be a power of two no larger
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* than the page containing the code to be invalidated. If the value
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* is smaller than the actual page size, this function will still
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* work, but may run slower than necessary.
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*/
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static __inline void
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invalidate_icache(const void* addr, unsigned long size,
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unsigned long page_size)
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{
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const unsigned long cache_way_size =
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CHIP_L1I_CACHE_SIZE() / CHIP_L1I_ASSOC();
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unsigned long max_useful_size;
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const char* start, *end;
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long num_passes;
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if (__builtin_expect(size == 0, 0))
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return;
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#ifdef __tilegx__
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/* Limit the number of bytes visited to avoid redundant iterations. */
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max_useful_size = (page_size < cache_way_size) ? page_size : cache_way_size;
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/* No PA aliasing is possible, so one pass always suffices. */
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num_passes = 1;
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#else
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/* Limit the number of bytes visited to avoid redundant iterations. */
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max_useful_size = cache_way_size;
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/*
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* Compute how many passes we need (we'll treat 0 as if it were 1).
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* This works because we know the page size is a power of two.
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*/
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num_passes = cache_way_size >> __builtin_ctzl(page_size);
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#endif
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if (__builtin_expect(size > max_useful_size, 0))
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size = max_useful_size;
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/* Locate the first and last bytes to be invalidated. */
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start = (const char *)((unsigned long)addr & -CHIP_L1I_LINE_SIZE());
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end = (const char*)addr + size - 1;
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__insn_mf();
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do
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{
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const char* p;
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for (p = start; p <= end; p += CHIP_L1I_LINE_SIZE())
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__insn_icoh(p);
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start += page_size;
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end += page_size;
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}
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while (--num_passes > 0);
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__insn_drain();
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}
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#endif /* __ARCH_ICACHE_H__ */
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@ -21,6 +21,7 @@
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#include <linux/mm.h>
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#include <linux/cache.h>
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#include <asm/system.h>
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#include <arch/icache.h>
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/* Caches are physically-indexed and so don't need special treatment */
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#define flush_cache_all() do { } while (0)
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@ -37,14 +38,8 @@
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#define flush_icache_page(vma, pg) do { } while (0)
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#define flush_icache_user_range(vma, pg, adr, len) do { } while (0)
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/* See "arch/tile/lib/__invalidate_icache.S". */
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extern void __invalidate_icache(unsigned long start, unsigned long size);
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/* Flush the icache just on this cpu */
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static inline void __flush_icache_range(unsigned long start, unsigned long end)
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{
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__invalidate_icache(start, end - start);
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}
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extern void __flush_icache_range(unsigned long start, unsigned long end);
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/* Flush the entire icache on this cpu. */
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#define __flush_icache() __flush_icache_range(0, CHIP_L1I_CACHE_SIZE())
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@ -2,7 +2,7 @@
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# Makefile for TILE-specific library files..
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#
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lib-y = checksum.o cpumask.o delay.o __invalidate_icache.o \
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lib-y = cacheflush.o checksum.o cpumask.o delay.o \
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mb_incoherent.o uaccess.o \
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memcpy_$(BITS).o memchr_$(BITS).o memmove_$(BITS).o memset_$(BITS).o \
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strchr_$(BITS).o strlen_$(BITS).o
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@ -1,106 +0,0 @@
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/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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* A routine for synchronizing the instruction and data caches.
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* Useful for self-modifying code.
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*
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* r0 holds the buffer address
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* r1 holds the size in bytes
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*/
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#include <arch/chip.h>
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#include <feedback.h>
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#if defined(__NEWLIB__) || defined(__BME__)
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#include <sys/page.h>
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#else
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#include <asm/page.h>
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#endif
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#ifdef __tilegx__
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/* Share code among Tile family chips but adjust opcodes appropriately. */
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#define slt cmpltu
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#define bbst blbst
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#define bnezt bnzt
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#endif
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#if defined(__tilegx__) && __SIZEOF_POINTER__ == 4
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/* Force 32-bit ops so pointers wrap around appropriately. */
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#define ADD_PTR addx
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#define ADDI_PTR addxi
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#else
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#define ADD_PTR add
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#define ADDI_PTR addi
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#endif
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.section .text.__invalidate_icache, "ax"
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.global __invalidate_icache
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.type __invalidate_icache,@function
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.hidden __invalidate_icache
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.align 8
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__invalidate_icache:
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FEEDBACK_ENTER(__invalidate_icache)
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{
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ADD_PTR r1, r0, r1 /* end of buffer */
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blez r1, .Lexit /* skip out if size <= 0 */
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}
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{
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ADDI_PTR r1, r1, -1 /* point to last byte to flush */
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andi r0, r0, -CHIP_L1I_LINE_SIZE() /* align to cache-line size */
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}
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{
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andi r1, r1, -CHIP_L1I_LINE_SIZE() /* last cache line to flush */
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mf
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}
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#if CHIP_L1I_CACHE_SIZE() > PAGE_SIZE
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{
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moveli r4, CHIP_L1I_CACHE_SIZE() / PAGE_SIZE /* loop counter */
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move r2, r0 /* remember starting address */
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}
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#endif
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drain
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{
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slt r3, r0, r1 /* set up loop invariant */
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#if CHIP_L1I_CACHE_SIZE() > PAGE_SIZE
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moveli r6, PAGE_SIZE
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#endif
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}
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.Lentry:
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{
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icoh r0
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ADDI_PTR r0, r0, CHIP_L1I_LINE_SIZE() /* advance buffer */
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}
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{
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slt r3, r0, r1 /* check if buffer < buffer + size */
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bbst r3, .Lentry /* loop if buffer < buffer + size */
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}
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#if CHIP_L1I_CACHE_SIZE() > PAGE_SIZE
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{
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ADD_PTR r2, r2, r6
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ADD_PTR r1, r1, r6
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}
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{
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move r0, r2
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addi r4, r4, -1
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}
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{
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slt r3, r0, r1 /* set up loop invariant */
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bnezt r4, .Lentry
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}
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#endif
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drain
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.Lexit:
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jrp lr
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.Lend___invalidate_icache:
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.size __invalidate_icache, \
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.Lend___invalidate_icache - __invalidate_icache
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@ -0,0 +1,23 @@
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/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#include <asm/page.h>
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#include <asm/cacheflush.h>
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#include <arch/icache.h>
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void __flush_icache_range(unsigned long start, unsigned long end)
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{
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invalidate_icache((const void *)start, end - start, PAGE_SIZE);
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}
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