qed: Add infrastructure for PTP support
The patch adds the required qed interfaces for configuring/reading the PTP clock on the adapter. Signed-off-by: Sudarsana Reddy Kalluru <Sudarsana.Kalluru@cavium.com> Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>zero-colors
Sudarsana Reddy Kalluru
David S. Miller
parent
b93f79bea9
commit
c78c70fa30
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@ -2,7 +2,7 @@ obj-$(CONFIG_QED) := qed.o
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qed-y := qed_cxt.o qed_dev.o qed_hw.o qed_init_fw_funcs.o qed_init_ops.o \
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qed_int.o qed_main.o qed_mcp.o qed_sp_commands.o qed_spq.o qed_l2.o \
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qed_selftest.o qed_dcbx.o qed_debug.o
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qed_selftest.o qed_dcbx.o qed_debug.o qed_ptp.o
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qed-$(CONFIG_QED_SRIOV) += qed_sriov.o qed_vf.o
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qed-$(CONFIG_QED_LL2) += qed_ll2.o
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qed-$(CONFIG_QED_RDMA) += qed_roce.o
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@ -456,6 +456,8 @@ struct qed_hwfn {
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u8 dcbx_no_edpm;
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u8 db_bar_no_edpm;
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/* p_ptp_ptt is valid for leading HWFN only */
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struct qed_ptt *p_ptp_ptt;
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struct qed_simd_fp_handler simd_proto_handler[64];
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#ifdef CONFIG_QED_SRIOV
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@ -214,6 +214,7 @@ int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn,
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p_ramrod->vport_id = abs_vport_id;
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p_ramrod->mtu = cpu_to_le16(p_params->mtu);
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p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts;
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p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
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p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
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p_ramrod->untagged = p_params->only_untagged;
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@ -1886,6 +1887,7 @@ static int qed_start_vport(struct qed_dev *cdev,
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start.drop_ttl0 = params->drop_ttl0;
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start.opaque_fid = p_hwfn->hw_info.opaque_fid;
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start.concrete_fid = p_hwfn->hw_info.concrete_fid;
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start.handle_ptp_pkts = params->handle_ptp_pkts;
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start.vport_id = params->vport_id;
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start.max_buffers_per_cqe = 16;
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start.mtu = params->mtu;
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@ -2328,6 +2330,8 @@ extern const struct qed_iov_hv_ops qed_iov_ops_pass;
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extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass;
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#endif
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extern const struct qed_eth_ptp_ops qed_ptp_ops_pass;
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static const struct qed_eth_ops qed_eth_ops_pass = {
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.common = &qed_common_ops_pass,
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#ifdef CONFIG_QED_SRIOV
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@ -2336,6 +2340,7 @@ static const struct qed_eth_ops qed_eth_ops_pass = {
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#ifdef CONFIG_DCB
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.dcb = &qed_dcbnl_ops_pass,
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#endif
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.ptp = &qed_ptp_ops_pass,
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.fill_dev_info = &qed_fill_eth_dev_info,
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.register_ops = &qed_register_eth_ops,
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.check_mac = &qed_check_mac,
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@ -156,6 +156,7 @@ struct qed_sp_vport_start_params {
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enum qed_tpa_mode tpa_mode;
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bool remove_inner_vlan;
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bool tx_switching;
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bool handle_ptp_pkts;
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bool only_untagged;
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bool drop_ttl0;
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u8 max_buffers_per_cqe;
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@ -902,6 +902,7 @@ static int qed_slowpath_start(struct qed_dev *cdev,
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struct qed_mcp_drv_version drv_version;
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const u8 *data = NULL;
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struct qed_hwfn *hwfn;
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struct qed_ptt *p_ptt;
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int rc = -EINVAL;
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if (qed_iov_wq_start(cdev))
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@ -916,6 +917,14 @@ static int qed_slowpath_start(struct qed_dev *cdev,
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QED_FW_FILE_NAME);
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goto err;
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}
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p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
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if (p_ptt) {
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QED_LEADING_HWFN(cdev)->p_ptp_ptt = p_ptt;
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} else {
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DP_NOTICE(cdev, "Failed to acquire PTT for PTP\n");
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goto err;
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}
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}
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cdev->rx_coalesce_usecs = QED_DEFAULT_RX_USECS;
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@ -1003,6 +1012,10 @@ err:
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if (IS_PF(cdev))
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release_firmware(cdev->firmware);
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if (IS_PF(cdev) && QED_LEADING_HWFN(cdev)->p_ptp_ptt)
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qed_ptt_release(QED_LEADING_HWFN(cdev),
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QED_LEADING_HWFN(cdev)->p_ptp_ptt);
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qed_iov_wq_stop(cdev, false);
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return rc;
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@ -1016,6 +1029,8 @@ static int qed_slowpath_stop(struct qed_dev *cdev)
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qed_ll2_dealloc_if(cdev);
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if (IS_PF(cdev)) {
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qed_ptt_release(QED_LEADING_HWFN(cdev),
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QED_LEADING_HWFN(cdev)->p_ptp_ptt);
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qed_free_stream_mem(cdev);
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if (IS_QED_ETH_IF(cdev))
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qed_sriov_disable(cdev, true);
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@ -0,0 +1,323 @@
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/* QLogic qed NIC Driver
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* Copyright (c) 2015-2017 QLogic Corporation
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and /or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/types.h>
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#include "qed.h"
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#include "qed_dev_api.h"
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#include "qed_hw.h"
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#include "qed_l2.h"
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#include "qed_ptp.h"
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#include "qed_reg_addr.h"
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/* 16 nano second time quantas to wait before making a Drift adjustment */
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#define QED_DRIFT_CNTR_TIME_QUANTA_SHIFT 0
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/* Nano seconds to add/subtract when making a Drift adjustment */
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#define QED_DRIFT_CNTR_ADJUSTMENT_SHIFT 28
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/* Add/subtract the Adjustment_Value when making a Drift adjustment */
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#define QED_DRIFT_CNTR_DIRECTION_SHIFT 31
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#define QED_TIMESTAMP_MASK BIT(16)
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/* Read Rx timestamp */
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static int qed_ptp_hw_read_rx_ts(struct qed_dev *cdev, u64 *timestamp)
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{
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struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
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u32 val;
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*timestamp = 0;
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val = qed_rd(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_SEQID);
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if (!(val & QED_TIMESTAMP_MASK)) {
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DP_INFO(p_hwfn, "Invalid Rx timestamp, buf_seqid = %d\n", val);
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return -EINVAL;
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}
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val = qed_rd(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_TS_LSB);
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*timestamp = qed_rd(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_TS_MSB);
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*timestamp <<= 32;
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*timestamp |= val;
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/* Reset timestamp register to allow new timestamp */
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_SEQID,
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QED_TIMESTAMP_MASK);
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return 0;
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}
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/* Read Tx timestamp */
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static int qed_ptp_hw_read_tx_ts(struct qed_dev *cdev, u64 *timestamp)
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{
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struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
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u32 val;
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*timestamp = 0;
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val = qed_rd(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_SEQID);
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if (!(val & QED_TIMESTAMP_MASK)) {
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DP_INFO(p_hwfn, "Invalid Tx timestamp, buf_seqid = %d\n", val);
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return -EINVAL;
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}
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val = qed_rd(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_TS_LSB);
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*timestamp = qed_rd(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_TS_MSB);
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*timestamp <<= 32;
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*timestamp |= val;
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/* Reset timestamp register to allow new timestamp */
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_SEQID, QED_TIMESTAMP_MASK);
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return 0;
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}
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/* Read Phy Hardware Clock */
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static int qed_ptp_hw_read_cc(struct qed_dev *cdev, u64 *phc_cycles)
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{
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struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
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u32 temp = 0;
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temp = qed_rd(p_hwfn, p_ptt, NIG_REG_TSGEN_SYNC_TIME_LSB);
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*phc_cycles = qed_rd(p_hwfn, p_ptt, NIG_REG_TSGEN_SYNC_TIME_MSB);
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*phc_cycles <<= 32;
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*phc_cycles |= temp;
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return 0;
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}
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/* Filter PTP protocol packets that need to be timestamped */
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static int qed_ptp_hw_cfg_rx_filters(struct qed_dev *cdev,
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enum qed_ptp_filter_type type)
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{
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struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
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u32 rule_mask, parm_mask;
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switch (type) {
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case QED_PTP_FILTER_L2_IPV4_IPV6:
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parm_mask = 0x6AA;
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rule_mask = 0x3EEE;
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break;
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case QED_PTP_FILTER_L2:
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parm_mask = 0x6BF;
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rule_mask = 0x3EFF;
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break;
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case QED_PTP_FILTER_IPV4_IPV6:
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parm_mask = 0x7EA;
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rule_mask = 0x3FFE;
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break;
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case QED_PTP_FILTER_IPV4:
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parm_mask = 0x7EE;
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rule_mask = 0x3FFE;
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break;
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default:
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DP_INFO(p_hwfn, "Invalid PTP filter type %d\n", type);
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return -EINVAL;
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}
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_PARAM_MASK, parm_mask);
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_RULE_MASK, rule_mask);
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_TO_HOST, 0x1);
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/* Reset possibly old timestamps */
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_SEQID,
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QED_TIMESTAMP_MASK);
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return 0;
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}
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/* Adjust the HW clock by a rate given in parts-per-billion (ppb) units.
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* FW/HW accepts the adjustment value in terms of 3 parameters:
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* Drift period - adjustment happens once in certain number of nano seconds.
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* Drift value - time is adjusted by a certain value, for example by 5 ns.
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* Drift direction - add or subtract the adjustment value.
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* The routine translates ppb into the adjustment triplet in an optimal manner.
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*/
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static int qed_ptp_hw_adjfreq(struct qed_dev *cdev, s32 ppb)
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{
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s64 best_val = 0, val, best_period = 0, period, approx_dev, dif, dif2;
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struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
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u32 drift_ctr_cfg = 0, drift_state;
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int drift_dir = 1;
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if (ppb < 0) {
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ppb = -ppb;
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drift_dir = 0;
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}
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if (ppb > 1) {
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s64 best_dif = ppb, best_approx_dev = 1;
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/* Adjustment value is up to +/-7ns, find an optimal value in
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* this range.
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*/
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for (val = 7; val > 0; val--) {
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period = div_s64(val * 1000000000, ppb);
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period -= 8;
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period >>= 4;
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if (period < 1)
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period = 1;
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if (period > 0xFFFFFFE)
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period = 0xFFFFFFE;
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/* Check both rounding ends for approximate error */
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approx_dev = period * 16 + 8;
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dif = ppb * approx_dev - val * 1000000000;
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dif2 = dif + 16 * ppb;
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if (dif < 0)
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dif = -dif;
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if (dif2 < 0)
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dif2 = -dif2;
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/* Determine which end gives better approximation */
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if (dif * (approx_dev + 16) > dif2 * approx_dev) {
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period++;
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approx_dev += 16;
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dif = dif2;
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}
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/* Track best approximation found so far */
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if (best_dif * approx_dev > dif * best_approx_dev) {
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best_dif = dif;
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best_val = val;
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best_period = period;
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best_approx_dev = approx_dev;
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}
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}
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} else if (ppb == 1) {
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/* This is a special case as its the only value which wouldn't
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* fit in a s64 variable. In order to prevent castings simple
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* handle it seperately.
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*/
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best_val = 4;
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best_period = 0xee6b27f;
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} else {
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best_val = 0;
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best_period = 0xFFFFFFF;
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}
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drift_ctr_cfg = (best_period << QED_DRIFT_CNTR_TIME_QUANTA_SHIFT) |
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(((int)best_val) << QED_DRIFT_CNTR_ADJUSTMENT_SHIFT) |
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(((int)drift_dir) << QED_DRIFT_CNTR_DIRECTION_SHIFT);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_RST_DRIFT_CNTR, 0x1);
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drift_state = qed_rd(p_hwfn, p_ptt, NIG_REG_TSGEN_RST_DRIFT_CNTR);
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if (drift_state & 1) {
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qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_DRIFT_CNTR_CONF,
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drift_ctr_cfg);
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} else {
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DP_INFO(p_hwfn, "Drift counter is not reset\n");
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return -EINVAL;
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}
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qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_RST_DRIFT_CNTR, 0x0);
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return 0;
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}
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static int qed_ptp_hw_enable(struct qed_dev *cdev)
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{
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struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
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/* Reset PTP event detection rules - will be configured in the IOCTL */
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_PARAM_MASK, 0x7FF);
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_RULE_MASK, 0x3FFF);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK, 0x7FF);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, 0x3FFF);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_PTP_EN, 7);
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qed_wr(p_hwfn, p_ptt, NIG_REG_RX_PTP_EN, 7);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TS_OUTPUT_ENABLE_PDA, 0x1);
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/* Pause free running counter */
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qed_wr(p_hwfn, p_ptt, NIG_REG_TIMESYNC_GEN_REG_BB, 2);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_FREE_CNT_VALUE_LSB, 0);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_FREE_CNT_VALUE_MSB, 0);
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/* Resume free running counter */
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qed_wr(p_hwfn, p_ptt, NIG_REG_TIMESYNC_GEN_REG_BB, 4);
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/* Disable drift register */
|
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qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_DRIFT_CNTR_CONF, 0x0);
|
||||
qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_RST_DRIFT_CNTR, 0x0);
|
||||
|
||||
/* Reset possibly old timestamps */
|
||||
qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_SEQID,
|
||||
QED_TIMESTAMP_MASK);
|
||||
qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_SEQID, QED_TIMESTAMP_MASK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qed_ptp_hw_hwtstamp_tx_on(struct qed_dev *cdev)
|
||||
{
|
||||
struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
|
||||
struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
|
||||
|
||||
qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK, 0x6AA);
|
||||
qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, 0x3EEE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qed_ptp_hw_disable(struct qed_dev *cdev)
|
||||
{
|
||||
struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
|
||||
struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
|
||||
|
||||
/* Reset PTP event detection rules */
|
||||
qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_PARAM_MASK, 0x7FF);
|
||||
qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_RULE_MASK, 0x3FFF);
|
||||
|
||||
qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK, 0x7FF);
|
||||
qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, 0x3FFF);
|
||||
|
||||
/* Disable the PTP feature */
|
||||
qed_wr(p_hwfn, p_ptt, NIG_REG_RX_PTP_EN, 0x0);
|
||||
qed_wr(p_hwfn, p_ptt, NIG_REG_TX_PTP_EN, 0x0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct qed_eth_ptp_ops qed_ptp_ops_pass = {
|
||||
.hwtstamp_tx_on = qed_ptp_hw_hwtstamp_tx_on,
|
||||
.cfg_rx_filters = qed_ptp_hw_cfg_rx_filters,
|
||||
.read_rx_ts = qed_ptp_hw_read_rx_ts,
|
||||
.read_tx_ts = qed_ptp_hw_read_tx_ts,
|
||||
.read_cc = qed_ptp_hw_read_cc,
|
||||
.adjfreq = qed_ptp_hw_adjfreq,
|
||||
.disable = qed_ptp_hw_disable,
|
||||
.enable = qed_ptp_hw_enable,
|
||||
};
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/* QLogic qed NIC Driver
|
||||
* Copyright (c) 2015-2017 QLogic Corporation
|
||||
*
|
||||
* This software is available to you under a choice of one of two
|
||||
* licenses. You may choose to be licensed under the terms of the GNU
|
||||
* General Public License (GPL) Version 2, available from the file
|
||||
* COPYING in the main directory of this source tree, or the
|
||||
* OpenIB.org BSD license below:
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or
|
||||
* without modification, are permitted provided that the following
|
||||
* conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer.
|
||||
*
|
||||
* - Redistributions in binary form must reproduce the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and /or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
|
||||
#ifndef _QED_PTP_H
|
||||
#define _QED_PTP_H
|
||||
#include <linux/types.h>
|
||||
|
||||
int qed_ptp_hwtstamp_tx_on(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
|
||||
int qed_ptp_cfg_rx_filters(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
|
||||
enum qed_ptp_filter_type type);
|
||||
int qed_ptp_read_rx_ts(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u64 *ts);
|
||||
int qed_ptp_read_tx_ts(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u64 *ts);
|
||||
int qed_ptp_read_cc(struct qed_hwfn *p_hwfn,
|
||||
struct qed_ptt *p_ptt, u64 *cycles);
|
||||
int qed_ptp_adjfreq(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, s32 ppb);
|
||||
int qed_ptp_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
|
||||
int qed_ptp_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
|
||||
|
||||
#endif
|
||||
|
|
@ -1481,4 +1481,35 @@
|
|||
#define DORQ_REG_PF_ICID_BIT_SHIFT_NORM 0x100448UL
|
||||
#define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL
|
||||
#define DORQ_REG_PF_DPI_BIT_SHIFT 0x100450UL
|
||||
#define NIG_REG_RX_PTP_EN 0x501900UL
|
||||
#define NIG_REG_TX_PTP_EN 0x501904UL
|
||||
#define NIG_REG_LLH_PTP_TO_HOST 0x501908UL
|
||||
#define NIG_REG_LLH_PTP_TO_MCP 0x50190cUL
|
||||
#define NIG_REG_PTP_SW_TXTSEN 0x501910UL
|
||||
#define NIG_REG_LLH_PTP_ETHERTYPE_1 0x501914UL
|
||||
#define NIG_REG_LLH_PTP_MAC_DA_2_LSB 0x501918UL
|
||||
#define NIG_REG_LLH_PTP_MAC_DA_2_MSB 0x50191cUL
|
||||
#define NIG_REG_LLH_PTP_PARAM_MASK 0x501920UL
|
||||
#define NIG_REG_LLH_PTP_RULE_MASK 0x501924UL
|
||||
#define NIG_REG_TX_LLH_PTP_PARAM_MASK 0x501928UL
|
||||
#define NIG_REG_TX_LLH_PTP_RULE_MASK 0x50192cUL
|
||||
#define NIG_REG_LLH_PTP_HOST_BUF_SEQID 0x501930UL
|
||||
#define NIG_REG_LLH_PTP_HOST_BUF_TS_LSB 0x501934UL
|
||||
#define NIG_REG_LLH_PTP_HOST_BUF_TS_MSB 0x501938UL
|
||||
#define NIG_REG_LLH_PTP_MCP_BUF_SEQID 0x50193cUL
|
||||
#define NIG_REG_LLH_PTP_MCP_BUF_TS_LSB 0x501940UL
|
||||
#define NIG_REG_LLH_PTP_MCP_BUF_TS_MSB 0x501944UL
|
||||
#define NIG_REG_TX_LLH_PTP_BUF_SEQID 0x501948UL
|
||||
#define NIG_REG_TX_LLH_PTP_BUF_TS_LSB 0x50194cUL
|
||||
#define NIG_REG_TX_LLH_PTP_BUF_TS_MSB 0x501950UL
|
||||
#define NIG_REG_RX_PTP_TS_MSB_ERR 0x501954UL
|
||||
#define NIG_REG_TX_PTP_TS_MSB_ERR 0x501958UL
|
||||
#define NIG_REG_TSGEN_SYNC_TIME_LSB 0x5088c0UL
|
||||
#define NIG_REG_TSGEN_SYNC_TIME_MSB 0x5088c4UL
|
||||
#define NIG_REG_TSGEN_RST_DRIFT_CNTR 0x5088d8UL
|
||||
#define NIG_REG_TSGEN_DRIFT_CNTR_CONF 0x5088dcUL
|
||||
#define NIG_REG_TS_OUTPUT_ENABLE_PDA 0x508870UL
|
||||
#define NIG_REG_TIMESYNC_GEN_REG_BB 0x500d00UL
|
||||
#define NIG_REG_TSGEN_FREE_CNT_VALUE_LSB 0x5088a8UL
|
||||
#define NIG_REG_TSGEN_FREE_CNT_VALUE_MSB 0x5088acUL
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -96,6 +96,7 @@ struct qed_update_vport_params {
|
|||
|
||||
struct qed_start_vport_params {
|
||||
bool remove_inner_vlan;
|
||||
bool handle_ptp_pkts;
|
||||
bool gro_enable;
|
||||
bool drop_ttl0;
|
||||
u8 vport_id;
|
||||
|
|
@ -159,6 +160,15 @@ struct qed_eth_cb_ops {
|
|||
void (*force_mac) (void *dev, u8 *mac, bool forced);
|
||||
};
|
||||
|
||||
#define QED_MAX_PHC_DRIFT_PPB 291666666
|
||||
|
||||
enum qed_ptp_filter_type {
|
||||
QED_PTP_FILTER_L2,
|
||||
QED_PTP_FILTER_IPV4,
|
||||
QED_PTP_FILTER_IPV4_IPV6,
|
||||
QED_PTP_FILTER_L2_IPV4_IPV6
|
||||
};
|
||||
|
||||
#ifdef CONFIG_DCB
|
||||
/* Prototype declaration of qed_eth_dcbnl_ops should match with the declaration
|
||||
* of dcbnl_rtnl_ops structure.
|
||||
|
|
@ -218,6 +228,17 @@ struct qed_eth_dcbnl_ops {
|
|||
};
|
||||
#endif
|
||||
|
||||
struct qed_eth_ptp_ops {
|
||||
int (*hwtstamp_tx_on)(struct qed_dev *);
|
||||
int (*cfg_rx_filters)(struct qed_dev *, enum qed_ptp_filter_type);
|
||||
int (*read_rx_ts)(struct qed_dev *, u64 *);
|
||||
int (*read_tx_ts)(struct qed_dev *, u64 *);
|
||||
int (*read_cc)(struct qed_dev *, u64 *);
|
||||
int (*disable)(struct qed_dev *);
|
||||
int (*adjfreq)(struct qed_dev *, s32);
|
||||
int (*enable)(struct qed_dev *);
|
||||
};
|
||||
|
||||
struct qed_eth_ops {
|
||||
const struct qed_common_ops *common;
|
||||
#ifdef CONFIG_QED_SRIOV
|
||||
|
|
@ -226,6 +247,7 @@ struct qed_eth_ops {
|
|||
#ifdef CONFIG_DCB
|
||||
const struct qed_eth_dcbnl_ops *dcb;
|
||||
#endif
|
||||
const struct qed_eth_ptp_ops *ptp;
|
||||
|
||||
int (*fill_dev_info)(struct qed_dev *cdev,
|
||||
struct qed_dev_eth_info *info);
|
||||
|
|
|
|||
Loading…
Reference in New Issue