Merge remote-tracking branch 'asoc/topic/core' into tmp
This commit is contained in:
commit
c79c33af8f
|
@ -2953,7 +2953,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
|
|||
improve throughput, but will also increase the
|
||||
amount of memory reserved for use by the client.
|
||||
|
||||
swapaccount[=0|1]
|
||||
swapaccount=[0|1]
|
||||
[KNL] Enable accounting of swap in memory resource
|
||||
controller if no parameter or 1 is given or disable
|
||||
it if 0 is given (See Documentation/cgroups/memory.txt)
|
||||
|
|
|
@ -5885,7 +5885,7 @@ F: drivers/i2c/busses/i2c-omap.c
|
|||
F: include/linux/i2c-omap.h
|
||||
|
||||
OMAP DEVICE TREE SUPPORT
|
||||
M: Benoît Cousson <b-cousson@ti.com>
|
||||
M: Benoît Cousson <bcousson@baylibre.com>
|
||||
M: Tony Lindgren <tony@atomide.com>
|
||||
L: linux-omap@vger.kernel.org
|
||||
L: devicetree@vger.kernel.org
|
||||
|
@ -5965,14 +5965,14 @@ S: Maintained
|
|||
F: drivers/char/hw_random/omap-rng.c
|
||||
|
||||
OMAP HWMOD SUPPORT
|
||||
M: Benoît Cousson <b-cousson@ti.com>
|
||||
M: Benoît Cousson <bcousson@baylibre.com>
|
||||
M: Paul Walmsley <paul@pwsan.com>
|
||||
L: linux-omap@vger.kernel.org
|
||||
S: Maintained
|
||||
F: arch/arm/mach-omap2/omap_hwmod.*
|
||||
|
||||
OMAP HWMOD DATA FOR OMAP4-BASED DEVICES
|
||||
M: Benoît Cousson <b-cousson@ti.com>
|
||||
M: Benoît Cousson <bcousson@baylibre.com>
|
||||
L: linux-omap@vger.kernel.org
|
||||
S: Maintained
|
||||
F: arch/arm/mach-omap2/omap_hwmod_44xx_data.c
|
||||
|
|
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 11
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc6
|
||||
EXTRAVERSION = -rc7
|
||||
NAME = Linux for Workgroups
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
@ -39,9 +39,18 @@ ARC_ENTRY strchr
|
|||
ld.a r2,[r0,4]
|
||||
sub r12,r6,r7
|
||||
bic r12,r12,r6
|
||||
#ifdef __LITTLE_ENDIAN__
|
||||
and r7,r12,r4
|
||||
breq r7,0,.Loop ; For speed, we want this branch to be unaligned.
|
||||
b .Lfound_char ; Likewise this one.
|
||||
#else
|
||||
and r12,r12,r4
|
||||
breq r12,0,.Loop ; For speed, we want this branch to be unaligned.
|
||||
lsr_s r12,r12,7
|
||||
bic r2,r7,r6
|
||||
b.d .Lfound_char_b
|
||||
and_s r2,r2,r12
|
||||
#endif
|
||||
; /* We require this code address to be unaligned for speed... */
|
||||
.Laligned:
|
||||
ld_s r2,[r0]
|
||||
|
@ -95,6 +104,7 @@ ARC_ENTRY strchr
|
|||
lsr r7,r7,7
|
||||
|
||||
bic r2,r7,r6
|
||||
.Lfound_char_b:
|
||||
norm r2,r2
|
||||
sub_s r0,r0,4
|
||||
asr_s r2,r2,3
|
||||
|
|
|
@ -14,11 +14,11 @@
|
|||
compatible = "atmel,at91sam9n12ek", "atmel,at91sam9n12", "atmel,at91sam9";
|
||||
|
||||
chosen {
|
||||
bootargs = "mem=128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2";
|
||||
bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x20000000 0x10000000>;
|
||||
reg = <0x20000000 0x8000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
|
|
|
@ -94,8 +94,9 @@
|
|||
|
||||
usb0: ohci@00600000 {
|
||||
status = "okay";
|
||||
num-ports = <2>;
|
||||
atmel,vbus-gpio = <&pioD 19 GPIO_ACTIVE_LOW
|
||||
num-ports = <3>;
|
||||
atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW *//* Activate to have access to port A */
|
||||
&pioD 19 GPIO_ACTIVE_LOW
|
||||
&pioD 20 GPIO_ACTIVE_LOW
|
||||
>;
|
||||
};
|
||||
|
|
|
@ -830,6 +830,8 @@
|
|||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 24 0>; /* PD0 */
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -412,6 +412,8 @@
|
|||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 170 0>; /* PV2 */
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -588,6 +588,8 @@
|
|||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vbus3_reg: regulator@3 {
|
||||
|
@ -598,6 +600,8 @@
|
|||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -89,7 +89,8 @@ void set_fiq_handler(void *start, unsigned int length)
|
|||
|
||||
memcpy(base + offset, start, length);
|
||||
if (!cache_is_vipt_nonaliasing())
|
||||
flush_icache_range(base + offset, offset + length);
|
||||
flush_icache_range((unsigned long)base + offset, offset +
|
||||
length);
|
||||
flush_icache_range(0xffff0000 + offset, 0xffff0000 + offset + length);
|
||||
}
|
||||
|
||||
|
|
|
@ -82,6 +82,7 @@ void machine_crash_nonpanic_core(void *unused)
|
|||
crash_save_cpu(®s, smp_processor_id());
|
||||
flush_cache_all();
|
||||
|
||||
set_cpu_online(smp_processor_id(), false);
|
||||
atomic_dec(&waiting_for_crash_ipi);
|
||||
while (1)
|
||||
cpu_relax();
|
||||
|
|
|
@ -146,7 +146,11 @@ static bool pm_fake(struct kvm_vcpu *vcpu,
|
|||
#define access_pmintenclr pm_fake
|
||||
|
||||
/* Architected CP15 registers.
|
||||
* Important: Must be sorted ascending by CRn, CRM, Op1, Op2
|
||||
* CRn denotes the primary register number, but is copied to the CRm in the
|
||||
* user space API for 64-bit register access in line with the terminology used
|
||||
* in the ARM ARM.
|
||||
* Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit
|
||||
* registers preceding 32-bit ones.
|
||||
*/
|
||||
static const struct coproc_reg cp15_regs[] = {
|
||||
/* CSSELR: swapped by interrupt.S. */
|
||||
|
@ -154,8 +158,8 @@ static const struct coproc_reg cp15_regs[] = {
|
|||
NULL, reset_unknown, c0_CSSELR },
|
||||
|
||||
/* TTBR0/TTBR1: swapped by interrupt.S. */
|
||||
{ CRm( 2), Op1( 0), is64, NULL, reset_unknown64, c2_TTBR0 },
|
||||
{ CRm( 2), Op1( 1), is64, NULL, reset_unknown64, c2_TTBR1 },
|
||||
{ CRm64( 2), Op1( 0), is64, NULL, reset_unknown64, c2_TTBR0 },
|
||||
{ CRm64( 2), Op1( 1), is64, NULL, reset_unknown64, c2_TTBR1 },
|
||||
|
||||
/* TTBCR: swapped by interrupt.S. */
|
||||
{ CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
|
||||
|
@ -182,7 +186,7 @@ static const struct coproc_reg cp15_regs[] = {
|
|||
NULL, reset_unknown, c6_IFAR },
|
||||
|
||||
/* PAR swapped by interrupt.S */
|
||||
{ CRn( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR },
|
||||
{ CRm64( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR },
|
||||
|
||||
/*
|
||||
* DC{C,I,CI}SW operations:
|
||||
|
@ -399,12 +403,13 @@ static bool index_to_params(u64 id, struct coproc_params *params)
|
|||
| KVM_REG_ARM_OPC1_MASK))
|
||||
return false;
|
||||
params->is_64bit = true;
|
||||
params->CRm = ((id & KVM_REG_ARM_CRM_MASK)
|
||||
/* CRm to CRn: see cp15_to_index for details */
|
||||
params->CRn = ((id & KVM_REG_ARM_CRM_MASK)
|
||||
>> KVM_REG_ARM_CRM_SHIFT);
|
||||
params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
|
||||
>> KVM_REG_ARM_OPC1_SHIFT);
|
||||
params->Op2 = 0;
|
||||
params->CRn = 0;
|
||||
params->CRm = 0;
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
|
@ -898,7 +903,14 @@ static u64 cp15_to_index(const struct coproc_reg *reg)
|
|||
if (reg->is_64) {
|
||||
val |= KVM_REG_SIZE_U64;
|
||||
val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
|
||||
val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT);
|
||||
/*
|
||||
* CRn always denotes the primary coproc. reg. nr. for the
|
||||
* in-kernel representation, but the user space API uses the
|
||||
* CRm for the encoding, because it is modelled after the
|
||||
* MRRC/MCRR instructions: see the ARM ARM rev. c page
|
||||
* B3-1445
|
||||
*/
|
||||
val |= (reg->CRn << KVM_REG_ARM_CRM_SHIFT);
|
||||
} else {
|
||||
val |= KVM_REG_SIZE_U32;
|
||||
val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
|
||||
|
|
|
@ -135,6 +135,8 @@ static inline int cmp_reg(const struct coproc_reg *i1,
|
|||
return -1;
|
||||
if (i1->CRn != i2->CRn)
|
||||
return i1->CRn - i2->CRn;
|
||||
if (i1->is_64 != i2->is_64)
|
||||
return i2->is_64 - i1->is_64;
|
||||
if (i1->CRm != i2->CRm)
|
||||
return i1->CRm - i2->CRm;
|
||||
if (i1->Op1 != i2->Op1)
|
||||
|
@ -145,6 +147,7 @@ static inline int cmp_reg(const struct coproc_reg *i1,
|
|||
|
||||
#define CRn(_x) .CRn = _x
|
||||
#define CRm(_x) .CRm = _x
|
||||
#define CRm64(_x) .CRn = _x, .CRm = 0
|
||||
#define Op1(_x) .Op1 = _x
|
||||
#define Op2(_x) .Op2 = _x
|
||||
#define is64 .is_64 = true
|
||||
|
|
|
@ -114,7 +114,11 @@ static bool access_l2ectlr(struct kvm_vcpu *vcpu,
|
|||
|
||||
/*
|
||||
* A15-specific CP15 registers.
|
||||
* Important: Must be sorted ascending by CRn, CRM, Op1, Op2
|
||||
* CRn denotes the primary register number, but is copied to the CRm in the
|
||||
* user space API for 64-bit register access in line with the terminology used
|
||||
* in the ARM ARM.
|
||||
* Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit
|
||||
* registers preceding 32-bit ones.
|
||||
*/
|
||||
static const struct coproc_reg a15_regs[] = {
|
||||
/* MPIDR: we use VMPIDR for guest access. */
|
||||
|
|
|
@ -63,7 +63,8 @@ int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run)
|
|||
static int decode_hsr(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
|
||||
struct kvm_exit_mmio *mmio)
|
||||
{
|
||||
unsigned long rt, len;
|
||||
unsigned long rt;
|
||||
int len;
|
||||
bool is_write, sign_extend;
|
||||
|
||||
if (kvm_vcpu_dabt_isextabt(vcpu)) {
|
||||
|
|
|
@ -85,6 +85,12 @@ static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
|
|||
return p;
|
||||
}
|
||||
|
||||
static bool page_empty(void *ptr)
|
||||
{
|
||||
struct page *ptr_page = virt_to_page(ptr);
|
||||
return page_count(ptr_page) == 1;
|
||||
}
|
||||
|
||||
static void clear_pud_entry(struct kvm *kvm, pud_t *pud, phys_addr_t addr)
|
||||
{
|
||||
pmd_t *pmd_table = pmd_offset(pud, 0);
|
||||
|
@ -103,12 +109,6 @@ static void clear_pmd_entry(struct kvm *kvm, pmd_t *pmd, phys_addr_t addr)
|
|||
put_page(virt_to_page(pmd));
|
||||
}
|
||||
|
||||
static bool pmd_empty(pmd_t *pmd)
|
||||
{
|
||||
struct page *pmd_page = virt_to_page(pmd);
|
||||
return page_count(pmd_page) == 1;
|
||||
}
|
||||
|
||||
static void clear_pte_entry(struct kvm *kvm, pte_t *pte, phys_addr_t addr)
|
||||
{
|
||||
if (pte_present(*pte)) {
|
||||
|
@ -118,12 +118,6 @@ static void clear_pte_entry(struct kvm *kvm, pte_t *pte, phys_addr_t addr)
|
|||
}
|
||||
}
|
||||
|
||||
static bool pte_empty(pte_t *pte)
|
||||
{
|
||||
struct page *pte_page = virt_to_page(pte);
|
||||
return page_count(pte_page) == 1;
|
||||
}
|
||||
|
||||
static void unmap_range(struct kvm *kvm, pgd_t *pgdp,
|
||||
unsigned long long start, u64 size)
|
||||
{
|
||||
|
@ -132,37 +126,37 @@ static void unmap_range(struct kvm *kvm, pgd_t *pgdp,
|
|||
pmd_t *pmd;
|
||||
pte_t *pte;
|
||||
unsigned long long addr = start, end = start + size;
|
||||
u64 range;
|
||||
u64 next;
|
||||
|
||||
while (addr < end) {
|
||||
pgd = pgdp + pgd_index(addr);
|
||||
pud = pud_offset(pgd, addr);
|
||||
if (pud_none(*pud)) {
|
||||
addr += PUD_SIZE;
|
||||
addr = pud_addr_end(addr, end);
|
||||
continue;
|
||||
}
|
||||
|
||||
pmd = pmd_offset(pud, addr);
|
||||
if (pmd_none(*pmd)) {
|
||||
addr += PMD_SIZE;
|
||||
addr = pmd_addr_end(addr, end);
|
||||
continue;
|
||||
}
|
||||
|
||||
pte = pte_offset_kernel(pmd, addr);
|
||||
clear_pte_entry(kvm, pte, addr);
|
||||
range = PAGE_SIZE;
|
||||
next = addr + PAGE_SIZE;
|
||||
|
||||
/* If we emptied the pte, walk back up the ladder */
|
||||
if (pte_empty(pte)) {
|
||||
if (page_empty(pte)) {
|
||||
clear_pmd_entry(kvm, pmd, addr);
|
||||
range = PMD_SIZE;
|
||||
if (pmd_empty(pmd)) {
|
||||
next = pmd_addr_end(addr, end);
|
||||
if (page_empty(pmd) && !page_empty(pud)) {
|
||||
clear_pud_entry(kvm, pud, addr);
|
||||
range = PUD_SIZE;
|
||||
next = pud_addr_end(addr, end);
|
||||
}
|
||||
}
|
||||
|
||||
addr += range;
|
||||
addr = next;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -227,6 +227,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
|
|||
CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
|
||||
CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
|
||||
CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
|
||||
CLKDEV_CON_DEV_ID("usart", "f8040000.serial", &uart0_clk),
|
||||
CLKDEV_CON_DEV_ID("usart", "f8044000.serial", &uart1_clk),
|
||||
CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
|
||||
CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
|
||||
CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc0_clk),
|
||||
|
|
|
@ -75,6 +75,7 @@ static struct davinci_nand_pdata davinci_nand_data = {
|
|||
.parts = davinci_nand_partitions,
|
||||
.nr_parts = ARRAY_SIZE(davinci_nand_partitions),
|
||||
.ecc_mode = NAND_ECC_HW_SYNDROME,
|
||||
.ecc_bits = 4,
|
||||
.bbt_options = NAND_BBT_USE_FLASH,
|
||||
};
|
||||
|
||||
|
|
|
@ -153,6 +153,7 @@ static struct davinci_nand_pdata davinci_evm_nandflash_data = {
|
|||
.parts = davinci_evm_nandflash_partition,
|
||||
.nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition),
|
||||
.ecc_mode = NAND_ECC_HW,
|
||||
.ecc_bits = 1,
|
||||
.bbt_options = NAND_BBT_USE_FLASH,
|
||||
.timing = &davinci_evm_nandflash_timing,
|
||||
};
|
||||
|
|
|
@ -90,6 +90,7 @@ static struct davinci_nand_pdata davinci_nand_data = {
|
|||
.parts = davinci_nand_partitions,
|
||||
.nr_parts = ARRAY_SIZE(davinci_nand_partitions),
|
||||
.ecc_mode = NAND_ECC_HW,
|
||||
.ecc_bits = 1,
|
||||
.options = 0,
|
||||
};
|
||||
|
||||
|
|
|
@ -88,6 +88,7 @@ static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
|
|||
.parts = davinci_ntosd2_nandflash_partition,
|
||||
.nr_parts = ARRAY_SIZE(davinci_ntosd2_nandflash_partition),
|
||||
.ecc_mode = NAND_ECC_HW,
|
||||
.ecc_bits = 1,
|
||||
.bbt_options = NAND_BBT_USE_FLASH,
|
||||
};
|
||||
|
||||
|
|
|
@ -122,11 +122,7 @@ static struct musb_hdrc_config musb_config = {
|
|||
};
|
||||
|
||||
static struct musb_hdrc_platform_data tusb_data = {
|
||||
#ifdef CONFIG_USB_GADGET_MUSB_HDRC
|
||||
.mode = MUSB_OTG,
|
||||
#else
|
||||
.mode = MUSB_HOST,
|
||||
#endif
|
||||
.set_power = tusb_set_power,
|
||||
.min_power = 25, /* x2 = 50 mA drawn from VBUS as peripheral */
|
||||
.power = 100, /* Max 100 mA VBUS for host mode */
|
||||
|
|
|
@ -85,7 +85,7 @@ static struct omap_board_mux board_mux[] __initdata = {
|
|||
|
||||
static struct omap_musb_board_data musb_board_data = {
|
||||
.interface_type = MUSB_INTERFACE_ULPI,
|
||||
.mode = MUSB_PERIPHERAL,
|
||||
.mode = MUSB_OTG,
|
||||
.power = 0,
|
||||
};
|
||||
|
||||
|
|
|
@ -38,11 +38,8 @@ static struct musb_hdrc_config musb_config = {
|
|||
};
|
||||
|
||||
static struct musb_hdrc_platform_data musb_plat = {
|
||||
#ifdef CONFIG_USB_GADGET_MUSB_HDRC
|
||||
.mode = MUSB_OTG,
|
||||
#else
|
||||
.mode = MUSB_HOST,
|
||||
#endif
|
||||
|
||||
/* .clock is set dynamically */
|
||||
.config = &musb_config,
|
||||
|
||||
|
|
|
@ -809,15 +809,18 @@ config KUSER_HELPERS
|
|||
the CPU type fitted to the system. This permits binaries to be
|
||||
run on ARMv4 through to ARMv7 without modification.
|
||||
|
||||
See Documentation/arm/kernel_user_helpers.txt for details.
|
||||
|
||||
However, the fixed address nature of these helpers can be used
|
||||
by ROP (return orientated programming) authors when creating
|
||||
exploits.
|
||||
|
||||
If all of the binaries and libraries which run on your platform
|
||||
are built specifically for your platform, and make no use of
|
||||
these helpers, then you can turn this option off. However,
|
||||
when such an binary or library is run, it will receive a SIGILL
|
||||
signal, which will terminate the program.
|
||||
these helpers, then you can turn this option off to hinder
|
||||
such exploits. However, in that case, if a binary or library
|
||||
relying on those helpers is run, it will receive a SIGILL signal,
|
||||
which will terminate the program.
|
||||
|
||||
Say N here only if you are absolutely certain that you do not
|
||||
need these helpers; otherwise, the safe option is to say Y.
|
||||
|
|
|
@ -55,12 +55,13 @@ void __init s3c_init_cpu(unsigned long idcode,
|
|||
|
||||
printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
|
||||
|
||||
if (cpu->map_io == NULL || cpu->init == NULL) {
|
||||
if (cpu->init == NULL) {
|
||||
printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
|
||||
panic("Unsupported Samsung CPU");
|
||||
}
|
||||
|
||||
cpu->map_io();
|
||||
if (cpu->map_io)
|
||||
cpu->map_io();
|
||||
}
|
||||
|
||||
/* s3c24xx_init_clocks
|
||||
|
|
|
@ -170,6 +170,7 @@ static void __init xen_percpu_init(void *unused)
|
|||
per_cpu(xen_vcpu, cpu) = vcpup;
|
||||
|
||||
enable_percpu_irq(xen_events_irq, 0);
|
||||
put_cpu();
|
||||
}
|
||||
|
||||
static void xen_restart(enum reboot_mode reboot_mode, const char *cmd)
|
||||
|
|
|
@ -42,14 +42,15 @@
|
|||
#define TPIDR_EL1 18 /* Thread ID, Privileged */
|
||||
#define AMAIR_EL1 19 /* Aux Memory Attribute Indirection Register */
|
||||
#define CNTKCTL_EL1 20 /* Timer Control Register (EL1) */
|
||||
#define PAR_EL1 21 /* Physical Address Register */
|
||||
/* 32bit specific registers. Keep them at the end of the range */
|
||||
#define DACR32_EL2 21 /* Domain Access Control Register */
|
||||
#define IFSR32_EL2 22 /* Instruction Fault Status Register */
|
||||
#define FPEXC32_EL2 23 /* Floating-Point Exception Control Register */
|
||||
#define DBGVCR32_EL2 24 /* Debug Vector Catch Register */
|
||||
#define TEECR32_EL1 25 /* ThumbEE Configuration Register */
|
||||
#define TEEHBR32_EL1 26 /* ThumbEE Handler Base Register */
|
||||
#define NR_SYS_REGS 27
|
||||
#define DACR32_EL2 22 /* Domain Access Control Register */
|
||||
#define IFSR32_EL2 23 /* Instruction Fault Status Register */
|
||||
#define FPEXC32_EL2 24 /* Floating-Point Exception Control Register */
|
||||
#define DBGVCR32_EL2 25 /* Debug Vector Catch Register */
|
||||
#define TEECR32_EL1 26 /* ThumbEE Configuration Register */
|
||||
#define TEEHBR32_EL1 27 /* ThumbEE Handler Base Register */
|
||||
#define NR_SYS_REGS 28
|
||||
|
||||
/* 32bit mapping */
|
||||
#define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
|
||||
|
@ -69,6 +70,8 @@
|
|||
#define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
|
||||
#define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */
|
||||
#define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */
|
||||
#define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */
|
||||
#define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */
|
||||
#define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */
|
||||
#define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */
|
||||
#define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */
|
||||
|
|
|
@ -129,7 +129,7 @@ struct kvm_vcpu_arch {
|
|||
struct kvm_mmu_memory_cache mmu_page_cache;
|
||||
|
||||
/* Target CPU and feature flags */
|
||||
u32 target;
|
||||
int target;
|
||||
DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
|
||||
|
||||
/* Detect first run of a vcpu */
|
||||
|
|
|
@ -107,7 +107,12 @@ armpmu_map_cache_event(const unsigned (*cache_map)
|
|||
static int
|
||||
armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
|
||||
{
|
||||
int mapping = (*event_map)[config];
|
||||
int mapping;
|
||||
|
||||
if (config >= PERF_COUNT_HW_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
mapping = (*event_map)[config];
|
||||
return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
|
||||
}
|
||||
|
||||
|
@ -317,6 +322,9 @@ validate_event(struct pmu_hw_events *hw_events,
|
|||
struct hw_perf_event fake_event = event->hw;
|
||||
struct pmu *leader_pmu = event->group_leader->pmu;
|
||||
|
||||
if (is_software_event(event))
|
||||
return 1;
|
||||
|
||||
if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
|
||||
return 1;
|
||||
|
||||
|
|
|
@ -214,6 +214,7 @@ __kvm_hyp_code_start:
|
|||
mrs x21, tpidr_el1
|
||||
mrs x22, amair_el1
|
||||
mrs x23, cntkctl_el1
|
||||
mrs x24, par_el1
|
||||
|
||||
stp x4, x5, [x3]
|
||||
stp x6, x7, [x3, #16]
|
||||
|
@ -225,6 +226,7 @@ __kvm_hyp_code_start:
|
|||
stp x18, x19, [x3, #112]
|
||||
stp x20, x21, [x3, #128]
|
||||
stp x22, x23, [x3, #144]
|
||||
str x24, [x3, #160]
|
||||
.endm
|
||||
|
||||
.macro restore_sysregs
|
||||
|
@ -243,6 +245,7 @@ __kvm_hyp_code_start:
|
|||
ldp x18, x19, [x3, #112]
|
||||
ldp x20, x21, [x3, #128]
|
||||
ldp x22, x23, [x3, #144]
|
||||
ldr x24, [x3, #160]
|
||||
|
||||
msr vmpidr_el2, x4
|
||||
msr csselr_el1, x5
|
||||
|
@ -264,6 +267,7 @@ __kvm_hyp_code_start:
|
|||
msr tpidr_el1, x21
|
||||
msr amair_el1, x22
|
||||
msr cntkctl_el1, x23
|
||||
msr par_el1, x24
|
||||
.endm
|
||||
|
||||
.macro skip_32bit_state tmp, target
|
||||
|
@ -600,6 +604,8 @@ END(__kvm_vcpu_run)
|
|||
|
||||
// void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
|
||||
ENTRY(__kvm_tlb_flush_vmid_ipa)
|
||||
dsb ishst
|
||||
|
||||
kern_hyp_va x0
|
||||
ldr x2, [x0, #KVM_VTTBR]
|
||||
msr vttbr_el2, x2
|
||||
|
@ -621,6 +627,7 @@ ENTRY(__kvm_tlb_flush_vmid_ipa)
|
|||
ENDPROC(__kvm_tlb_flush_vmid_ipa)
|
||||
|
||||
ENTRY(__kvm_flush_vm_context)
|
||||
dsb ishst
|
||||
tlbi alle1is
|
||||
ic ialluis
|
||||
dsb sy
|
||||
|
@ -753,6 +760,10 @@ el1_trap:
|
|||
*/
|
||||
tbnz x1, #7, 1f // S1PTW is set
|
||||
|
||||
/* Preserve PAR_EL1 */
|
||||
mrs x3, par_el1
|
||||
push x3, xzr
|
||||
|
||||
/*
|
||||
* Permission fault, HPFAR_EL2 is invalid.
|
||||
* Resolve the IPA the hard way using the guest VA.
|
||||
|
@ -766,6 +777,8 @@ el1_trap:
|
|||
|
||||
/* Read result */
|
||||
mrs x3, par_el1
|
||||
pop x0, xzr // Restore PAR_EL1 from the stack
|
||||
msr par_el1, x0
|
||||
tbnz x3, #0, 3f // Bail out if we failed the translation
|
||||
ubfx x3, x3, #12, #36 // Extract IPA
|
||||
lsl x3, x3, #4 // and present it like HPFAR
|
||||
|
|
|
@ -211,6 +211,9 @@ static const struct sys_reg_desc sys_reg_descs[] = {
|
|||
/* FAR_EL1 */
|
||||
{ Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
|
||||
NULL, reset_unknown, FAR_EL1 },
|
||||
/* PAR_EL1 */
|
||||
{ Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
|
||||
NULL, reset_unknown, PAR_EL1 },
|
||||
|
||||
/* PMINTENSET_EL1 */
|
||||
{ Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
|
||||
|
|
|
@ -803,6 +803,32 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
|
|||
dec_insn.next_pc_inc;
|
||||
return 1;
|
||||
break;
|
||||
#ifdef CONFIG_CPU_CAVIUM_OCTEON
|
||||
case lwc2_op: /* This is bbit0 on Octeon */
|
||||
if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
|
||||
*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
|
||||
else
|
||||
*contpc = regs->cp0_epc + 8;
|
||||
return 1;
|
||||
case ldc2_op: /* This is bbit032 on Octeon */
|
||||
if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
|
||||
*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
|
||||
else
|
||||
*contpc = regs->cp0_epc + 8;
|
||||
return 1;
|
||||
case swc2_op: /* This is bbit1 on Octeon */
|
||||
if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
|
||||
*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
|
||||
else
|
||||
*contpc = regs->cp0_epc + 8;
|
||||
return 1;
|
||||
case sdc2_op: /* This is bbit132 on Octeon */
|
||||
if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
|
||||
*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
|
||||
else
|
||||
*contpc = regs->cp0_epc + 8;
|
||||
return 1;
|
||||
#endif
|
||||
case cop0_op:
|
||||
case cop1_op:
|
||||
case cop2_op:
|
||||
|
|
|
@ -35,9 +35,9 @@ static void sanitize_boot_params(struct boot_params *boot_params)
|
|||
*/
|
||||
if (boot_params->sentinel) {
|
||||
/* fields in boot_params are left uninitialized, clear them */
|
||||
memset(&boot_params->olpc_ofw_header, 0,
|
||||
memset(&boot_params->ext_ramdisk_image, 0,
|
||||
(char *)&boot_params->efi_info -
|
||||
(char *)&boot_params->olpc_ofw_header);
|
||||
(char *)&boot_params->ext_ramdisk_image);
|
||||
memset(&boot_params->kbd_status, 0,
|
||||
(char *)&boot_params->hdr -
|
||||
(char *)&boot_params->kbd_status);
|
||||
|
|
|
@ -59,7 +59,7 @@ static inline u16 find_equiv_id(struct equiv_cpu_entry *equiv_cpu_table,
|
|||
|
||||
extern int __apply_microcode_amd(struct microcode_amd *mc_amd);
|
||||
extern int apply_microcode_amd(int cpu);
|
||||
extern enum ucode_state load_microcode_amd(int cpu, const u8 *data, size_t size);
|
||||
extern enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t size);
|
||||
|
||||
#ifdef CONFIG_MICROCODE_AMD_EARLY
|
||||
#ifdef CONFIG_X86_32
|
||||
|
|
|
@ -512,7 +512,7 @@ static void early_init_amd(struct cpuinfo_x86 *c)
|
|||
|
||||
static const int amd_erratum_383[];
|
||||
static const int amd_erratum_400[];
|
||||
static bool cpu_has_amd_erratum(const int *erratum);
|
||||
static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
|
||||
|
||||
static void init_amd(struct cpuinfo_x86 *c)
|
||||
{
|
||||
|
@ -729,11 +729,11 @@ static void init_amd(struct cpuinfo_x86 *c)
|
|||
value &= ~(1ULL << 24);
|
||||
wrmsrl_safe(MSR_AMD64_BU_CFG2, value);
|
||||
|
||||
if (cpu_has_amd_erratum(amd_erratum_383))
|
||||
if (cpu_has_amd_erratum(c, amd_erratum_383))
|
||||
set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
|
||||
}
|
||||
|
||||
if (cpu_has_amd_erratum(amd_erratum_400))
|
||||
if (cpu_has_amd_erratum(c, amd_erratum_400))
|
||||
set_cpu_bug(c, X86_BUG_AMD_APIC_C1E);
|
||||
|
||||
rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
|
||||
|
@ -878,23 +878,13 @@ static const int amd_erratum_400[] =
|
|||
static const int amd_erratum_383[] =
|
||||
AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
|
||||
|
||||
static bool cpu_has_amd_erratum(const int *erratum)
|
||||
|
||||
static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
|
||||
{
|
||||
struct cpuinfo_x86 *cpu = __this_cpu_ptr(&cpu_info);
|
||||
int osvw_id = *erratum++;
|
||||
u32 range;
|
||||
u32 ms;
|
||||
|
||||
/*
|
||||
* If called early enough that current_cpu_data hasn't been initialized
|
||||
* yet, fall back to boot_cpu_data.
|
||||
*/
|
||||
if (cpu->x86 == 0)
|
||||
cpu = &boot_cpu_data;
|
||||
|
||||
if (cpu->x86_vendor != X86_VENDOR_AMD)
|
||||
return false;
|
||||
|
||||
if (osvw_id >= 0 && osvw_id < 65536 &&
|
||||
cpu_has(cpu, X86_FEATURE_OSVW)) {
|
||||
u64 osvw_len;
|
||||
|
|
|
@ -145,10 +145,9 @@ static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static unsigned int verify_patch_size(int cpu, u32 patch_size,
|
||||
static unsigned int verify_patch_size(u8 family, u32 patch_size,
|
||||
unsigned int size)
|
||||
{
|
||||
struct cpuinfo_x86 *c = &cpu_data(cpu);
|
||||
u32 max_size;
|
||||
|
||||
#define F1XH_MPB_MAX_SIZE 2048
|
||||
|
@ -156,7 +155,7 @@ static unsigned int verify_patch_size(int cpu, u32 patch_size,
|
|||
#define F15H_MPB_MAX_SIZE 4096
|
||||
#define F16H_MPB_MAX_SIZE 3458
|
||||
|
||||
switch (c->x86) {
|
||||
switch (family) {
|
||||
case 0x14:
|
||||
max_size = F14H_MPB_MAX_SIZE;
|
||||
break;
|
||||
|
@ -277,9 +276,8 @@ static void cleanup(void)
|
|||
* driver cannot continue functioning normally. In such cases, we tear
|
||||
* down everything we've used up so far and exit.
|
||||
*/
|
||||
static int verify_and_add_patch(unsigned int cpu, u8 *fw, unsigned int leftover)
|
||||
static int verify_and_add_patch(u8 family, u8 *fw, unsigned int leftover)
|
||||
{
|
||||
struct cpuinfo_x86 *c = &cpu_data(cpu);
|
||||
struct microcode_header_amd *mc_hdr;
|
||||
struct ucode_patch *patch;
|
||||
unsigned int patch_size, crnt_size, ret;
|
||||
|
@ -299,7 +297,7 @@ static int verify_and_add_patch(unsigned int cpu, u8 *fw, unsigned int leftover)
|
|||
|
||||
/* check if patch is for the current family */
|
||||
proc_fam = ((proc_fam >> 8) & 0xf) + ((proc_fam >> 20) & 0xff);
|
||||
if (proc_fam != c->x86)
|
||||
if (proc_fam != family)
|
||||
return crnt_size;
|
||||
|
||||
if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
|
||||
|
@ -308,7 +306,7 @@ static int verify_and_add_patch(unsigned int cpu, u8 *fw, unsigned int leftover)
|
|||
return crnt_size;
|
||||
}
|
||||
|
||||
ret = verify_patch_size(cpu, patch_size, leftover);
|
||||
ret = verify_patch_size(family, patch_size, leftover);
|
||||
if (!ret) {
|
||||
pr_err("Patch-ID 0x%08x: size mismatch.\n", mc_hdr->patch_id);
|
||||
return crnt_size;
|
||||
|
@ -339,7 +337,8 @@ static int verify_and_add_patch(unsigned int cpu, u8 *fw, unsigned int leftover)
|
|||
return crnt_size;
|
||||
}
|
||||
|
||||
static enum ucode_state __load_microcode_amd(int cpu, const u8 *data, size_t size)
|
||||
static enum ucode_state __load_microcode_amd(u8 family, const u8 *data,
|
||||
size_t size)
|
||||
{
|
||||
enum ucode_state ret = UCODE_ERROR;
|
||||
unsigned int leftover;
|
||||
|
@ -362,7 +361,7 @@ static enum ucode_state __load_microcode_amd(int cpu, const u8 *data, size_t siz
|
|||
}
|
||||
|
||||
while (leftover) {
|
||||
crnt_size = verify_and_add_patch(cpu, fw, leftover);
|
||||
crnt_size = verify_and_add_patch(family, fw, leftover);
|
||||
if (crnt_size < 0)
|
||||
return ret;
|
||||
|
||||
|
@ -373,22 +372,22 @@ static enum ucode_state __load_microcode_amd(int cpu, const u8 *data, size_t siz
|
|||
return UCODE_OK;
|
||||
}
|
||||
|
||||
enum ucode_state load_microcode_amd(int cpu, const u8 *data, size_t size)
|
||||
enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t size)
|
||||
{
|
||||
enum ucode_state ret;
|
||||
|
||||
/* free old equiv table */
|
||||
free_equiv_cpu_table();
|
||||
|
||||
ret = __load_microcode_amd(cpu, data, size);
|
||||
ret = __load_microcode_amd(family, data, size);
|
||||
|
||||
if (ret != UCODE_OK)
|
||||
cleanup();
|
||||
|
||||
#if defined(CONFIG_MICROCODE_AMD_EARLY) && defined(CONFIG_X86_32)
|
||||
/* save BSP's matching patch for early load */
|
||||
if (cpu_data(cpu).cpu_index == boot_cpu_data.cpu_index) {
|
||||
struct ucode_patch *p = find_patch(cpu);
|
||||
if (cpu_data(smp_processor_id()).cpu_index == boot_cpu_data.cpu_index) {
|
||||
struct ucode_patch *p = find_patch(smp_processor_id());
|
||||
if (p) {
|
||||
memset(amd_bsp_mpb, 0, MPB_MAX_SIZE);
|
||||
memcpy(amd_bsp_mpb, p->data, min_t(u32, ksize(p->data),
|
||||
|
@ -441,7 +440,7 @@ static enum ucode_state request_microcode_amd(int cpu, struct device *device,
|
|||
goto fw_release;
|
||||
}
|
||||
|
||||
ret = load_microcode_amd(cpu, fw->data, fw->size);
|
||||
ret = load_microcode_amd(c->x86, fw->data, fw->size);
|
||||
|
||||
fw_release:
|
||||
release_firmware(fw);
|
||||
|
|
|
@ -238,25 +238,17 @@ static void __init collect_cpu_sig_on_bsp(void *arg)
|
|||
uci->cpu_sig.sig = cpuid_eax(0x00000001);
|
||||
}
|
||||
#else
|
||||
static void collect_cpu_info_amd_early(struct cpuinfo_x86 *c,
|
||||
struct ucode_cpu_info *uci)
|
||||
void load_ucode_amd_ap(void)
|
||||
{
|
||||
unsigned int cpu = smp_processor_id();
|
||||
struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
|
||||
u32 rev, eax;
|
||||
|
||||
rdmsr(MSR_AMD64_PATCH_LEVEL, rev, eax);
|
||||
eax = cpuid_eax(0x00000001);
|
||||
|
||||
uci->cpu_sig.sig = eax;
|
||||
uci->cpu_sig.rev = rev;
|
||||
c->microcode = rev;
|
||||
c->x86 = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff);
|
||||
}
|
||||
|
||||
void load_ucode_amd_ap(void)
|
||||
{
|
||||
unsigned int cpu = smp_processor_id();
|
||||
|
||||
collect_cpu_info_amd_early(&cpu_data(cpu), ucode_cpu_info + cpu);
|
||||
uci->cpu_sig.sig = eax;
|
||||
|
||||
if (cpu && !ucode_loaded) {
|
||||
void *ucode;
|
||||
|
@ -265,8 +257,10 @@ void load_ucode_amd_ap(void)
|
|||
return;
|
||||
|
||||
ucode = (void *)(initrd_start + ucode_offset);
|
||||
if (load_microcode_amd(0, ucode, ucode_size) != UCODE_OK)
|
||||
eax = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff);
|
||||
if (load_microcode_amd(eax, ucode, ucode_size) != UCODE_OK)
|
||||
return;
|
||||
|
||||
ucode_loaded = true;
|
||||
}
|
||||
|
||||
|
@ -278,6 +272,8 @@ int __init save_microcode_in_initrd_amd(void)
|
|||
{
|
||||
enum ucode_state ret;
|
||||
void *ucode;
|
||||
u32 eax;
|
||||
|
||||
#ifdef CONFIG_X86_32
|
||||
unsigned int bsp = boot_cpu_data.cpu_index;
|
||||
struct ucode_cpu_info *uci = ucode_cpu_info + bsp;
|
||||
|
@ -293,7 +289,10 @@ int __init save_microcode_in_initrd_amd(void)
|
|||
return 0;
|
||||
|
||||
ucode = (void *)(initrd_start + ucode_offset);
|
||||
ret = load_microcode_amd(0, ucode, ucode_size);
|
||||
eax = cpuid_eax(0x00000001);
|
||||
eax = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff);
|
||||
|
||||
ret = load_microcode_amd(eax, ucode, ucode_size);
|
||||
if (ret != UCODE_OK)
|
||||
return -EINVAL;
|
||||
|
||||
|
|
|
@ -101,7 +101,7 @@ static void find_start_end(unsigned long flags, unsigned long *begin,
|
|||
*begin = new_begin;
|
||||
}
|
||||
} else {
|
||||
*begin = mmap_legacy_base();
|
||||
*begin = current->mm->mmap_legacy_base;
|
||||
*end = TASK_SIZE;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -98,7 +98,7 @@ static unsigned long mmap_base(void)
|
|||
* Bottom-up (legacy) layout on X86_32 did not support randomization, X86_64
|
||||
* does, but not when emulating X86_32
|
||||
*/
|
||||
unsigned long mmap_legacy_base(void)
|
||||
static unsigned long mmap_legacy_base(void)
|
||||
{
|
||||
if (mmap_is_ia32())
|
||||
return TASK_UNMAPPED_BASE;
|
||||
|
@ -112,11 +112,13 @@ unsigned long mmap_legacy_base(void)
|
|||
*/
|
||||
void arch_pick_mmap_layout(struct mm_struct *mm)
|
||||
{
|
||||
mm->mmap_legacy_base = mmap_legacy_base();
|
||||
mm->mmap_base = mmap_base();
|
||||
|
||||
if (mmap_is_legacy()) {
|
||||
mm->mmap_base = mmap_legacy_base();
|
||||
mm->mmap_base = mm->mmap_legacy_base;
|
||||
mm->get_unmapped_area = arch_get_unmapped_area;
|
||||
} else {
|
||||
mm->mmap_base = mmap_base();
|
||||
mm->get_unmapped_area = arch_get_unmapped_area_topdown;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -313,6 +313,17 @@ static void xen_align_and_add_e820_region(u64 start, u64 size, int type)
|
|||
e820_add_region(start, end - start, type);
|
||||
}
|
||||
|
||||
void xen_ignore_unusable(struct e820entry *list, size_t map_size)
|
||||
{
|
||||
struct e820entry *entry;
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0, entry = list; i < map_size; i++, entry++) {
|
||||
if (entry->type == E820_UNUSABLE)
|
||||
entry->type = E820_RAM;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* machine_specific_memory_setup - Hook for machine specific memory setup.
|
||||
**/
|
||||
|
@ -353,6 +364,17 @@ char * __init xen_memory_setup(void)
|
|||
}
|
||||
BUG_ON(rc);
|
||||
|
||||
/*
|
||||
* Xen won't allow a 1:1 mapping to be created to UNUSABLE
|
||||
* regions, so if we're using the machine memory map leave the
|
||||
* region as RAM as it is in the pseudo-physical map.
|
||||
*
|
||||
* UNUSABLE regions in domUs are not handled and will need
|
||||
* a patch in the future.
|
||||
*/
|
||||
if (xen_initial_domain())
|
||||
xen_ignore_unusable(map, memmap.nr_entries);
|
||||
|
||||
/* Make sure the Xen-supplied memory map is well-ordered. */
|
||||
sanitize_e820_map(map, memmap.nr_entries, &memmap.nr_entries);
|
||||
|
||||
|
|
|
@ -694,8 +694,15 @@ static void __init xen_hvm_smp_prepare_cpus(unsigned int max_cpus)
|
|||
static int xen_hvm_cpu_up(unsigned int cpu, struct task_struct *tidle)
|
||||
{
|
||||
int rc;
|
||||
rc = native_cpu_up(cpu, tidle);
|
||||
WARN_ON (xen_smp_intr_init(cpu));
|
||||
/*
|
||||
* xen_smp_intr_init() needs to run before native_cpu_up()
|
||||
* so that IPI vectors are set up on the booting CPU before
|
||||
* it is marked online in native_cpu_up().
|
||||
*/
|
||||
rc = xen_smp_intr_init(cpu);
|
||||
WARN_ON(rc);
|
||||
if (!rc)
|
||||
rc = native_cpu_up(cpu, tidle);
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
|
|
@ -908,9 +908,6 @@ static void acpi_video_device_find_cap(struct acpi_video_device *device)
|
|||
device->cap._DDC = 1;
|
||||
}
|
||||
|
||||
if (acpi_video_init_brightness(device))
|
||||
return;
|
||||
|
||||
if (acpi_video_backlight_support()) {
|
||||
struct backlight_properties props;
|
||||
struct pci_dev *pdev;
|
||||
|
@ -920,6 +917,9 @@ static void acpi_video_device_find_cap(struct acpi_video_device *device)
|
|||
static int count = 0;
|
||||
char *name;
|
||||
|
||||
result = acpi_video_init_brightness(device);
|
||||
if (result)
|
||||
return;
|
||||
name = kasprintf(GFP_KERNEL, "acpi_video%d", count);
|
||||
if (!name)
|
||||
return;
|
||||
|
@ -979,11 +979,6 @@ static void acpi_video_device_find_cap(struct acpi_video_device *device)
|
|||
if (result)
|
||||
printk(KERN_ERR PREFIX "Create sysfs link\n");
|
||||
|
||||
} else {
|
||||
/* Remove the brightness object. */
|
||||
kfree(device->brightness->levels);
|
||||
kfree(device->brightness);
|
||||
device->brightness = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -289,24 +289,24 @@ static int sata_pmp_configure(struct ata_device *dev, int print_info)
|
|||
|
||||
/* Disable sending Early R_OK.
|
||||
* With "cached read" HDD testing and multiple ports busy on a SATA
|
||||
* host controller, 3726 PMP will very rarely drop a deferred
|
||||
* host controller, 3x26 PMP will very rarely drop a deferred
|
||||
* R_OK that was intended for the host. Symptom will be all
|
||||
* 5 drives under test will timeout, get reset, and recover.
|
||||
*/
|
||||
if (vendor == 0x1095 && devid == 0x3726) {
|
||||
if (vendor == 0x1095 && (devid == 0x3726 || devid == 0x3826)) {
|
||||
u32 reg;
|
||||
|
||||
err_mask = sata_pmp_read(&ap->link, PMP_GSCR_SII_POL, ®);
|
||||
if (err_mask) {
|
||||
rc = -EIO;
|
||||
reason = "failed to read Sil3726 Private Register";
|
||||
reason = "failed to read Sil3x26 Private Register";
|
||||
goto fail;
|
||||
}
|
||||
reg &= ~0x1;
|
||||
err_mask = sata_pmp_write(&ap->link, PMP_GSCR_SII_POL, reg);
|
||||
if (err_mask) {
|
||||
rc = -EIO;
|
||||
reason = "failed to write Sil3726 Private Register";
|
||||
reason = "failed to write Sil3x26 Private Register";
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
|
@ -383,8 +383,8 @@ static void sata_pmp_quirks(struct ata_port *ap)
|
|||
u16 devid = sata_pmp_gscr_devid(gscr);
|
||||
struct ata_link *link;
|
||||
|
||||
if (vendor == 0x1095 && devid == 0x3726) {
|
||||
/* sil3726 quirks */
|
||||
if (vendor == 0x1095 && (devid == 0x3726 || devid == 0x3826)) {
|
||||
/* sil3x26 quirks */
|
||||
ata_for_each_link(link, ap, EDGE) {
|
||||
/* link reports offline after LPM */
|
||||
link->flags |= ATA_LFLAG_NO_LPM;
|
||||
|
|
|
@ -293,6 +293,7 @@ static void fsl_sata_set_irq_coalescing(struct ata_host *host,
|
|||
{
|
||||
struct sata_fsl_host_priv *host_priv = host->private_data;
|
||||
void __iomem *hcr_base = host_priv->hcr_base;
|
||||
unsigned long flags;
|
||||
|
||||
if (count > ICC_MAX_INT_COUNT_THRESHOLD)
|
||||
count = ICC_MAX_INT_COUNT_THRESHOLD;
|
||||
|
@ -305,12 +306,12 @@ static void fsl_sata_set_irq_coalescing(struct ata_host *host,
|
|||
(count > ICC_MIN_INT_COUNT_THRESHOLD))
|
||||
ticks = ICC_SAFE_INT_TICKS;
|
||||
|
||||
spin_lock(&host->lock);
|
||||
spin_lock_irqsave(&host->lock, flags);
|
||||
iowrite32((count << 24 | ticks), hcr_base + ICC);
|
||||
|
||||
intr_coalescing_count = count;
|
||||
intr_coalescing_ticks = ticks;
|
||||
spin_unlock(&host->lock);
|
||||
spin_unlock_irqrestore(&host->lock, flags);
|
||||
|
||||
DPRINTK("interrupt coalescing, count = 0x%x, ticks = %x\n",
|
||||
intr_coalescing_count, intr_coalescing_ticks);
|
||||
|
|
|
@ -86,11 +86,11 @@ struct ecx_plat_data {
|
|||
|
||||
#define SGPIO_SIGNALS 3
|
||||
#define ECX_ACTIVITY_BITS 0x300000
|
||||
#define ECX_ACTIVITY_SHIFT 2
|
||||
#define ECX_ACTIVITY_SHIFT 0
|
||||
#define ECX_LOCATE_BITS 0x80000
|
||||
#define ECX_LOCATE_SHIFT 1
|
||||
#define ECX_FAULT_BITS 0x400000
|
||||
#define ECX_FAULT_SHIFT 0
|
||||
#define ECX_FAULT_SHIFT 2
|
||||
static inline int sgpio_bit_shift(struct ecx_plat_data *pdata, u32 port,
|
||||
u32 shift)
|
||||
{
|
||||
|
|
|
@ -500,7 +500,8 @@ static bool psb_intel_sdvo_read_response(struct psb_intel_sdvo *psb_intel_sdvo,
|
|||
&status))
|
||||
goto log_fail;
|
||||
|
||||
while (status == SDVO_CMD_STATUS_PENDING && retry--) {
|
||||
while ((status == SDVO_CMD_STATUS_PENDING ||
|
||||
status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && retry--) {
|
||||
udelay(15);
|
||||
if (!psb_intel_sdvo_read_byte(psb_intel_sdvo,
|
||||
SDVO_I2C_CMD_STATUS,
|
||||
|
|
|
@ -85,9 +85,17 @@ static void i915_gem_unmap_dma_buf(struct dma_buf_attachment *attachment,
|
|||
struct sg_table *sg,
|
||||
enum dma_data_direction dir)
|
||||
{
|
||||
struct drm_i915_gem_object *obj = attachment->dmabuf->priv;
|
||||
|
||||
mutex_lock(&obj->base.dev->struct_mutex);
|
||||
|
||||
dma_unmap_sg(attachment->dev, sg->sgl, sg->nents, dir);
|
||||
sg_free_table(sg);
|
||||
kfree(sg);
|
||||
|
||||
i915_gem_object_unpin_pages(obj);
|
||||
|
||||
mutex_unlock(&obj->base.dev->struct_mutex);
|
||||
}
|
||||
|
||||
static void i915_gem_dmabuf_release(struct dma_buf *dma_buf)
|
||||
|
|
|
@ -752,6 +752,8 @@
|
|||
will not assert AGPBUSY# and will only
|
||||
be delivered when out of C3. */
|
||||
#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
|
||||
#define INSTPM_TLB_INVALIDATE (1<<9)
|
||||
#define INSTPM_SYNC_FLUSH (1<<5)
|
||||
#define ACTHD 0x020c8
|
||||
#define FW_BLC 0x020d8
|
||||
#define FW_BLC2 0x020dc
|
||||
|
|
|
@ -10042,6 +10042,8 @@ struct intel_display_error_state {
|
|||
|
||||
u32 power_well_driver;
|
||||
|
||||
int num_transcoders;
|
||||
|
||||
struct intel_cursor_error_state {
|
||||
u32 control;
|
||||
u32 position;
|
||||
|
@ -10050,16 +10052,7 @@ struct intel_display_error_state {
|
|||
} cursor[I915_MAX_PIPES];
|
||||
|
||||
struct intel_pipe_error_state {
|
||||
enum transcoder cpu_transcoder;
|
||||
u32 conf;
|
||||
u32 source;
|
||||
|
||||
u32 htotal;
|
||||
u32 hblank;
|
||||
u32 hsync;
|
||||
u32 vtotal;
|
||||
u32 vblank;
|
||||
u32 vsync;
|
||||
} pipe[I915_MAX_PIPES];
|
||||
|
||||
struct intel_plane_error_state {
|
||||
|
@ -10071,6 +10064,19 @@ struct intel_display_error_state {
|
|||
u32 surface;
|
||||
u32 tile_offset;
|
||||
} plane[I915_MAX_PIPES];
|
||||
|
||||
struct intel_transcoder_error_state {
|
||||
enum transcoder cpu_transcoder;
|
||||
|
||||
u32 conf;
|
||||
|
||||
u32 htotal;
|
||||
u32 hblank;
|
||||
u32 hsync;
|
||||
u32 vtotal;
|
||||
u32 vblank;
|
||||
u32 vsync;
|
||||
} transcoder[4];
|
||||
};
|
||||
|
||||
struct intel_display_error_state *
|
||||
|
@ -10078,9 +10084,17 @@ intel_display_capture_error_state(struct drm_device *dev)
|
|||
{
|
||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||
struct intel_display_error_state *error;
|
||||
enum transcoder cpu_transcoder;
|
||||
int transcoders[] = {
|
||||
TRANSCODER_A,
|
||||
TRANSCODER_B,
|
||||
TRANSCODER_C,
|
||||
TRANSCODER_EDP,
|
||||
};
|
||||
int i;
|
||||
|
||||
if (INTEL_INFO(dev)->num_pipes == 0)
|
||||
return NULL;
|
||||
|
||||
error = kmalloc(sizeof(*error), GFP_ATOMIC);
|
||||
if (error == NULL)
|
||||
return NULL;
|
||||
|
@ -10089,9 +10103,6 @@ intel_display_capture_error_state(struct drm_device *dev)
|
|||
error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
|
||||
|
||||
for_each_pipe(i) {
|
||||
cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
|
||||
error->pipe[i].cpu_transcoder = cpu_transcoder;
|
||||
|
||||
if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
|
||||
error->cursor[i].control = I915_READ(CURCNTR(i));
|
||||
error->cursor[i].position = I915_READ(CURPOS(i));
|
||||
|
@ -10115,14 +10126,25 @@ intel_display_capture_error_state(struct drm_device *dev)
|
|||
error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
|
||||
}
|
||||
|
||||
error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
|
||||
error->pipe[i].source = I915_READ(PIPESRC(i));
|
||||
error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
|
||||
error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
|
||||
error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
|
||||
error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
|
||||
error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
|
||||
error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
|
||||
}
|
||||
|
||||
error->num_transcoders = INTEL_INFO(dev)->num_pipes;
|
||||
if (HAS_DDI(dev_priv->dev))
|
||||
error->num_transcoders++; /* Account for eDP. */
|
||||
|
||||
for (i = 0; i < error->num_transcoders; i++) {
|
||||
enum transcoder cpu_transcoder = transcoders[i];
|
||||
|
||||
error->transcoder[i].cpu_transcoder = cpu_transcoder;
|
||||
|
||||
error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
|
||||
error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
|
||||
error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
|
||||
error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
|
||||
error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
|
||||
error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
|
||||
error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
|
||||
}
|
||||
|
||||
/* In the code above we read the registers without checking if the power
|
||||
|
@ -10144,22 +10166,16 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
|
|||
{
|
||||
int i;
|
||||
|
||||
if (!error)
|
||||
return;
|
||||
|
||||
err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
|
||||
if (HAS_POWER_WELL(dev))
|
||||
err_printf(m, "PWR_WELL_CTL2: %08x\n",
|
||||
error->power_well_driver);
|
||||
for_each_pipe(i) {
|
||||
err_printf(m, "Pipe [%d]:\n", i);
|
||||
err_printf(m, " CPU transcoder: %c\n",
|
||||
transcoder_name(error->pipe[i].cpu_transcoder));
|
||||
err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
|
||||
err_printf(m, " SRC: %08x\n", error->pipe[i].source);
|
||||
err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
|
||||
err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
|
||||
err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
|
||||
err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
|
||||
err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
|
||||
err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
|
||||
|
||||
err_printf(m, "Plane [%d]:\n", i);
|
||||
err_printf(m, " CNTR: %08x\n", error->plane[i].control);
|
||||
|
@ -10180,5 +10196,17 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
|
|||
err_printf(m, " POS: %08x\n", error->cursor[i].position);
|
||||
err_printf(m, " BASE: %08x\n", error->cursor[i].base);
|
||||
}
|
||||
|
||||
for (i = 0; i < error->num_transcoders; i++) {
|
||||
err_printf(m, " CPU transcoder: %c\n",
|
||||
transcoder_name(error->transcoder[i].cpu_transcoder));
|
||||
err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
|
||||
err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
|
||||
err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
|
||||
err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
|
||||
err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
|
||||
err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
|
||||
err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -968,6 +968,18 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
|
|||
|
||||
I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
|
||||
POSTING_READ(mmio);
|
||||
|
||||
/* Flush the TLB for this page */
|
||||
if (INTEL_INFO(dev)->gen >= 6) {
|
||||
u32 reg = RING_INSTPM(ring->mmio_base);
|
||||
I915_WRITE(reg,
|
||||
_MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
|
||||
INSTPM_SYNC_FLUSH));
|
||||
if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
|
||||
1000))
|
||||
DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
|
||||
ring->name);
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
|
|
|
@ -98,6 +98,8 @@ nouveau_mm_head(struct nouveau_mm *mm, u8 type, u32 size_max, u32 size_min,
|
|||
u32 splitoff;
|
||||
u32 s, e;
|
||||
|
||||
BUG_ON(!type);
|
||||
|
||||
list_for_each_entry(this, &mm->free, fl_entry) {
|
||||
e = this->offset + this->length;
|
||||
s = this->offset;
|
||||
|
@ -162,6 +164,8 @@ nouveau_mm_tail(struct nouveau_mm *mm, u8 type, u32 size_max, u32 size_min,
|
|||
struct nouveau_mm_node *prev, *this, *next;
|
||||
u32 mask = align - 1;
|
||||
|
||||
BUG_ON(!type);
|
||||
|
||||
list_for_each_entry_reverse(this, &mm->free, fl_entry) {
|
||||
u32 e = this->offset + this->length;
|
||||
u32 s = this->offset;
|
||||
|
|
|
@ -20,8 +20,8 @@ nouveau_mc(void *obj)
|
|||
return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_MC];
|
||||
}
|
||||
|
||||
#define nouveau_mc_create(p,e,o,d) \
|
||||
nouveau_mc_create_((p), (e), (o), sizeof(**d), (void **)d)
|
||||
#define nouveau_mc_create(p,e,o,m,d) \
|
||||
nouveau_mc_create_((p), (e), (o), (m), sizeof(**d), (void **)d)
|
||||
#define nouveau_mc_destroy(p) ({ \
|
||||
struct nouveau_mc *pmc = (p); _nouveau_mc_dtor(nv_object(pmc)); \
|
||||
})
|
||||
|
@ -33,7 +33,8 @@ nouveau_mc(void *obj)
|
|||
})
|
||||
|
||||
int nouveau_mc_create_(struct nouveau_object *, struct nouveau_object *,
|
||||
struct nouveau_oclass *, int, void **);
|
||||
struct nouveau_oclass *, const struct nouveau_mc_intr *,
|
||||
int, void **);
|
||||
void _nouveau_mc_dtor(struct nouveau_object *);
|
||||
int _nouveau_mc_init(struct nouveau_object *);
|
||||
int _nouveau_mc_fini(struct nouveau_object *, bool);
|
||||
|
|
|
@ -40,15 +40,15 @@ nv49_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
|
|||
return ret;
|
||||
|
||||
switch (pfb914 & 0x00000003) {
|
||||
case 0x00000000: pfb->ram->type = NV_MEM_TYPE_DDR1; break;
|
||||
case 0x00000001: pfb->ram->type = NV_MEM_TYPE_DDR2; break;
|
||||
case 0x00000002: pfb->ram->type = NV_MEM_TYPE_GDDR3; break;
|
||||
case 0x00000000: ram->type = NV_MEM_TYPE_DDR1; break;
|
||||
case 0x00000001: ram->type = NV_MEM_TYPE_DDR2; break;
|
||||
case 0x00000002: ram->type = NV_MEM_TYPE_GDDR3; break;
|
||||
case 0x00000003: break;
|
||||
}
|
||||
|
||||
pfb->ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000;
|
||||
pfb->ram->parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
|
||||
pfb->ram->tags = nv_rd32(pfb, 0x100320);
|
||||
ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000;
|
||||
ram->parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
|
||||
ram->tags = nv_rd32(pfb, 0x100320);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -38,8 +38,8 @@ nv4e_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
pfb->ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000;
|
||||
pfb->ram->type = NV_MEM_TYPE_STOLEN;
|
||||
ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000;
|
||||
ram->type = NV_MEM_TYPE_STOLEN;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -30,8 +30,9 @@ struct nvc0_ltcg_priv {
|
|||
struct nouveau_ltcg base;
|
||||
u32 part_nr;
|
||||
u32 subp_nr;
|
||||
struct nouveau_mm tags;
|
||||
u32 num_tags;
|
||||
u32 tag_base;
|
||||
struct nouveau_mm tags;
|
||||
struct nouveau_mm_node *tag_ram;
|
||||
};
|
||||
|
||||
|
@ -117,10 +118,6 @@ nvc0_ltcg_init_tag_ram(struct nouveau_fb *pfb, struct nvc0_ltcg_priv *priv)
|
|||
u32 tag_size, tag_margin, tag_align;
|
||||
int ret;
|
||||
|
||||
nv_wr32(priv, 0x17e8d8, priv->part_nr);
|
||||
if (nv_device(pfb)->card_type >= NV_E0)
|
||||
nv_wr32(priv, 0x17e000, priv->part_nr);
|
||||
|
||||
/* tags for 1/4 of VRAM should be enough (8192/4 per GiB of VRAM) */
|
||||
priv->num_tags = (pfb->ram->size >> 17) / 4;
|
||||
if (priv->num_tags > (1 << 17))
|
||||
|
@ -142,7 +139,7 @@ nvc0_ltcg_init_tag_ram(struct nouveau_fb *pfb, struct nvc0_ltcg_priv *priv)
|
|||
tag_size += tag_align;
|
||||
tag_size = (tag_size + 0xfff) >> 12; /* round up */
|
||||
|
||||
ret = nouveau_mm_tail(&pfb->vram, 0, tag_size, tag_size, 1,
|
||||
ret = nouveau_mm_tail(&pfb->vram, 1, tag_size, tag_size, 1,
|
||||
&priv->tag_ram);
|
||||
if (ret) {
|
||||
priv->num_tags = 0;
|
||||
|
@ -152,7 +149,7 @@ nvc0_ltcg_init_tag_ram(struct nouveau_fb *pfb, struct nvc0_ltcg_priv *priv)
|
|||
tag_base += tag_align - 1;
|
||||
ret = do_div(tag_base, tag_align);
|
||||
|
||||
nv_wr32(priv, 0x17e8d4, tag_base);
|
||||
priv->tag_base = tag_base;
|
||||
}
|
||||
ret = nouveau_mm_init(&priv->tags, 0, priv->num_tags, 1);
|
||||
|
||||
|
@ -182,8 +179,6 @@ nvc0_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
|||
}
|
||||
priv->subp_nr = nv_rd32(priv, 0x17e8dc) >> 28;
|
||||
|
||||
nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
|
||||
|
||||
ret = nvc0_ltcg_init_tag_ram(pfb, priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
@ -209,13 +204,32 @@ nvc0_ltcg_dtor(struct nouveau_object *object)
|
|||
nouveau_ltcg_destroy(ltcg);
|
||||
}
|
||||
|
||||
static int
|
||||
nvc0_ltcg_init(struct nouveau_object *object)
|
||||
{
|
||||
struct nouveau_ltcg *ltcg = (struct nouveau_ltcg *)object;
|
||||
struct nvc0_ltcg_priv *priv = (struct nvc0_ltcg_priv *)ltcg;
|
||||
int ret;
|
||||
|
||||
ret = nouveau_ltcg_init(ltcg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
|
||||
nv_wr32(priv, 0x17e8d8, priv->part_nr);
|
||||
if (nv_device(ltcg)->card_type >= NV_E0)
|
||||
nv_wr32(priv, 0x17e000, priv->part_nr);
|
||||
nv_wr32(priv, 0x17e8d4, priv->tag_base);
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct nouveau_oclass
|
||||
nvc0_ltcg_oclass = {
|
||||
.handle = NV_SUBDEV(LTCG, 0xc0),
|
||||
.ofuncs = &(struct nouveau_ofuncs) {
|
||||
.ctor = nvc0_ltcg_ctor,
|
||||
.dtor = nvc0_ltcg_dtor,
|
||||
.init = _nouveau_ltcg_init,
|
||||
.init = nvc0_ltcg_init,
|
||||
.fini = _nouveau_ltcg_fini,
|
||||
},
|
||||
};
|
||||
|
|
|
@ -80,7 +80,9 @@ _nouveau_mc_dtor(struct nouveau_object *object)
|
|||
|
||||
int
|
||||
nouveau_mc_create_(struct nouveau_object *parent, struct nouveau_object *engine,
|
||||
struct nouveau_oclass *oclass, int length, void **pobject)
|
||||
struct nouveau_oclass *oclass,
|
||||
const struct nouveau_mc_intr *intr_map,
|
||||
int length, void **pobject)
|
||||
{
|
||||
struct nouveau_device *device = nv_device(parent);
|
||||
struct nouveau_mc *pmc;
|
||||
|
@ -92,6 +94,8 @@ nouveau_mc_create_(struct nouveau_object *parent, struct nouveau_object *engine,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
pmc->intr_map = intr_map;
|
||||
|
||||
ret = request_irq(device->pdev->irq, nouveau_mc_intr,
|
||||
IRQF_SHARED, "nouveau", pmc);
|
||||
if (ret < 0)
|
||||
|
|
|
@ -50,12 +50,11 @@ nv04_mc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
|||
struct nv04_mc_priv *priv;
|
||||
int ret;
|
||||
|
||||
ret = nouveau_mc_create(parent, engine, oclass, &priv);
|
||||
ret = nouveau_mc_create(parent, engine, oclass, nv04_mc_intr, &priv);
|
||||
*pobject = nv_object(priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
priv->base.intr_map = nv04_mc_intr;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -36,12 +36,11 @@ nv44_mc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
|||
struct nv44_mc_priv *priv;
|
||||
int ret;
|
||||
|
||||
ret = nouveau_mc_create(parent, engine, oclass, &priv);
|
||||
ret = nouveau_mc_create(parent, engine, oclass, nv04_mc_intr, &priv);
|
||||
*pobject = nv_object(priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
priv->base.intr_map = nv04_mc_intr;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -53,12 +53,11 @@ nv50_mc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
|||
struct nv50_mc_priv *priv;
|
||||
int ret;
|
||||
|
||||
ret = nouveau_mc_create(parent, engine, oclass, &priv);
|
||||
ret = nouveau_mc_create(parent, engine, oclass, nv50_mc_intr, &priv);
|
||||
*pobject = nv_object(priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
priv->base.intr_map = nv50_mc_intr;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -54,12 +54,11 @@ nv98_mc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
|||
struct nv98_mc_priv *priv;
|
||||
int ret;
|
||||
|
||||
ret = nouveau_mc_create(parent, engine, oclass, &priv);
|
||||
ret = nouveau_mc_create(parent, engine, oclass, nv98_mc_intr, &priv);
|
||||
*pobject = nv_object(priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
priv->base.intr_map = nv98_mc_intr;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -57,12 +57,11 @@ nvc0_mc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
|||
struct nvc0_mc_priv *priv;
|
||||
int ret;
|
||||
|
||||
ret = nouveau_mc_create(parent, engine, oclass, &priv);
|
||||
ret = nouveau_mc_create(parent, engine, oclass, nvc0_mc_intr, &priv);
|
||||
*pobject = nv_object(priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
priv->base.intr_map = nvc0_mc_intr;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -606,6 +606,24 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
|
|||
regp->ramdac_a34 = 0x1;
|
||||
}
|
||||
|
||||
static int
|
||||
nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
|
||||
{
|
||||
struct nv04_display *disp = nv04_display(crtc->dev);
|
||||
struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb);
|
||||
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
||||
int ret;
|
||||
|
||||
ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
|
||||
if (ret == 0) {
|
||||
if (disp->image[nv_crtc->index])
|
||||
nouveau_bo_unpin(disp->image[nv_crtc->index]);
|
||||
nouveau_bo_ref(nvfb->nvbo, &disp->image[nv_crtc->index]);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* Sets up registers for the given mode/adjusted_mode pair.
|
||||
*
|
||||
|
@ -622,10 +640,15 @@ nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
|
|||
struct drm_device *dev = crtc->dev;
|
||||
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
||||
struct nouveau_drm *drm = nouveau_drm(dev);
|
||||
int ret;
|
||||
|
||||
NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index);
|
||||
drm_mode_debug_printmodeline(adjusted_mode);
|
||||
|
||||
ret = nv_crtc_swap_fbs(crtc, old_fb);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* unlock must come after turning off FP_TG_CONTROL in output_prepare */
|
||||
nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1);
|
||||
|
||||
|
@ -722,6 +745,7 @@ static void nv_crtc_commit(struct drm_crtc *crtc)
|
|||
|
||||
static void nv_crtc_destroy(struct drm_crtc *crtc)
|
||||
{
|
||||
struct nv04_display *disp = nv04_display(crtc->dev);
|
||||
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
||||
|
||||
if (!nv_crtc)
|
||||
|
@ -729,6 +753,10 @@ static void nv_crtc_destroy(struct drm_crtc *crtc)
|
|||
|
||||
drm_crtc_cleanup(crtc);
|
||||
|
||||
if (disp->image[nv_crtc->index])
|
||||
nouveau_bo_unpin(disp->image[nv_crtc->index]);
|
||||
nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]);
|
||||
|
||||
nouveau_bo_unmap(nv_crtc->cursor.nvbo);
|
||||
nouveau_bo_unpin(nv_crtc->cursor.nvbo);
|
||||
nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
|
||||
|
@ -753,6 +781,16 @@ nv_crtc_gamma_load(struct drm_crtc *crtc)
|
|||
nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
|
||||
}
|
||||
|
||||
static void
|
||||
nv_crtc_disable(struct drm_crtc *crtc)
|
||||
{
|
||||
struct nv04_display *disp = nv04_display(crtc->dev);
|
||||
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
||||
if (disp->image[nv_crtc->index])
|
||||
nouveau_bo_unpin(disp->image[nv_crtc->index]);
|
||||
nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]);
|
||||
}
|
||||
|
||||
static void
|
||||
nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, uint32_t start,
|
||||
uint32_t size)
|
||||
|
@ -791,7 +829,6 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
|
|||
struct drm_framebuffer *drm_fb;
|
||||
struct nouveau_framebuffer *fb;
|
||||
int arb_burst, arb_lwm;
|
||||
int ret;
|
||||
|
||||
NV_DEBUG(drm, "index %d\n", nv_crtc->index);
|
||||
|
||||
|
@ -801,10 +838,8 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
|
|||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/* If atomic, we want to switch to the fb we were passed, so
|
||||
* now we update pointers to do that. (We don't pin; just
|
||||
* assume we're already pinned and update the base address.)
|
||||
* now we update pointers to do that.
|
||||
*/
|
||||
if (atomic) {
|
||||
drm_fb = passed_fb;
|
||||
|
@ -812,17 +847,6 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
|
|||
} else {
|
||||
drm_fb = crtc->fb;
|
||||
fb = nouveau_framebuffer(crtc->fb);
|
||||
/* If not atomic, we can go ahead and pin, and unpin the
|
||||
* old fb we were passed.
|
||||
*/
|
||||
ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (passed_fb) {
|
||||
struct nouveau_framebuffer *ofb = nouveau_framebuffer(passed_fb);
|
||||
nouveau_bo_unpin(ofb->nvbo);
|
||||
}
|
||||
}
|
||||
|
||||
nv_crtc->fb.offset = fb->nvbo->bo.offset;
|
||||
|
@ -877,6 +901,9 @@ static int
|
|||
nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
|
||||
struct drm_framebuffer *old_fb)
|
||||
{
|
||||
int ret = nv_crtc_swap_fbs(crtc, old_fb);
|
||||
if (ret)
|
||||
return ret;
|
||||
return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false);
|
||||
}
|
||||
|
||||
|
@ -1027,6 +1054,7 @@ static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = {
|
|||
.mode_set_base = nv04_crtc_mode_set_base,
|
||||
.mode_set_base_atomic = nv04_crtc_mode_set_base_atomic,
|
||||
.load_lut = nv_crtc_gamma_load,
|
||||
.disable = nv_crtc_disable,
|
||||
};
|
||||
|
||||
int
|
||||
|
|
|
@ -81,6 +81,7 @@ struct nv04_display {
|
|||
uint32_t saved_vga_font[4][16384];
|
||||
uint32_t dac_users[4];
|
||||
struct nouveau_object *core;
|
||||
struct nouveau_bo *image[2];
|
||||
};
|
||||
|
||||
static inline struct nv04_display *
|
||||
|
|
|
@ -577,6 +577,9 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
|
|||
ret = nv50_display_flip_next(crtc, fb, chan, 0);
|
||||
if (ret)
|
||||
goto fail_unreserve;
|
||||
} else {
|
||||
struct nv04_display *dispnv04 = nv04_display(dev);
|
||||
nouveau_bo_ref(new_bo, &dispnv04->image[nouveau_crtc(crtc)->index]);
|
||||
}
|
||||
|
||||
ret = nouveau_page_flip_emit(chan, old_bo, new_bo, s, &fence);
|
||||
|
|
|
@ -131,7 +131,7 @@ nv40_calc_pll(struct drm_device *dev, u32 reg, struct nvbios_pll *pll,
|
|||
if (clk < pll->vco1.max_freq)
|
||||
pll->vco2.max_freq = 0;
|
||||
|
||||
pclk->pll_calc(pclk, pll, clk, &coef);
|
||||
ret = pclk->pll_calc(pclk, pll, clk, &coef);
|
||||
if (ret == 0)
|
||||
return -ERANGE;
|
||||
|
||||
|
|
|
@ -2163,7 +2163,7 @@ void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
|
|||
WREG32(reg, tmp_); \
|
||||
} while (0)
|
||||
#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
|
||||
#define WREG32_OR(reg, or) WREG32_P(reg, or, ~or)
|
||||
#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
|
||||
#define WREG32_PLL_P(reg, val, mask) \
|
||||
do { \
|
||||
uint32_t tmp_ = RREG32_PLL(reg); \
|
||||
|
|
|
@ -356,6 +356,14 @@ static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (bo->tbo.sync_obj) {
|
||||
r = radeon_fence_wait(bo->tbo.sync_obj, false);
|
||||
if (r) {
|
||||
DRM_ERROR("Failed waiting for UVD message (%d)!\n", r);
|
||||
return r;
|
||||
}
|
||||
}
|
||||
|
||||
r = radeon_bo_kmap(bo, &ptr);
|
||||
if (r) {
|
||||
DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
|
||||
|
|
|
@ -744,10 +744,10 @@ static void rv770_init_golden_registers(struct radeon_device *rdev)
|
|||
(const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
|
||||
radeon_program_register_sequence(rdev,
|
||||
rv730_golden_registers,
|
||||
(const u32)ARRAY_SIZE(rv770_golden_registers));
|
||||
(const u32)ARRAY_SIZE(rv730_golden_registers));
|
||||
radeon_program_register_sequence(rdev,
|
||||
rv730_mgcg_init,
|
||||
(const u32)ARRAY_SIZE(rv770_mgcg_init));
|
||||
(const u32)ARRAY_SIZE(rv730_mgcg_init));
|
||||
break;
|
||||
case CHIP_RV710:
|
||||
radeon_program_register_sequence(rdev,
|
||||
|
@ -758,18 +758,18 @@ static void rv770_init_golden_registers(struct radeon_device *rdev)
|
|||
(const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
|
||||
radeon_program_register_sequence(rdev,
|
||||
rv710_golden_registers,
|
||||
(const u32)ARRAY_SIZE(rv770_golden_registers));
|
||||
(const u32)ARRAY_SIZE(rv710_golden_registers));
|
||||
radeon_program_register_sequence(rdev,
|
||||
rv710_mgcg_init,
|
||||
(const u32)ARRAY_SIZE(rv770_mgcg_init));
|
||||
(const u32)ARRAY_SIZE(rv710_mgcg_init));
|
||||
break;
|
||||
case CHIP_RV740:
|
||||
radeon_program_register_sequence(rdev,
|
||||
rv740_golden_registers,
|
||||
(const u32)ARRAY_SIZE(rv770_golden_registers));
|
||||
(const u32)ARRAY_SIZE(rv740_golden_registers));
|
||||
radeon_program_register_sequence(rdev,
|
||||
rv740_mgcg_init,
|
||||
(const u32)ARRAY_SIZE(rv770_mgcg_init));
|
||||
(const u32)ARRAY_SIZE(rv740_mgcg_init));
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
|
|
|
@ -232,7 +232,8 @@ static int adjd_s311_read_raw(struct iio_dev *indio_dev,
|
|||
|
||||
switch (mask) {
|
||||
case IIO_CHAN_INFO_RAW:
|
||||
ret = adjd_s311_read_data(indio_dev, chan->address, val);
|
||||
ret = adjd_s311_read_data(indio_dev,
|
||||
ADJD_S311_DATA_REG(chan->address), val);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
return IIO_VAL_INT;
|
||||
|
|
|
@ -959,23 +959,21 @@ out:
|
|||
return r;
|
||||
}
|
||||
|
||||
static void remove_mapping(struct mq_policy *mq, dm_oblock_t oblock)
|
||||
static void mq_remove_mapping(struct dm_cache_policy *p, dm_oblock_t oblock)
|
||||
{
|
||||
struct entry *e = hash_lookup(mq, oblock);
|
||||
struct mq_policy *mq = to_mq_policy(p);
|
||||
struct entry *e;
|
||||
|
||||
mutex_lock(&mq->lock);
|
||||
|
||||
e = hash_lookup(mq, oblock);
|
||||
|
||||
BUG_ON(!e || !e->in_cache);
|
||||
|
||||
del(mq, e);
|
||||
e->in_cache = false;
|
||||
push(mq, e);
|
||||
}
|
||||
|
||||
static void mq_remove_mapping(struct dm_cache_policy *p, dm_oblock_t oblock)
|
||||
{
|
||||
struct mq_policy *mq = to_mq_policy(p);
|
||||
|
||||
mutex_lock(&mq->lock);
|
||||
remove_mapping(mq, oblock);
|
||||
mutex_unlock(&mq->lock);
|
||||
}
|
||||
|
||||
|
|
|
@ -1333,6 +1333,8 @@ enum {
|
|||
BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
|
||||
BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
|
||||
BNX2X_SP_RTNL_HYPERVISOR_VLAN,
|
||||
BNX2X_SP_RTNL_TX_STOP,
|
||||
BNX2X_SP_RTNL_TX_RESUME,
|
||||
};
|
||||
|
||||
struct bnx2x_prev_path_list {
|
||||
|
|
|
@ -30,10 +30,8 @@
|
|||
#include "bnx2x_dcb.h"
|
||||
|
||||
/* forward declarations of dcbx related functions */
|
||||
static int bnx2x_dcbx_stop_hw_tx(struct bnx2x *bp);
|
||||
static void bnx2x_pfc_set_pfc(struct bnx2x *bp);
|
||||
static void bnx2x_dcbx_update_ets_params(struct bnx2x *bp);
|
||||
static int bnx2x_dcbx_resume_hw_tx(struct bnx2x *bp);
|
||||
static void bnx2x_dcbx_get_ets_pri_pg_tbl(struct bnx2x *bp,
|
||||
u32 *set_configuration_ets_pg,
|
||||
u32 *pri_pg_tbl);
|
||||
|
@ -425,30 +423,52 @@ static void bnx2x_pfc_set_pfc(struct bnx2x *bp)
|
|||
bnx2x_pfc_clear(bp);
|
||||
}
|
||||
|
||||
static int bnx2x_dcbx_stop_hw_tx(struct bnx2x *bp)
|
||||
int bnx2x_dcbx_stop_hw_tx(struct bnx2x *bp)
|
||||
{
|
||||
struct bnx2x_func_state_params func_params = {NULL};
|
||||
int rc;
|
||||
|
||||
func_params.f_obj = &bp->func_obj;
|
||||
func_params.cmd = BNX2X_F_CMD_TX_STOP;
|
||||
|
||||
__set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
|
||||
__set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
|
||||
|
||||
DP(BNX2X_MSG_DCB, "STOP TRAFFIC\n");
|
||||
return bnx2x_func_state_change(bp, &func_params);
|
||||
|
||||
rc = bnx2x_func_state_change(bp, &func_params);
|
||||
if (rc) {
|
||||
BNX2X_ERR("Unable to hold traffic for HW configuration\n");
|
||||
bnx2x_panic();
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int bnx2x_dcbx_resume_hw_tx(struct bnx2x *bp)
|
||||
int bnx2x_dcbx_resume_hw_tx(struct bnx2x *bp)
|
||||
{
|
||||
struct bnx2x_func_state_params func_params = {NULL};
|
||||
struct bnx2x_func_tx_start_params *tx_params =
|
||||
&func_params.params.tx_start;
|
||||
int rc;
|
||||
|
||||
func_params.f_obj = &bp->func_obj;
|
||||
func_params.cmd = BNX2X_F_CMD_TX_START;
|
||||
|
||||
__set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
|
||||
__set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
|
||||
|
||||
bnx2x_dcbx_fw_struct(bp, tx_params);
|
||||
|
||||
DP(BNX2X_MSG_DCB, "START TRAFFIC\n");
|
||||
return bnx2x_func_state_change(bp, &func_params);
|
||||
|
||||
rc = bnx2x_func_state_change(bp, &func_params);
|
||||
if (rc) {
|
||||
BNX2X_ERR("Unable to resume traffic after HW configuration\n");
|
||||
bnx2x_panic();
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void bnx2x_dcbx_2cos_limit_update_ets_config(struct bnx2x *bp)
|
||||
|
@ -744,7 +764,9 @@ void bnx2x_dcbx_set_params(struct bnx2x *bp, u32 state)
|
|||
if (IS_MF(bp))
|
||||
bnx2x_link_sync_notify(bp);
|
||||
|
||||
bnx2x_dcbx_stop_hw_tx(bp);
|
||||
set_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state);
|
||||
|
||||
schedule_delayed_work(&bp->sp_rtnl_task, 0);
|
||||
|
||||
return;
|
||||
}
|
||||
|
@ -757,7 +779,9 @@ void bnx2x_dcbx_set_params(struct bnx2x *bp, u32 state)
|
|||
/* ets may affect cmng configuration: reinit it in hw */
|
||||
bnx2x_set_local_cmng(bp);
|
||||
|
||||
bnx2x_dcbx_resume_hw_tx(bp);
|
||||
set_bit(BNX2X_SP_RTNL_TX_RESUME, &bp->sp_rtnl_state);
|
||||
|
||||
schedule_delayed_work(&bp->sp_rtnl_task, 0);
|
||||
|
||||
return;
|
||||
case BNX2X_DCBX_STATE_TX_RELEASED:
|
||||
|
@ -2367,21 +2391,24 @@ static u8 bnx2x_dcbnl_get_featcfg(struct net_device *netdev, int featid,
|
|||
case DCB_FEATCFG_ATTR_PG:
|
||||
if (bp->dcbx_local_feat.ets.enabled)
|
||||
*flags |= DCB_FEATCFG_ENABLE;
|
||||
if (bp->dcbx_error & DCBX_LOCAL_ETS_ERROR)
|
||||
if (bp->dcbx_error & (DCBX_LOCAL_ETS_ERROR |
|
||||
DCBX_REMOTE_MIB_ERROR))
|
||||
*flags |= DCB_FEATCFG_ERROR;
|
||||
break;
|
||||
case DCB_FEATCFG_ATTR_PFC:
|
||||
if (bp->dcbx_local_feat.pfc.enabled)
|
||||
*flags |= DCB_FEATCFG_ENABLE;
|
||||
if (bp->dcbx_error & (DCBX_LOCAL_PFC_ERROR |
|
||||
DCBX_LOCAL_PFC_MISMATCH))
|
||||
DCBX_LOCAL_PFC_MISMATCH |
|
||||
DCBX_REMOTE_MIB_ERROR))
|
||||
*flags |= DCB_FEATCFG_ERROR;
|
||||
break;
|
||||
case DCB_FEATCFG_ATTR_APP:
|
||||
if (bp->dcbx_local_feat.app.enabled)
|
||||
*flags |= DCB_FEATCFG_ENABLE;
|
||||
if (bp->dcbx_error & (DCBX_LOCAL_APP_ERROR |
|
||||
DCBX_LOCAL_APP_MISMATCH))
|
||||
DCBX_LOCAL_APP_MISMATCH |
|
||||
DCBX_REMOTE_MIB_ERROR))
|
||||
*flags |= DCB_FEATCFG_ERROR;
|
||||
break;
|
||||
default:
|
||||
|
|
|
@ -199,4 +199,7 @@ extern const struct dcbnl_rtnl_ops bnx2x_dcbnl_ops;
|
|||
int bnx2x_dcbnl_update_applist(struct bnx2x *bp, bool delall);
|
||||
#endif /* BCM_DCBNL */
|
||||
|
||||
int bnx2x_dcbx_stop_hw_tx(struct bnx2x *bp);
|
||||
int bnx2x_dcbx_resume_hw_tx(struct bnx2x *bp);
|
||||
|
||||
#endif /* BNX2X_DCB_H */
|
||||
|
|
|
@ -2261,6 +2261,23 @@ static void bnx2x_set_requested_fc(struct bnx2x *bp)
|
|||
bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
|
||||
}
|
||||
|
||||
static void bnx2x_init_dropless_fc(struct bnx2x *bp)
|
||||
{
|
||||
u32 pause_enabled = 0;
|
||||
|
||||
if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
|
||||
if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
|
||||
pause_enabled = 1;
|
||||
|
||||
REG_WR(bp, BAR_USTRORM_INTMEM +
|
||||
USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
|
||||
pause_enabled);
|
||||
}
|
||||
|
||||
DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
|
||||
pause_enabled ? "enabled" : "disabled");
|
||||
}
|
||||
|
||||
int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
|
||||
{
|
||||
int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
|
||||
|
@ -2294,6 +2311,8 @@ int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
|
|||
|
||||
bnx2x_release_phy_lock(bp);
|
||||
|
||||
bnx2x_init_dropless_fc(bp);
|
||||
|
||||
bnx2x_calc_fc_adv(bp);
|
||||
|
||||
if (bp->link_vars.link_up) {
|
||||
|
@ -2315,6 +2334,8 @@ void bnx2x_link_set(struct bnx2x *bp)
|
|||
bnx2x_phy_init(&bp->link_params, &bp->link_vars);
|
||||
bnx2x_release_phy_lock(bp);
|
||||
|
||||
bnx2x_init_dropless_fc(bp);
|
||||
|
||||
bnx2x_calc_fc_adv(bp);
|
||||
} else
|
||||
BNX2X_ERR("Bootcode is missing - can not set link\n");
|
||||
|
@ -2556,21 +2577,10 @@ static void bnx2x_link_attn(struct bnx2x *bp)
|
|||
|
||||
bnx2x_link_update(&bp->link_params, &bp->link_vars);
|
||||
|
||||
bnx2x_init_dropless_fc(bp);
|
||||
|
||||
if (bp->link_vars.link_up) {
|
||||
|
||||
/* dropless flow control */
|
||||
if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
|
||||
int port = BP_PORT(bp);
|
||||
u32 pause_enabled = 0;
|
||||
|
||||
if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
|
||||
pause_enabled = 1;
|
||||
|
||||
REG_WR(bp, BAR_USTRORM_INTMEM +
|
||||
USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
|
||||
pause_enabled);
|
||||
}
|
||||
|
||||
if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
|
||||
struct host_port_stats *pstats;
|
||||
|
||||
|
@ -9645,6 +9655,12 @@ sp_rtnl_not_reset:
|
|||
&bp->sp_rtnl_state))
|
||||
bnx2x_pf_set_vfs_vlan(bp);
|
||||
|
||||
if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state))
|
||||
bnx2x_dcbx_stop_hw_tx(bp);
|
||||
|
||||
if (test_and_clear_bit(BNX2X_SP_RTNL_TX_RESUME, &bp->sp_rtnl_state))
|
||||
bnx2x_dcbx_resume_hw_tx(bp);
|
||||
|
||||
/* work which needs rtnl lock not-taken (as it takes the lock itself and
|
||||
* can be called from other contexts as well)
|
||||
*/
|
||||
|
@ -11147,6 +11163,9 @@ static bool bnx2x_get_dropless_info(struct bnx2x *bp)
|
|||
int tmp;
|
||||
u32 cfg;
|
||||
|
||||
if (IS_VF(bp))
|
||||
return 0;
|
||||
|
||||
if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
|
||||
/* Take function: tmp = func */
|
||||
tmp = BP_ABS_FUNC(bp);
|
||||
|
|
|
@ -1747,11 +1747,8 @@ void bnx2x_iov_init_dq(struct bnx2x *bp)
|
|||
|
||||
void bnx2x_iov_init_dmae(struct bnx2x *bp)
|
||||
{
|
||||
DP(BNX2X_MSG_IOV, "SRIOV is %s\n", IS_SRIOV(bp) ? "ON" : "OFF");
|
||||
if (!IS_SRIOV(bp))
|
||||
return;
|
||||
|
||||
REG_WR(bp, DMAE_REG_BACKWARD_COMP_EN, 0);
|
||||
if (pci_find_ext_capability(bp->pdev, PCI_EXT_CAP_ID_SRIOV))
|
||||
REG_WR(bp, DMAE_REG_BACKWARD_COMP_EN, 0);
|
||||
}
|
||||
|
||||
static int bnx2x_vf_bus(struct bnx2x *bp, int vfid)
|
||||
|
@ -3084,8 +3081,9 @@ void bnx2x_disable_sriov(struct bnx2x *bp)
|
|||
pci_disable_sriov(bp->pdev);
|
||||
}
|
||||
|
||||
static int bnx2x_vf_ndo_sanity(struct bnx2x *bp, int vfidx,
|
||||
struct bnx2x_virtf *vf)
|
||||
static int bnx2x_vf_ndo_prep(struct bnx2x *bp, int vfidx,
|
||||
struct bnx2x_virtf **vf,
|
||||
struct pf_vf_bulletin_content **bulletin)
|
||||
{
|
||||
if (bp->state != BNX2X_STATE_OPEN) {
|
||||
BNX2X_ERR("vf ndo called though PF is down\n");
|
||||
|
@ -3103,12 +3101,22 @@ static int bnx2x_vf_ndo_sanity(struct bnx2x *bp, int vfidx,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!vf) {
|
||||
/* init members */
|
||||
*vf = BP_VF(bp, vfidx);
|
||||
*bulletin = BP_VF_BULLETIN(bp, vfidx);
|
||||
|
||||
if (!*vf) {
|
||||
BNX2X_ERR("vf ndo called but vf was null. vfidx was %d\n",
|
||||
vfidx);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!*bulletin) {
|
||||
BNX2X_ERR("vf ndo called but Bulletin Board struct is null. vfidx was %d\n",
|
||||
vfidx);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -3116,17 +3124,19 @@ int bnx2x_get_vf_config(struct net_device *dev, int vfidx,
|
|||
struct ifla_vf_info *ivi)
|
||||
{
|
||||
struct bnx2x *bp = netdev_priv(dev);
|
||||
struct bnx2x_virtf *vf = BP_VF(bp, vfidx);
|
||||
struct bnx2x_vlan_mac_obj *mac_obj = &bnx2x_vfq(vf, 0, mac_obj);
|
||||
struct bnx2x_vlan_mac_obj *vlan_obj = &bnx2x_vfq(vf, 0, vlan_obj);
|
||||
struct pf_vf_bulletin_content *bulletin = BP_VF_BULLETIN(bp, vfidx);
|
||||
struct bnx2x_virtf *vf = NULL;
|
||||
struct pf_vf_bulletin_content *bulletin = NULL;
|
||||
struct bnx2x_vlan_mac_obj *mac_obj;
|
||||
struct bnx2x_vlan_mac_obj *vlan_obj;
|
||||
int rc;
|
||||
|
||||
/* sanity */
|
||||
rc = bnx2x_vf_ndo_sanity(bp, vfidx, vf);
|
||||
/* sanity and init */
|
||||
rc = bnx2x_vf_ndo_prep(bp, vfidx, &vf, &bulletin);
|
||||
if (rc)
|
||||
return rc;
|
||||
if (!mac_obj || !vlan_obj || !bulletin) {
|
||||
mac_obj = &bnx2x_vfq(vf, 0, mac_obj);
|
||||
vlan_obj = &bnx2x_vfq(vf, 0, vlan_obj);
|
||||
if (!mac_obj || !vlan_obj) {
|
||||
BNX2X_ERR("VF partially initialized\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
@ -3183,11 +3193,11 @@ int bnx2x_set_vf_mac(struct net_device *dev, int vfidx, u8 *mac)
|
|||
{
|
||||
struct bnx2x *bp = netdev_priv(dev);
|
||||
int rc, q_logical_state;
|
||||
struct bnx2x_virtf *vf = BP_VF(bp, vfidx);
|
||||
struct pf_vf_bulletin_content *bulletin = BP_VF_BULLETIN(bp, vfidx);
|
||||
struct bnx2x_virtf *vf = NULL;
|
||||
struct pf_vf_bulletin_content *bulletin = NULL;
|
||||
|
||||
/* sanity */
|
||||
rc = bnx2x_vf_ndo_sanity(bp, vfidx, vf);
|
||||
/* sanity and init */
|
||||
rc = bnx2x_vf_ndo_prep(bp, vfidx, &vf, &bulletin);
|
||||
if (rc)
|
||||
return rc;
|
||||
if (!is_valid_ether_addr(mac)) {
|
||||
|
@ -3249,11 +3259,11 @@ int bnx2x_set_vf_vlan(struct net_device *dev, int vfidx, u16 vlan, u8 qos)
|
|||
{
|
||||
struct bnx2x *bp = netdev_priv(dev);
|
||||
int rc, q_logical_state;
|
||||
struct bnx2x_virtf *vf = BP_VF(bp, vfidx);
|
||||
struct pf_vf_bulletin_content *bulletin = BP_VF_BULLETIN(bp, vfidx);
|
||||
struct bnx2x_virtf *vf = NULL;
|
||||
struct pf_vf_bulletin_content *bulletin = NULL;
|
||||
|
||||
/* sanity */
|
||||
rc = bnx2x_vf_ndo_sanity(bp, vfidx, vf);
|
||||
/* sanity and init */
|
||||
rc = bnx2x_vf_ndo_prep(bp, vfidx, &vf, &bulletin);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
|
|
|
@ -2563,8 +2563,8 @@ static int be_close(struct net_device *netdev)
|
|||
/* Wait for all pending tx completions to arrive so that
|
||||
* all tx skbs are freed.
|
||||
*/
|
||||
be_tx_compl_clean(adapter);
|
||||
netif_tx_disable(netdev);
|
||||
be_tx_compl_clean(adapter);
|
||||
|
||||
be_rx_qs_destroy(adapter);
|
||||
|
||||
|
|
|
@ -7088,7 +7088,7 @@ rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
|
||||
RTL_W8(Cfg9346, Cfg9346_Unlock);
|
||||
RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
|
||||
RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
|
||||
RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
|
||||
if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
|
||||
tp->features |= RTL_FEATURE_WOL;
|
||||
if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
|
||||
|
|
|
@ -675,7 +675,7 @@ s32 efx_filter_insert_filter(struct efx_nic *efx, struct efx_filter_spec *spec,
|
|||
BUILD_BUG_ON(EFX_FILTER_INDEX_UC_DEF != 0);
|
||||
BUILD_BUG_ON(EFX_FILTER_INDEX_MC_DEF !=
|
||||
EFX_FILTER_MC_DEF - EFX_FILTER_UC_DEF);
|
||||
rep_index = spec->type - EFX_FILTER_INDEX_UC_DEF;
|
||||
rep_index = spec->type - EFX_FILTER_UC_DEF;
|
||||
ins_index = rep_index;
|
||||
|
||||
spin_lock_bh(&state->lock);
|
||||
|
|
|
@ -210,8 +210,7 @@ static int via_init_one(struct pci_dev *pcidev, const struct pci_device_id *id)
|
|||
pci_write_config_byte(pcidev,0x42,(bTmp | 0xf0));
|
||||
pci_write_config_byte(pcidev,0x5a,0xc0);
|
||||
WriteLPCReg(0x28, 0x70 );
|
||||
if (via_ircc_open(pcidev, &info, 0x3076) == 0)
|
||||
rc=0;
|
||||
rc = via_ircc_open(pcidev, &info, 0x3076);
|
||||
} else
|
||||
rc = -ENODEV; //IR not turn on
|
||||
} else { //Not VT1211
|
||||
|
@ -249,8 +248,7 @@ static int via_init_one(struct pci_dev *pcidev, const struct pci_device_id *id)
|
|||
info.irq=FirIRQ;
|
||||
info.dma=FirDRQ1;
|
||||
info.dma2=FirDRQ0;
|
||||
if (via_ircc_open(pcidev, &info, 0x3096) == 0)
|
||||
rc=0;
|
||||
rc = via_ircc_open(pcidev, &info, 0x3096);
|
||||
} else
|
||||
rc = -ENODEV; //IR not turn on !!!!!
|
||||
}//Not VT1211
|
||||
|
|
|
@ -68,6 +68,8 @@ static const struct proto_ops macvtap_socket_ops;
|
|||
#define TUN_OFFLOADS (NETIF_F_HW_CSUM | NETIF_F_TSO_ECN | NETIF_F_TSO | \
|
||||
NETIF_F_TSO6 | NETIF_F_UFO)
|
||||
#define RX_OFFLOADS (NETIF_F_GRO | NETIF_F_LRO)
|
||||
#define TAP_FEATURES (NETIF_F_GSO | NETIF_F_SG)
|
||||
|
||||
/*
|
||||
* RCU usage:
|
||||
* The macvtap_queue and the macvlan_dev are loosely coupled, the
|
||||
|
@ -278,7 +280,8 @@ static int macvtap_forward(struct net_device *dev, struct sk_buff *skb)
|
|||
{
|
||||
struct macvlan_dev *vlan = netdev_priv(dev);
|
||||
struct macvtap_queue *q = macvtap_get_queue(dev, skb);
|
||||
netdev_features_t features;
|
||||
netdev_features_t features = TAP_FEATURES;
|
||||
|
||||
if (!q)
|
||||
goto drop;
|
||||
|
||||
|
@ -287,9 +290,11 @@ static int macvtap_forward(struct net_device *dev, struct sk_buff *skb)
|
|||
|
||||
skb->dev = dev;
|
||||
/* Apply the forward feature mask so that we perform segmentation
|
||||
* according to users wishes.
|
||||
* according to users wishes. This only works if VNET_HDR is
|
||||
* enabled.
|
||||
*/
|
||||
features = netif_skb_features(skb) & vlan->tap_features;
|
||||
if (q->flags & IFF_VNET_HDR)
|
||||
features |= vlan->tap_features;
|
||||
if (netif_needs_gso(skb, features)) {
|
||||
struct sk_buff *segs = __skb_gso_segment(skb, features, false);
|
||||
|
||||
|
@ -1064,8 +1069,7 @@ static int set_offload(struct macvtap_queue *q, unsigned long arg)
|
|||
/* tap_features are the same as features on tun/tap and
|
||||
* reflect user expectations.
|
||||
*/
|
||||
vlan->tap_features = vlan->dev->features &
|
||||
(feature_mask | ~TUN_OFFLOADS);
|
||||
vlan->tap_features = feature_mask;
|
||||
vlan->set_features = features;
|
||||
netdev_update_features(vlan->dev);
|
||||
|
||||
|
@ -1161,10 +1165,6 @@ static long macvtap_ioctl(struct file *file, unsigned int cmd,
|
|||
TUN_F_TSO_ECN | TUN_F_UFO))
|
||||
return -EINVAL;
|
||||
|
||||
/* TODO: only accept frames with the features that
|
||||
got enabled for forwarded frames */
|
||||
if (!(q->flags & IFF_VNET_HDR))
|
||||
return -EINVAL;
|
||||
rtnl_lock();
|
||||
ret = set_offload(q, arg);
|
||||
rtnl_unlock();
|
||||
|
|
|
@ -23,7 +23,7 @@
|
|||
#define RTL821x_INER_INIT 0x6400
|
||||
#define RTL821x_INSR 0x13
|
||||
|
||||
#define RTL8211E_INER_LINK_STAT 0x10
|
||||
#define RTL8211E_INER_LINK_STATUS 0x400
|
||||
|
||||
MODULE_DESCRIPTION("Realtek PHY driver");
|
||||
MODULE_AUTHOR("Johnson Leung");
|
||||
|
@ -57,7 +57,7 @@ static int rtl8211e_config_intr(struct phy_device *phydev)
|
|||
|
||||
if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
|
||||
err = phy_write(phydev, RTL821x_INER,
|
||||
RTL8211E_INER_LINK_STAT);
|
||||
RTL8211E_INER_LINK_STATUS);
|
||||
else
|
||||
err = phy_write(phydev, RTL821x_INER, 0);
|
||||
|
||||
|
|
|
@ -2816,13 +2816,16 @@ exit:
|
|||
static int hso_get_config_data(struct usb_interface *interface)
|
||||
{
|
||||
struct usb_device *usbdev = interface_to_usbdev(interface);
|
||||
u8 config_data[17];
|
||||
u8 *config_data = kmalloc(17, GFP_KERNEL);
|
||||
u32 if_num = interface->altsetting->desc.bInterfaceNumber;
|
||||
s32 result;
|
||||
|
||||
if (!config_data)
|
||||
return -ENOMEM;
|
||||
if (usb_control_msg(usbdev, usb_rcvctrlpipe(usbdev, 0),
|
||||
0x86, 0xC0, 0, 0, config_data, 17,
|
||||
USB_CTRL_SET_TIMEOUT) != 0x11) {
|
||||
kfree(config_data);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
|
@ -2873,6 +2876,7 @@ static int hso_get_config_data(struct usb_interface *interface)
|
|||
if (config_data[16] & 0x1)
|
||||
result |= HSO_INFO_CRC_BUG;
|
||||
|
||||
kfree(config_data);
|
||||
return result;
|
||||
}
|
||||
|
||||
|
@ -2886,6 +2890,11 @@ static int hso_probe(struct usb_interface *interface,
|
|||
struct hso_shared_int *shared_int;
|
||||
struct hso_device *tmp_dev = NULL;
|
||||
|
||||
if (interface->cur_altsetting->desc.bInterfaceClass != 0xFF) {
|
||||
dev_err(&interface->dev, "Not our interface\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if_num = interface->altsetting->desc.bInterfaceNumber;
|
||||
|
||||
/* Get the interface/port specification from either driver_info or from
|
||||
|
@ -2895,10 +2904,6 @@ static int hso_probe(struct usb_interface *interface,
|
|||
else
|
||||
port_spec = hso_get_config_data(interface);
|
||||
|
||||
if (interface->cur_altsetting->desc.bInterfaceClass != 0xFF) {
|
||||
dev_err(&interface->dev, "Not our interface\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
/* Check if we need to switch to alt interfaces prior to port
|
||||
* configuration */
|
||||
if (interface->num_altsetting > 1)
|
||||
|
|
|
@ -523,9 +523,9 @@ static int prism2_ioctl_giwaplist(struct net_device *dev,
|
|||
|
||||
data->length = prism2_ap_get_sta_qual(local, addr, qual, IW_MAX_AP, 1);
|
||||
|
||||
memcpy(extra, &addr, sizeof(struct sockaddr) * data->length);
|
||||
memcpy(extra, addr, sizeof(struct sockaddr) * data->length);
|
||||
data->flags = 1; /* has quality information */
|
||||
memcpy(extra + sizeof(struct sockaddr) * data->length, &qual,
|
||||
memcpy(extra + sizeof(struct sockaddr) * data->length, qual,
|
||||
sizeof(struct iw_quality) * data->length);
|
||||
|
||||
kfree(addr);
|
||||
|
|
|
@ -1068,7 +1068,10 @@ void iwl_chswitch_done(struct iwl_priv *priv, bool is_success)
|
|||
if (test_bit(STATUS_EXIT_PENDING, &priv->status))
|
||||
return;
|
||||
|
||||
if (test_and_clear_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status))
|
||||
if (!test_and_clear_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status))
|
||||
return;
|
||||
|
||||
if (ctx->vif)
|
||||
ieee80211_chswitch_done(ctx->vif, is_success);
|
||||
}
|
||||
|
||||
|
|
|
@ -97,8 +97,6 @@
|
|||
|
||||
#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
|
||||
|
||||
#define APMG_RTC_INT_STT_RFKILL (0x10000000)
|
||||
|
||||
/* Device system time */
|
||||
#define DEVICE_SYSTEM_TIME_REG 0xA0206C
|
||||
|
||||
|
|
|
@ -138,6 +138,20 @@ static void iwl_mvm_roc_finished(struct iwl_mvm *mvm)
|
|||
schedule_work(&mvm->roc_done_wk);
|
||||
}
|
||||
|
||||
static bool iwl_mvm_te_check_disconnect(struct iwl_mvm *mvm,
|
||||
struct ieee80211_vif *vif,
|
||||
const char *errmsg)
|
||||
{
|
||||
if (vif->type != NL80211_IFTYPE_STATION)
|
||||
return false;
|
||||
if (vif->bss_conf.assoc && vif->bss_conf.dtim_period)
|
||||
return false;
|
||||
if (errmsg)
|
||||
IWL_ERR(mvm, "%s\n", errmsg);
|
||||
ieee80211_connection_loss(vif);
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* Handles a FW notification for an event that is known to the driver.
|
||||
*
|
||||
|
@ -163,8 +177,13 @@ static void iwl_mvm_te_handle_notif(struct iwl_mvm *mvm,
|
|||
* P2P Device discoveribility, while there are other higher priority
|
||||
* events in the system).
|
||||
*/
|
||||
WARN_ONCE(!le32_to_cpu(notif->status),
|
||||
"Failed to schedule time event\n");
|
||||
if (WARN_ONCE(!le32_to_cpu(notif->status),
|
||||
"Failed to schedule time event\n")) {
|
||||
if (iwl_mvm_te_check_disconnect(mvm, te_data->vif, NULL)) {
|
||||
iwl_mvm_te_clear_data(mvm, te_data);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
if (le32_to_cpu(notif->action) & TE_NOTIF_HOST_EVENT_END) {
|
||||
IWL_DEBUG_TE(mvm,
|
||||
|
@ -180,14 +199,8 @@ static void iwl_mvm_te_handle_notif(struct iwl_mvm *mvm,
|
|||
* By now, we should have finished association
|
||||
* and know the dtim period.
|
||||
*/
|
||||
if (te_data->vif->type == NL80211_IFTYPE_STATION &&
|
||||
(!te_data->vif->bss_conf.assoc ||
|
||||
!te_data->vif->bss_conf.dtim_period)) {
|
||||
IWL_ERR(mvm,
|
||||
"No assocation and the time event is over already...\n");
|
||||
ieee80211_connection_loss(te_data->vif);
|
||||
}
|
||||
|
||||
iwl_mvm_te_check_disconnect(mvm, te_data->vif,
|
||||
"No assocation and the time event is over already...");
|
||||
iwl_mvm_te_clear_data(mvm, te_data);
|
||||
} else if (le32_to_cpu(notif->action) & TE_NOTIF_HOST_EVENT_START) {
|
||||
te_data->running = true;
|
||||
|
|
|
@ -888,14 +888,6 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
|
|||
|
||||
iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
|
||||
if (hw_rfkill) {
|
||||
/*
|
||||
* Clear the interrupt in APMG if the NIC is going down.
|
||||
* Note that when the NIC exits RFkill (else branch), we
|
||||
* can't access prph and the NIC will be reset in
|
||||
* start_hw anyway.
|
||||
*/
|
||||
iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
|
||||
APMG_RTC_INT_STT_RFKILL);
|
||||
set_bit(STATUS_RFKILL, &trans_pcie->status);
|
||||
if (test_and_clear_bit(STATUS_HCMD_ACTIVE,
|
||||
&trans_pcie->status))
|
||||
|
|
|
@ -1502,16 +1502,16 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
|
|||
spin_lock_init(&trans_pcie->reg_lock);
|
||||
init_waitqueue_head(&trans_pcie->ucode_write_waitq);
|
||||
|
||||
/* W/A - seems to solve weird behavior. We need to remove this if we
|
||||
* don't want to stay in L1 all the time. This wastes a lot of power */
|
||||
pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
|
||||
PCIE_LINK_STATE_CLKPM);
|
||||
|
||||
if (pci_enable_device(pdev)) {
|
||||
err = -ENODEV;
|
||||
goto out_no_pci;
|
||||
}
|
||||
|
||||
/* W/A - seems to solve weird behavior. We need to remove this if we
|
||||
* don't want to stay in L1 all the time. This wastes a lot of power */
|
||||
pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
|
||||
PCIE_LINK_STATE_CLKPM);
|
||||
|
||||
pci_set_master(pdev);
|
||||
|
||||
err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
|
||||
|
|
|
@ -98,10 +98,12 @@ static int zd1201_fw_upload(struct usb_device *dev, int apfw)
|
|||
goto exit;
|
||||
|
||||
err = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), 0x4,
|
||||
USB_DIR_IN | 0x40, 0,0, &ret, sizeof(ret), ZD1201_FW_TIMEOUT);
|
||||
USB_DIR_IN | 0x40, 0, 0, buf, sizeof(ret), ZD1201_FW_TIMEOUT);
|
||||
if (err < 0)
|
||||
goto exit;
|
||||
|
||||
memcpy(&ret, buf, sizeof(ret));
|
||||
|
||||
if (ret & 0x80) {
|
||||
err = -EIO;
|
||||
goto exit;
|
||||
|
|
|
@ -392,6 +392,8 @@ static void __unflatten_device_tree(struct boot_param_header *blob,
|
|||
mem = (unsigned long)
|
||||
dt_alloc(size + 4, __alignof__(struct device_node));
|
||||
|
||||
memset((void *)mem, 0, size);
|
||||
|
||||
((__be32 *)mem)[size / 4] = cpu_to_be32(0xdeadbeef);
|
||||
|
||||
pr_debug(" unflattening %lx...\n", mem);
|
||||
|
|
|
@ -278,6 +278,7 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
|
|||
{
|
||||
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct sunxi_pinctrl_group *g = &pctl->groups[group];
|
||||
unsigned long flags;
|
||||
u32 val, mask;
|
||||
u16 strength;
|
||||
u8 dlevel;
|
||||
|
@ -295,22 +296,35 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
|
|||
* 3: 40mA
|
||||
*/
|
||||
dlevel = strength / 10 - 1;
|
||||
|
||||
spin_lock_irqsave(&pctl->lock, flags);
|
||||
|
||||
val = readl(pctl->membase + sunxi_dlevel_reg(g->pin));
|
||||
mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin);
|
||||
writel((val & ~mask) | dlevel << sunxi_dlevel_offset(g->pin),
|
||||
pctl->membase + sunxi_dlevel_reg(g->pin));
|
||||
|
||||
spin_unlock_irqrestore(&pctl->lock, flags);
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
spin_lock_irqsave(&pctl->lock, flags);
|
||||
|
||||
val = readl(pctl->membase + sunxi_pull_reg(g->pin));
|
||||
mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
|
||||
writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin),
|
||||
pctl->membase + sunxi_pull_reg(g->pin));
|
||||
|
||||
spin_unlock_irqrestore(&pctl->lock, flags);
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
spin_lock_irqsave(&pctl->lock, flags);
|
||||
|
||||
val = readl(pctl->membase + sunxi_pull_reg(g->pin));
|
||||
mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
|
||||
writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin),
|
||||
pctl->membase + sunxi_pull_reg(g->pin));
|
||||
|
||||
spin_unlock_irqrestore(&pctl->lock, flags);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
|
@ -360,11 +374,17 @@ static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
|
|||
u8 config)
|
||||
{
|
||||
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
||||
unsigned long flags;
|
||||
u32 val, mask;
|
||||
|
||||
u32 val = readl(pctl->membase + sunxi_mux_reg(pin));
|
||||
u32 mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
|
||||
spin_lock_irqsave(&pctl->lock, flags);
|
||||
|
||||
val = readl(pctl->membase + sunxi_mux_reg(pin));
|
||||
mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
|
||||
writel((val & ~mask) | config << sunxi_mux_offset(pin),
|
||||
pctl->membase + sunxi_mux_reg(pin));
|
||||
|
||||
spin_unlock_irqrestore(&pctl->lock, flags);
|
||||
}
|
||||
|
||||
static int sunxi_pmx_enable(struct pinctrl_dev *pctldev,
|
||||
|
@ -464,8 +484,21 @@ static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
|
|||
struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
|
||||
u32 reg = sunxi_data_reg(offset);
|
||||
u8 index = sunxi_data_offset(offset);
|
||||
unsigned long flags;
|
||||
u32 regval;
|
||||
|
||||
writel((value & DATA_PINS_MASK) << index, pctl->membase + reg);
|
||||
spin_lock_irqsave(&pctl->lock, flags);
|
||||
|
||||
regval = readl(pctl->membase + reg);
|
||||
|
||||
if (value)
|
||||
regval |= BIT(index);
|
||||
else
|
||||
regval &= ~(BIT(index));
|
||||
|
||||
writel(regval, pctl->membase + reg);
|
||||
|
||||
spin_unlock_irqrestore(&pctl->lock, flags);
|
||||
}
|
||||
|
||||
static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
|
||||
|
@ -526,6 +559,8 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
|
|||
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
|
||||
u32 reg = sunxi_irq_cfg_reg(d->hwirq);
|
||||
u8 index = sunxi_irq_cfg_offset(d->hwirq);
|
||||
unsigned long flags;
|
||||
u32 regval;
|
||||
u8 mode;
|
||||
|
||||
switch (type) {
|
||||
|
@ -548,7 +583,13 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
writel((mode & IRQ_CFG_IRQ_MASK) << index, pctl->membase + reg);
|
||||
spin_lock_irqsave(&pctl->lock, flags);
|
||||
|
||||
regval = readl(pctl->membase + reg);
|
||||
regval &= ~IRQ_CFG_IRQ_MASK;
|
||||
writel(regval | (mode << index), pctl->membase + reg);
|
||||
|
||||
spin_unlock_irqrestore(&pctl->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -560,14 +601,19 @@ static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d)
|
|||
u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq);
|
||||
u32 status_reg = sunxi_irq_status_reg(d->hwirq);
|
||||
u8 status_idx = sunxi_irq_status_offset(d->hwirq);
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
||||
spin_lock_irqsave(&pctl->lock, flags);
|
||||
|
||||
/* Mask the IRQ */
|
||||
val = readl(pctl->membase + ctrl_reg);
|
||||
writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg);
|
||||
|
||||
/* Clear the IRQ */
|
||||
writel(1 << status_idx, pctl->membase + status_reg);
|
||||
|
||||
spin_unlock_irqrestore(&pctl->lock, flags);
|
||||
}
|
||||
|
||||
static void sunxi_pinctrl_irq_mask(struct irq_data *d)
|
||||
|
@ -575,11 +621,16 @@ static void sunxi_pinctrl_irq_mask(struct irq_data *d)
|
|||
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
|
||||
u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
|
||||
u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
||||
spin_lock_irqsave(&pctl->lock, flags);
|
||||
|
||||
/* Mask the IRQ */
|
||||
val = readl(pctl->membase + reg);
|
||||
writel(val & ~(1 << idx), pctl->membase + reg);
|
||||
|
||||
spin_unlock_irqrestore(&pctl->lock, flags);
|
||||
}
|
||||
|
||||
static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
|
||||
|
@ -588,6 +639,7 @@ static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
|
|||
struct sunxi_desc_function *func;
|
||||
u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
|
||||
u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
||||
func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
|
||||
|
@ -597,9 +649,13 @@ static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
|
|||
/* Change muxing to INT mode */
|
||||
sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
|
||||
|
||||
spin_lock_irqsave(&pctl->lock, flags);
|
||||
|
||||
/* Unmask the IRQ */
|
||||
val = readl(pctl->membase + reg);
|
||||
writel(val | (1 << idx), pctl->membase + reg);
|
||||
|
||||
spin_unlock_irqrestore(&pctl->lock, flags);
|
||||
}
|
||||
|
||||
static struct irq_chip sunxi_pinctrl_irq_chip = {
|
||||
|
@ -752,6 +808,8 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
|
|||
return -ENOMEM;
|
||||
platform_set_drvdata(pdev, pctl);
|
||||
|
||||
spin_lock_init(&pctl->lock);
|
||||
|
||||
pctl->membase = of_iomap(node, 0);
|
||||
if (!pctl->membase)
|
||||
return -ENOMEM;
|
||||
|
|
|
@ -14,6 +14,7 @@
|
|||
#define __PINCTRL_SUNXI_H
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#define PA_BASE 0
|
||||
#define PB_BASE 32
|
||||
|
@ -407,6 +408,7 @@ struct sunxi_pinctrl {
|
|||
unsigned ngroups;
|
||||
int irq;
|
||||
int irq_array[SUNXI_IRQ_NUMBER];
|
||||
spinlock_t lock;
|
||||
struct pinctrl_dev *pctl_dev;
|
||||
};
|
||||
|
||||
|
|
|
@ -330,7 +330,7 @@ static int __init olpc_ec_init_module(void)
|
|||
return platform_driver_register(&olpc_ec_plat_driver);
|
||||
}
|
||||
|
||||
module_init(olpc_ec_init_module);
|
||||
arch_initcall(olpc_ec_init_module);
|
||||
|
||||
MODULE_AUTHOR("Andres Salomon <dilinger@queued.net>");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
|
@ -53,7 +53,6 @@ MODULE_ALIAS("wmi:5FB7F034-2C63-45e9-BE91-3D44E2C707E4");
|
|||
#define HPWMI_ALS_QUERY 0x3
|
||||
#define HPWMI_HARDWARE_QUERY 0x4
|
||||
#define HPWMI_WIRELESS_QUERY 0x5
|
||||
#define HPWMI_BIOS_QUERY 0x9
|
||||
#define HPWMI_HOTKEY_QUERY 0xc
|
||||
#define HPWMI_WIRELESS2_QUERY 0x1b
|
||||
#define HPWMI_POSTCODEERROR_QUERY 0x2a
|
||||
|
@ -293,19 +292,6 @@ static int hp_wmi_tablet_state(void)
|
|||
return (state & 0x4) ? 1 : 0;
|
||||
}
|
||||
|
||||
static int hp_wmi_enable_hotkeys(void)
|
||||
{
|
||||
int ret;
|
||||
int query = 0x6e;
|
||||
|
||||
ret = hp_wmi_perform_query(HPWMI_BIOS_QUERY, 1, &query, sizeof(query),
|
||||
0);
|
||||
|
||||
if (ret)
|
||||
return -EINVAL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hp_wmi_set_block(void *data, bool blocked)
|
||||
{
|
||||
enum hp_wmi_radio r = (enum hp_wmi_radio) data;
|
||||
|
@ -1009,8 +995,6 @@ static int __init hp_wmi_init(void)
|
|||
err = hp_wmi_input_setup();
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
hp_wmi_enable_hotkeys();
|
||||
}
|
||||
|
||||
if (bios_capable) {
|
||||
|
|
|
@ -2440,7 +2440,10 @@ static ssize_t sony_nc_gfx_switch_status_show(struct device *dev,
|
|||
if (pos < 0)
|
||||
return pos;
|
||||
|
||||
return snprintf(buffer, PAGE_SIZE, "%s\n", pos ? "speed" : "stamina");
|
||||
return snprintf(buffer, PAGE_SIZE, "%s\n",
|
||||
pos == SPEED ? "speed" :
|
||||
pos == STAMINA ? "stamina" :
|
||||
pos == AUTO ? "auto" : "unknown");
|
||||
}
|
||||
|
||||
static int sony_nc_gfx_switch_setup(struct platform_device *pd,
|
||||
|
@ -4320,7 +4323,8 @@ static int sony_pic_add(struct acpi_device *device)
|
|||
goto err_free_resources;
|
||||
}
|
||||
|
||||
if (sonypi_compat_init())
|
||||
result = sonypi_compat_init();
|
||||
if (result)
|
||||
goto err_remove_input;
|
||||
|
||||
/* request io port */
|
||||
|
|
|
@ -102,10 +102,13 @@ static void zfcp_erp_action_dismiss_port(struct zfcp_port *port)
|
|||
|
||||
if (atomic_read(&port->status) & ZFCP_STATUS_COMMON_ERP_INUSE)
|
||||
zfcp_erp_action_dismiss(&port->erp_action);
|
||||
else
|
||||
shost_for_each_device(sdev, port->adapter->scsi_host)
|
||||
else {
|
||||
spin_lock(port->adapter->scsi_host->host_lock);
|
||||
__shost_for_each_device(sdev, port->adapter->scsi_host)
|
||||
if (sdev_to_zfcp(sdev)->port == port)
|
||||
zfcp_erp_action_dismiss_lun(sdev);
|
||||
spin_unlock(port->adapter->scsi_host->host_lock);
|
||||
}
|
||||
}
|
||||
|
||||
static void zfcp_erp_action_dismiss_adapter(struct zfcp_adapter *adapter)
|
||||
|
@ -592,9 +595,11 @@ static void _zfcp_erp_lun_reopen_all(struct zfcp_port *port, int clear,
|
|||
{
|
||||
struct scsi_device *sdev;
|
||||
|
||||
shost_for_each_device(sdev, port->adapter->scsi_host)
|
||||
spin_lock(port->adapter->scsi_host->host_lock);
|
||||
__shost_for_each_device(sdev, port->adapter->scsi_host)
|
||||
if (sdev_to_zfcp(sdev)->port == port)
|
||||
_zfcp_erp_lun_reopen(sdev, clear, id, 0);
|
||||
spin_unlock(port->adapter->scsi_host->host_lock);
|
||||
}
|
||||
|
||||
static void zfcp_erp_strategy_followup_failed(struct zfcp_erp_action *act)
|
||||
|
@ -1434,8 +1439,10 @@ void zfcp_erp_set_adapter_status(struct zfcp_adapter *adapter, u32 mask)
|
|||
atomic_set_mask(common_mask, &port->status);
|
||||
read_unlock_irqrestore(&adapter->port_list_lock, flags);
|
||||
|
||||
shost_for_each_device(sdev, adapter->scsi_host)
|
||||
spin_lock_irqsave(adapter->scsi_host->host_lock, flags);
|
||||
__shost_for_each_device(sdev, adapter->scsi_host)
|
||||
atomic_set_mask(common_mask, &sdev_to_zfcp(sdev)->status);
|
||||
spin_unlock_irqrestore(adapter->scsi_host->host_lock, flags);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -1469,11 +1476,13 @@ void zfcp_erp_clear_adapter_status(struct zfcp_adapter *adapter, u32 mask)
|
|||
}
|
||||
read_unlock_irqrestore(&adapter->port_list_lock, flags);
|
||||
|
||||
shost_for_each_device(sdev, adapter->scsi_host) {
|
||||
spin_lock_irqsave(adapter->scsi_host->host_lock, flags);
|
||||
__shost_for_each_device(sdev, adapter->scsi_host) {
|
||||
atomic_clear_mask(common_mask, &sdev_to_zfcp(sdev)->status);
|
||||
if (clear_counter)
|
||||
atomic_set(&sdev_to_zfcp(sdev)->erp_counter, 0);
|
||||
}
|
||||
spin_unlock_irqrestore(adapter->scsi_host->host_lock, flags);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -1487,16 +1496,19 @@ void zfcp_erp_set_port_status(struct zfcp_port *port, u32 mask)
|
|||
{
|
||||
struct scsi_device *sdev;
|
||||
u32 common_mask = mask & ZFCP_COMMON_FLAGS;
|
||||
unsigned long flags;
|
||||
|
||||
atomic_set_mask(mask, &port->status);
|
||||
|
||||
if (!common_mask)
|
||||
return;
|
||||
|
||||
shost_for_each_device(sdev, port->adapter->scsi_host)
|
||||
spin_lock_irqsave(port->adapter->scsi_host->host_lock, flags);
|
||||
__shost_for_each_device(sdev, port->adapter->scsi_host)
|
||||
if (sdev_to_zfcp(sdev)->port == port)
|
||||
atomic_set_mask(common_mask,
|
||||
&sdev_to_zfcp(sdev)->status);
|
||||
spin_unlock_irqrestore(port->adapter->scsi_host->host_lock, flags);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -1511,6 +1523,7 @@ void zfcp_erp_clear_port_status(struct zfcp_port *port, u32 mask)
|
|||
struct scsi_device *sdev;
|
||||
u32 common_mask = mask & ZFCP_COMMON_FLAGS;
|
||||
u32 clear_counter = mask & ZFCP_STATUS_COMMON_ERP_FAILED;
|
||||
unsigned long flags;
|
||||
|
||||
atomic_clear_mask(mask, &port->status);
|
||||
|
||||
|
@ -1520,13 +1533,15 @@ void zfcp_erp_clear_port_status(struct zfcp_port *port, u32 mask)
|
|||
if (clear_counter)
|
||||
atomic_set(&port->erp_counter, 0);
|
||||
|
||||
shost_for_each_device(sdev, port->adapter->scsi_host)
|
||||
spin_lock_irqsave(port->adapter->scsi_host->host_lock, flags);
|
||||
__shost_for_each_device(sdev, port->adapter->scsi_host)
|
||||
if (sdev_to_zfcp(sdev)->port == port) {
|
||||
atomic_clear_mask(common_mask,
|
||||
&sdev_to_zfcp(sdev)->status);
|
||||
if (clear_counter)
|
||||
atomic_set(&sdev_to_zfcp(sdev)->erp_counter, 0);
|
||||
}
|
||||
spin_unlock_irqrestore(port->adapter->scsi_host->host_lock, flags);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
@ -224,11 +224,9 @@ int zfcp_qdio_sbals_from_sg(struct zfcp_qdio *qdio, struct zfcp_qdio_req *q_req,
|
|||
|
||||
static int zfcp_qdio_sbal_check(struct zfcp_qdio *qdio)
|
||||
{
|
||||
spin_lock_irq(&qdio->req_q_lock);
|
||||
if (atomic_read(&qdio->req_q_free) ||
|
||||
!(atomic_read(&qdio->adapter->status) & ZFCP_STATUS_ADAPTER_QDIOUP))
|
||||
return 1;
|
||||
spin_unlock_irq(&qdio->req_q_lock);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -246,9 +244,8 @@ int zfcp_qdio_sbal_get(struct zfcp_qdio *qdio)
|
|||
{
|
||||
long ret;
|
||||
|
||||
spin_unlock_irq(&qdio->req_q_lock);
|
||||
ret = wait_event_interruptible_timeout(qdio->req_q_wq,
|
||||
zfcp_qdio_sbal_check(qdio), 5 * HZ);
|
||||
ret = wait_event_interruptible_lock_irq_timeout(qdio->req_q_wq,
|
||||
zfcp_qdio_sbal_check(qdio), qdio->req_q_lock, 5 * HZ);
|
||||
|
||||
if (!(atomic_read(&qdio->adapter->status) & ZFCP_STATUS_ADAPTER_QDIOUP))
|
||||
return -EIO;
|
||||
|
@ -262,7 +259,6 @@ int zfcp_qdio_sbal_get(struct zfcp_qdio *qdio)
|
|||
zfcp_erp_adapter_reopen(qdio->adapter, 0, "qdsbg_1");
|
||||
}
|
||||
|
||||
spin_lock_irq(&qdio->req_q_lock);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
|
|
|
@ -27,6 +27,16 @@ static ssize_t zfcp_sysfs_##_feat##_##_name##_show(struct device *dev, \
|
|||
static ZFCP_DEV_ATTR(_feat, _name, S_IRUGO, \
|
||||
zfcp_sysfs_##_feat##_##_name##_show, NULL);
|
||||
|
||||
#define ZFCP_DEFINE_ATTR_CONST(_feat, _name, _format, _value) \
|
||||
static ssize_t zfcp_sysfs_##_feat##_##_name##_show(struct device *dev, \
|
||||
struct device_attribute *at,\
|
||||
char *buf) \
|
||||
{ \
|
||||
return sprintf(buf, _format, _value); \
|
||||
} \
|
||||
static ZFCP_DEV_ATTR(_feat, _name, S_IRUGO, \
|
||||
zfcp_sysfs_##_feat##_##_name##_show, NULL);
|
||||
|
||||
#define ZFCP_DEFINE_A_ATTR(_name, _format, _value) \
|
||||
static ssize_t zfcp_sysfs_adapter_##_name##_show(struct device *dev, \
|
||||
struct device_attribute *at,\
|
||||
|
@ -75,6 +85,8 @@ ZFCP_DEFINE_ATTR(zfcp_unit, unit, in_recovery, "%d\n",
|
|||
ZFCP_DEFINE_ATTR(zfcp_unit, unit, access_denied, "%d\n",
|
||||
(zfcp_unit_sdev_status(unit) &
|
||||
ZFCP_STATUS_COMMON_ACCESS_DENIED) != 0);
|
||||
ZFCP_DEFINE_ATTR_CONST(unit, access_shared, "%d\n", 0);
|
||||
ZFCP_DEFINE_ATTR_CONST(unit, access_readonly, "%d\n", 0);
|
||||
|
||||
static ssize_t zfcp_sysfs_port_failed_show(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
|
@ -347,6 +359,8 @@ static struct attribute *zfcp_unit_attrs[] = {
|
|||
&dev_attr_unit_in_recovery.attr,
|
||||
&dev_attr_unit_status.attr,
|
||||
&dev_attr_unit_access_denied.attr,
|
||||
&dev_attr_unit_access_shared.attr,
|
||||
&dev_attr_unit_access_readonly.attr,
|
||||
NULL
|
||||
};
|
||||
static struct attribute_group zfcp_unit_attr_group = {
|
||||
|
|
|
@ -1353,7 +1353,6 @@ config SCSI_LPFC
|
|||
tristate "Emulex LightPulse Fibre Channel Support"
|
||||
depends on PCI && SCSI
|
||||
select SCSI_FC_ATTRS
|
||||
select GENERIC_CSUM
|
||||
select CRC_T10DIF
|
||||
help
|
||||
This lpfc driver supports the Emulex LightPulse
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue