KVM: arm/arm64: vgic-v2: Save maintenance interrupt state only if required
Next on our list of useless accesses is the maintenance interrupt status registers (GICH_MISR, GICH_EISR{0,1}). It is pointless to save them if we haven't asked for a maintenance interrupt the first place, which can only happen for two reasons: - Underflow: GICH_HCR_UIE will be set, - EOI: GICH_LR_EOI will be set. These conditions can be checked on the in-memory copies of the regs. Should any of these two condition be valid, we must read GICH_MISR. We can then check for GICH_MISR_EOI, and only when set read GICH_EISR*. This means that in most case, we don't have to save them at all. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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@ -21,6 +21,49 @@
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#include <asm/kvm_hyp.h>
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static void __hyp_text save_maint_int_state(struct kvm_vcpu *vcpu,
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void __iomem *base)
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{
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struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
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int nr_lr = vcpu->arch.vgic_cpu.nr_lr;
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u32 eisr0, eisr1;
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int i;
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bool expect_mi;
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expect_mi = !!(cpu_if->vgic_hcr & GICH_HCR_UIE);
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for (i = 0; i < nr_lr; i++) {
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if (!(vcpu->arch.vgic_cpu.live_lrs & (1UL << i)))
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continue;
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expect_mi |= (!(cpu_if->vgic_lr[i] & GICH_LR_HW) &&
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(cpu_if->vgic_lr[i] & GICH_LR_EOI));
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}
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if (expect_mi) {
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cpu_if->vgic_misr = readl_relaxed(base + GICH_MISR);
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if (cpu_if->vgic_misr & GICH_MISR_EOI) {
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eisr0 = readl_relaxed(base + GICH_EISR0);
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if (unlikely(nr_lr > 32))
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eisr1 = readl_relaxed(base + GICH_EISR1);
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else
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eisr1 = 0;
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} else {
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eisr0 = eisr1 = 0;
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}
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} else {
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cpu_if->vgic_misr = 0;
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eisr0 = eisr1 = 0;
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}
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#ifdef CONFIG_CPU_BIG_ENDIAN
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cpu_if->vgic_eisr = ((u64)eisr0 << 32) | eisr1;
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#else
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cpu_if->vgic_eisr = ((u64)eisr1 << 32) | eisr0;
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#endif
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}
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/* vcpu is already in the HYP VA space */
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void __hyp_text __vgic_v2_save_state(struct kvm_vcpu *vcpu)
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{
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@ -28,7 +71,7 @@ void __hyp_text __vgic_v2_save_state(struct kvm_vcpu *vcpu)
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struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
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struct vgic_dist *vgic = &kvm->arch.vgic;
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void __iomem *base = kern_hyp_va(vgic->vctrl_base);
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u32 eisr0, eisr1, elrsr0, elrsr1;
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u32 elrsr0, elrsr1;
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int i, nr_lr;
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if (!base)
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@ -38,26 +81,23 @@ void __hyp_text __vgic_v2_save_state(struct kvm_vcpu *vcpu)
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cpu_if->vgic_vmcr = readl_relaxed(base + GICH_VMCR);
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if (vcpu->arch.vgic_cpu.live_lrs) {
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eisr0 = readl_relaxed(base + GICH_EISR0);
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elrsr0 = readl_relaxed(base + GICH_ELRSR0);
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cpu_if->vgic_misr = readl_relaxed(base + GICH_MISR);
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cpu_if->vgic_apr = readl_relaxed(base + GICH_APR);
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if (unlikely(nr_lr > 32)) {
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eisr1 = readl_relaxed(base + GICH_EISR1);
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elrsr1 = readl_relaxed(base + GICH_ELRSR1);
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} else {
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eisr1 = elrsr1 = 0;
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elrsr1 = 0;
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}
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#ifdef CONFIG_CPU_BIG_ENDIAN
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cpu_if->vgic_eisr = ((u64)eisr0 << 32) | eisr1;
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cpu_if->vgic_elrsr = ((u64)elrsr0 << 32) | elrsr1;
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#else
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cpu_if->vgic_eisr = ((u64)eisr1 << 32) | eisr0;
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cpu_if->vgic_elrsr = ((u64)elrsr1 << 32) | elrsr0;
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#endif
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save_maint_int_state(vcpu, base);
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for (i = 0; i < nr_lr; i++)
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if (vcpu->arch.vgic_cpu.live_lrs & (1UL << i))
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cpu_if->vgic_lr[i] = readl_relaxed(base + GICH_LR0 + (i * 4));
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