Merge branch 'sh-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* 'sh-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: sh: intc: Initialize radix tree gfp mask explicitly. sh: Fix up SH7201 clkfwk build. sh: mach-se: Fix up SE7206 build. sh: Fix up SH4-202 clkfwk build.
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@ -140,7 +140,7 @@ void __init init_se7206_IRQ(void)
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make_se7206_irq(IRQ1_IRQ); /* ATA */
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make_se7206_irq(IRQ3_IRQ); /* SLOT / PCM */
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__raw_writew(__raw_readw(INTC_ICR1) | 0x000b, INTC_ICR); /* ICR1 */
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__raw_writew(__raw_readw(INTC_ICR1) | 0x000b, INTC_ICR1); /* ICR1 */
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/* FPGA System register setup*/
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__raw_writew(0x0000,INTSTS0); /* Clear INTSTS0 */
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@ -34,7 +34,7 @@ static const int pfc_divisors[]={1,2,3,4,6,8,12};
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static void master_clk_init(struct clk *clk)
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{
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return 10000000 * PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
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clk->rate = 10000000 * PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
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}
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static struct clk_ops sh7201_master_clk_ops = {
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@ -81,8 +81,7 @@ static void shoc_clk_init(struct clk *clk)
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for (i = 0; i < ARRAY_SIZE(frqcr3_divisors); i++) {
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int divisor = frqcr3_divisors[i];
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if (clk->ops->set_rate(clk, clk->parent->rate /
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divisor, 0) == 0)
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if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0)
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break;
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}
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@ -198,6 +198,7 @@ int __init register_intc_controller(struct intc_desc *desc)
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list_add_tail(&d->list, &intc_list);
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raw_spin_lock_init(&d->lock);
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INIT_RADIX_TREE(&d->tree, GFP_ATOMIC);
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d->index = nr_intc_controllers;
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