drm/radeon/kms: Use surfaces for scanout / cursor byte swapping on big endian.
Signed-off-by: Michel Dänzer <daenzer@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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733289c265
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c88f9f0c91
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@ -2235,6 +2235,11 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg,
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flags |= R300_SURF_TILE_MICRO;
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}
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if (tiling_flags & RADEON_TILING_SWAP_16BIT)
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flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
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if (tiling_flags & RADEON_TILING_SWAP_32BIT)
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flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
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DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
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WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
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WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
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@ -45,71 +45,9 @@ struct radeon_fb_device {
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struct radeon_device *rdev;
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};
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static int radeon_fb_check_var(struct fb_var_screeninfo *var,
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struct fb_info *info)
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{
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int ret;
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ret = drm_fb_helper_check_var(var, info);
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if (ret)
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return ret;
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/* big endian override for radeon endian workaround */
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#ifdef __BIG_ENDIAN
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{
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int depth;
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switch (var->bits_per_pixel) {
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case 16:
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depth = (var->green.length == 6) ? 16 : 15;
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break;
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case 32:
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depth = (var->transp.length > 0) ? 32 : 24;
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break;
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default:
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depth = var->bits_per_pixel;
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break;
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}
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switch (depth) {
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case 8:
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var->red.offset = 0;
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var->green.offset = 0;
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var->blue.offset = 0;
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var->red.length = 8;
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var->green.length = 8;
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var->blue.length = 8;
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var->transp.length = 0;
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var->transp.offset = 0;
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break;
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case 24:
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var->red.offset = 8;
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var->green.offset = 16;
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var->blue.offset = 24;
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var->red.length = 8;
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var->green.length = 8;
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var->blue.length = 8;
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var->transp.length = 0;
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var->transp.offset = 0;
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break;
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case 32:
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var->red.offset = 8;
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var->green.offset = 16;
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var->blue.offset = 24;
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var->red.length = 8;
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var->green.length = 8;
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var->blue.length = 8;
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var->transp.length = 8;
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var->transp.offset = 0;
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break;
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default:
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return -EINVAL;
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}
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}
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#endif
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return 0;
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}
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static struct fb_ops radeonfb_ops = {
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.owner = THIS_MODULE,
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.fb_check_var = radeon_fb_check_var,
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.fb_check_var = drm_fb_helper_check_var,
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.fb_set_par = drm_fb_helper_set_par,
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.fb_setcolreg = drm_fb_helper_setcolreg,
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.fb_fillrect = cfb_fillrect,
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@ -206,6 +144,7 @@ int radeonfb_create(struct drm_device *dev,
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void *fbptr = NULL;
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unsigned long tmp;
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bool fb_tiled = false; /* useful for testing */
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u32 tiling_flags = 0;
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mode_cmd.width = surface_width;
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mode_cmd.height = surface_height;
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@ -230,7 +169,22 @@ int radeonfb_create(struct drm_device *dev,
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robj = gobj->driver_private;
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if (fb_tiled)
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radeon_object_set_tiling_flags(robj, RADEON_TILING_MACRO|RADEON_TILING_SURFACE, mode_cmd.pitch);
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tiling_flags = RADEON_TILING_MACRO;
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#ifdef __BIG_ENDIAN
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switch (mode_cmd.bpp) {
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case 32:
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tiling_flags |= RADEON_TILING_SWAP_32BIT;
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break;
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case 16:
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tiling_flags |= RADEON_TILING_SWAP_16BIT;
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default:
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break;
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}
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#endif
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if (tiling_flags)
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radeon_object_set_tiling_flags(robj, tiling_flags | RADEON_TILING_SURFACE, mode_cmd.pitch);
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mutex_lock(&rdev->ddev->struct_mutex);
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fb = radeon_framebuffer_create(rdev->ddev, &mode_cmd, gobj);
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if (fb == NULL) {
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@ -313,45 +267,6 @@ int radeonfb_create(struct drm_device *dev,
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DRM_INFO("fb depth is %d\n", fb->depth);
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DRM_INFO(" pitch is %d\n", fb->pitch);
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#ifdef __BIG_ENDIAN
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/* fill var sets defaults for this stuff - override
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on big endian */
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switch (fb->depth) {
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case 8:
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info->var.red.offset = 0;
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info->var.green.offset = 0;
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info->var.blue.offset = 0;
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info->var.red.length = 8; /* 8bit DAC */
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info->var.green.length = 8;
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info->var.blue.length = 8;
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info->var.transp.offset = 0;
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info->var.transp.length = 0;
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break;
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case 24:
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info->var.red.offset = 8;
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info->var.green.offset = 16;
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info->var.blue.offset = 24;
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info->var.red.length = 8;
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info->var.green.length = 8;
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info->var.blue.length = 8;
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info->var.transp.offset = 0;
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info->var.transp.length = 0;
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break;
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case 32:
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info->var.red.offset = 8;
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info->var.green.offset = 16;
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info->var.blue.offset = 24;
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info->var.red.length = 8;
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info->var.green.length = 8;
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info->var.blue.length = 8;
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info->var.transp.offset = 0;
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info->var.transp.length = 8;
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break;
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default:
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break;
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}
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#endif
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fb->fbdev = info;
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rfbdev->rfb = rfb;
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rfbdev->rdev = rdev;
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@ -188,6 +188,7 @@ int radeon_object_kmap(struct radeon_object *robj, void **ptr)
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if (ptr) {
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*ptr = robj->kptr;
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}
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radeon_object_check_tiling(robj, 0, 0);
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return 0;
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}
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@ -200,6 +201,7 @@ void radeon_object_kunmap(struct radeon_object *robj)
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}
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robj->kptr = NULL;
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spin_unlock(&robj->tobj.lock);
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radeon_object_check_tiling(robj, 0, 0);
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ttm_bo_kunmap(&robj->kmap);
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}
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@ -802,11 +802,12 @@ struct drm_radeon_gem_create {
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uint32_t flags;
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};
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#define RADEON_TILING_MACRO 0x1
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#define RADEON_TILING_MICRO 0x2
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#define RADEON_TILING_SWAP 0x4
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#define RADEON_TILING_SURFACE 0x8 /* this object requires a surface
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* when mapped - i.e. front buffer */
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#define RADEON_TILING_MACRO 0x1
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#define RADEON_TILING_MICRO 0x2
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#define RADEON_TILING_SWAP_16BIT 0x4
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#define RADEON_TILING_SWAP_32BIT 0x8
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#define RADEON_TILING_SURFACE 0x10 /* this object requires a surface
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* when mapped - i.e. front buffer */
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struct drm_radeon_gem_set_tiling {
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uint32_t handle;
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