MIPS: Emulate the BC1{EQ,NE}Z FPU instructions
MIPS R6 introduced the following two branch instructions for COP1: BC1EQZ: Branch if Cop1 (FPR) Register Bit 0 is Equal to Zero BC1NEZ: Branch if Cop1 (FPR) Register Bit 0 is Not Equal to Zero Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
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@ -115,7 +115,8 @@ enum cop_op {
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mfhc_op = 0x03, mtc_op = 0x04,
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dmtc_op = 0x05, ctc_op = 0x06,
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mthc0_op = 0x06, mthc_op = 0x07,
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bc_op = 0x08, cop_op = 0x10,
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bc_op = 0x08, bc1eqz_op = 0x09,
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bc1nez_op = 0x0d, cop_op = 0x10,
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copm_op = 0x18
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};
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@ -403,7 +403,7 @@ int __MIPS16e_compute_return_epc(struct pt_regs *regs)
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int __compute_return_epc_for_insn(struct pt_regs *regs,
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union mips_instruction insn)
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{
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unsigned int bit, fcr31, dspcontrol;
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unsigned int bit, fcr31, dspcontrol, reg;
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long epc = regs->cp0_epc;
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int ret = 0;
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@ -618,40 +618,83 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
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* And now the FPA/cp1 branch instructions.
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*/
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case cop1_op:
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preempt_disable();
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if (is_fpu_owner())
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fcr31 = read_32bit_cp1_register(CP1_STATUS);
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else
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fcr31 = current->thread.fpu.fcr31;
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preempt_enable();
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bit = (insn.i_format.rt >> 2);
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bit += (bit != 0);
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bit += 23;
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switch (insn.i_format.rt & 3) {
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case 0: /* bc1f */
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case 2: /* bc1fl */
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if (~fcr31 & (1 << bit)) {
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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if (insn.i_format.rt == 2)
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ret = BRANCH_LIKELY_TAKEN;
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} else
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if (cpu_has_mips_r6 &&
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((insn.i_format.rs == bc1eqz_op) ||
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(insn.i_format.rs == bc1nez_op))) {
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if (!used_math()) { /* First time FPU user */
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ret = init_fpu();
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if (ret && NO_R6EMU) {
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ret = -ret;
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break;
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}
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ret = 0;
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set_used_math();
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}
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lose_fpu(1); /* Save FPU state for the emulator. */
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reg = insn.i_format.rt;
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bit = 0;
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switch (insn.i_format.rs) {
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case bc1eqz_op:
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/* Test bit 0 */
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if (get_fpr32(¤t->thread.fpu.fpr[reg], 0)
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& 0x1)
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bit = 1;
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break;
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case bc1nez_op:
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/* Test bit 0 */
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if (!(get_fpr32(¤t->thread.fpu.fpr[reg], 0)
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& 0x1))
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bit = 1;
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break;
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}
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own_fpu(1);
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if (bit)
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epc = epc + 4 +
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(insn.i_format.simmediate << 2);
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else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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} else {
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case 1: /* bc1t */
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case 3: /* bc1tl */
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if (fcr31 & (1 << bit)) {
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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if (insn.i_format.rt == 3)
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ret = BRANCH_LIKELY_TAKEN;
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} else
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epc += 8;
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regs->cp0_epc = epc;
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preempt_disable();
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if (is_fpu_owner())
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fcr31 = read_32bit_cp1_register(CP1_STATUS);
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else
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fcr31 = current->thread.fpu.fcr31;
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preempt_enable();
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bit = (insn.i_format.rt >> 2);
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bit += (bit != 0);
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bit += 23;
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switch (insn.i_format.rt & 3) {
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case 0: /* bc1f */
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case 2: /* bc1fl */
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if (~fcr31 & (1 << bit)) {
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epc = epc + 4 +
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(insn.i_format.simmediate << 2);
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if (insn.i_format.rt == 2)
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ret = BRANCH_LIKELY_TAKEN;
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} else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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case 1: /* bc1t */
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case 3: /* bc1tl */
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if (fcr31 & (1 << bit)) {
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epc = epc + 4 +
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(insn.i_format.simmediate << 2);
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if (insn.i_format.rt == 3)
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ret = BRANCH_LIKELY_TAKEN;
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} else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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}
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break;
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}
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break;
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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case lwc2_op: /* This is bbit0 on Octeon */
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if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
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@ -602,6 +602,33 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
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#endif
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case cop0_op:
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case cop1_op:
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/* Need to check for R6 bc1nez and bc1eqz branches */
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if (cpu_has_mips_r6 &&
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((insn.i_format.rs == bc1eqz_op) ||
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(insn.i_format.rs == bc1nez_op))) {
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bit = 0;
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switch (insn.i_format.rs) {
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case bc1eqz_op:
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if (get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)
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bit = 1;
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break;
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case bc1nez_op:
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if (!(get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1))
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bit = 1;
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break;
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}
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if (bit)
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*contpc = regs->cp0_epc +
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dec_insn.pc_inc +
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(insn.i_format.simmediate << 2);
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else
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*contpc = regs->cp0_epc +
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dec_insn.pc_inc +
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dec_insn.next_pc_inc;
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return 1;
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}
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/* R2/R6 compatible cop1 instruction. Fall through */
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case cop2_op:
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case cop1x_op:
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if (insn.i_format.rs == bc_op) {
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