clocksource: armada-370-xp: Use atomic access for shared registers
Replace the driver-specific thread-safe shared register API by the recently introduced atomic_io_clear_set(). Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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@ -85,12 +85,6 @@ static u32 ticks_per_jiffy;
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static struct clock_event_device __percpu *armada_370_xp_evt;
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static void timer_ctrl_clrset(u32 clr, u32 set)
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{
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writel((readl(timer_base + TIMER_CTRL_OFF) & ~clr) | set,
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timer_base + TIMER_CTRL_OFF);
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}
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static void local_timer_ctrl_clrset(u32 clr, u32 set)
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{
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writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set,
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@ -245,7 +239,7 @@ static void __init armada_370_xp_timer_common_init(struct device_node *np)
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clr = TIMER0_25MHZ;
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enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
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}
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timer_ctrl_clrset(clr, set);
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atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set);
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local_timer_ctrl_clrset(clr, set);
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/*
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@ -263,7 +257,9 @@ static void __init armada_370_xp_timer_common_init(struct device_node *np)
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writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
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writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
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timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
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atomic_io_modify(timer_base + TIMER_CTRL_OFF,
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TIMER0_RELOAD_EN | enable_mask,
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TIMER0_RELOAD_EN | enable_mask);
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/*
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* Set scale and timer for sched_clock.
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