powerpc/mm: Free up _PAGE_COHERENCE for numa fault use later
Set memory coherence always on hash64 config. If a platform cannot have memory coherence always set they can infer that from _PAGE_NO_CACHE and _PAGE_WRITETHRU like in lpar. So we dont' really need a separate bit for tracking _PAGE_COHERENCE. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Acked-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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@ -19,7 +19,7 @@
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#define _PAGE_FILE 0x0002 /* (!present only) software: pte holds file offset */
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#define _PAGE_EXEC 0x0004 /* No execute on POWER4 and newer (we invert) */
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#define _PAGE_GUARDED 0x0008
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#define _PAGE_COHERENT 0x0010 /* M: enforce memory coherence (SMP systems) */
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/* We can derive Memory coherence from _PAGE_NO_CACHE */
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#define _PAGE_NO_CACHE 0x0020 /* I: cache inhibit */
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#define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */
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#define _PAGE_DIRTY 0x0080 /* C: page changed */
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@ -148,7 +148,10 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
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and r0,r0,r4 /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
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andc r0,r30,r0 /* r0 = pte & ~r0 */
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rlwimi r3,r0,32-1,31,31 /* Insert result into PP lsb */
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ori r3,r3,HPTE_R_C /* Always add "C" bit for perf. */
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/*
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* Always add "C" bit for perf. Memory coherence is always enabled
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*/
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ori r3,r3,HPTE_R_C | HPTE_R_M
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/* We eventually do the icache sync here (maybe inline that
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* code rather than call a C function...)
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@ -457,7 +460,10 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
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and r0,r0,r4 /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
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andc r0,r3,r0 /* r0 = pte & ~r0 */
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rlwimi r3,r0,32-1,31,31 /* Insert result into PP lsb */
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ori r3,r3,HPTE_R_C /* Always add "C" bit for perf. */
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/*
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* Always add "C" bit for perf. Memory coherence is always enabled
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*/
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ori r3,r3,HPTE_R_C | HPTE_R_M
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/* We eventually do the icache sync here (maybe inline that
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* code rather than call a C function...)
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@ -795,7 +801,10 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
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and r0,r0,r4 /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
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andc r0,r30,r0 /* r0 = pte & ~r0 */
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rlwimi r3,r0,32-1,31,31 /* Insert result into PP lsb */
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ori r3,r3,HPTE_R_C /* Always add "C" bit for perf. */
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/*
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* Always add "C" bit for perf. Memory coherence is always enabled
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*/
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ori r3,r3,HPTE_R_C | HPTE_R_M
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/* We eventually do the icache sync here (maybe inline that
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* code rather than call a C function...)
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@ -169,9 +169,10 @@ static unsigned long htab_convert_pte_flags(unsigned long pteflags)
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if ((pteflags & _PAGE_USER) && !((pteflags & _PAGE_RW) &&
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(pteflags & _PAGE_DIRTY)))
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rflags |= 1;
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/* Always add C */
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return rflags | HPTE_R_C;
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/*
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* Always add "C" bit for perf. Memory coherence is always enabled
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*/
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return rflags | HPTE_R_C | HPTE_R_M;
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}
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int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
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@ -127,7 +127,11 @@ repeat:
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/* Add in WIMG bits */
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rflags |= (new_pmd & (_PAGE_WRITETHRU | _PAGE_NO_CACHE |
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_PAGE_COHERENT | _PAGE_GUARDED));
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_PAGE_GUARDED));
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/*
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* enable the memory coherence always
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*/
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rflags |= HPTE_R_M;
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/* Insert into the hash table, primary slot */
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slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags, 0,
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@ -99,6 +99,10 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
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/* Add in WIMG bits */
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rflags |= (new_pte & (_PAGE_WRITETHRU | _PAGE_NO_CACHE |
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_PAGE_COHERENT | _PAGE_GUARDED));
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/*
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* enable the memory coherence always
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*/
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rflags |= HPTE_R_M;
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slot = hpte_insert_repeating(hash, vpn, pa, rflags, 0,
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mmu_psize, ssize);
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