[CPUFREQ] EXYNOS4210: Remove code about bus on cpufreq
This patch removes code for bus on cpufreq because the code for bus frequency changing moves to busfreq driver. So code about bus on cpufreq is not necessary. Signed-off-by: Jaecheol Lee <jc.lee@samsung.com> Signed-off-by: Jongpill Lee <boyko.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Dave Jones <davej@redhat.com>
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@ -33,21 +33,13 @@ static struct clk *mout_mpll;
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static struct clk *mout_apll;
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static struct regulator *arm_regulator;
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static struct regulator *int_regulator;
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static struct cpufreq_freqs freqs;
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static unsigned int memtype;
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static unsigned int locking_frequency;
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static bool frequency_locked;
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static DEFINE_MUTEX(cpufreq_lock);
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enum exynos4_memory_type {
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DDR2 = 4,
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LPDDR2,
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DDR3,
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};
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enum cpufreq_level_index {
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L0, L1, L2, L3, CPUFREQ_LEVEL_END,
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};
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@ -99,87 +91,24 @@ static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
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{ 3, 0 },
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};
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static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END][8] = {
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/*
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* Clock divider value for following
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* { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
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* DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
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*/
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/* DMC L0: 400MHz */
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{ 3, 1, 1, 1, 1, 1, 3, 1 },
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/* DMC L1: 400MHz */
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{ 3, 1, 1, 1, 1, 1, 3, 1 },
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/* DMC L2: 266.7MHz */
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{ 7, 1, 1, 2, 1, 1, 3, 1 },
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/* DMC L3: 200MHz */
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{ 7, 1, 1, 3, 1, 1, 3, 1 },
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};
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static unsigned int clkdiv_top[CPUFREQ_LEVEL_END][5] = {
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/*
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* Clock divider value for following
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* { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
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*/
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/* ACLK200 L0: 200MHz */
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{ 3, 7, 4, 5, 1 },
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/* ACLK200 L1: 200MHz */
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{ 3, 7, 4, 5, 1 },
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/* ACLK200 L2: 160MHz */
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{ 4, 7, 5, 7, 1 },
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/* ACLK200 L3: 133.3MHz */
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{ 5, 7, 7, 7, 1 },
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};
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static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END][2] = {
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/*
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* Clock divider value for following
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* { DIVGDL/R, DIVGPL/R }
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*/
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/* ACLK_GDL/R L0: 200MHz */
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{ 3, 1 },
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/* ACLK_GDL/R L1: 200MHz */
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{ 3, 1 },
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/* ACLK_GDL/R L2: 160MHz */
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{ 4, 1 },
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/* ACLK_GDL/R L3: 133.3MHz */
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{ 5, 1 },
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};
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struct cpufreq_voltage_table {
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unsigned int index; /* any */
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unsigned int arm_volt; /* uV */
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unsigned int int_volt;
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};
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static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] = {
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{
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.index = L0,
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.arm_volt = 1200000,
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.int_volt = 1100000,
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}, {
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.index = L1,
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.arm_volt = 1100000,
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.int_volt = 1100000,
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}, {
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.index = L2,
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.arm_volt = 1000000,
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.int_volt = 1000000,
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}, {
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.index = L3,
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.arm_volt = 900000,
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.int_volt = 1000000,
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},
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};
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@ -248,80 +177,6 @@ static void exynos4_set_clkdiv(unsigned int div_index)
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do {
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tmp = __raw_readl(S5P_CLKDIV_STATCPU1);
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} while (tmp & 0x11);
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/* Change Divider - DMC0 */
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tmp = __raw_readl(S5P_CLKDIV_DMC0);
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tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK | S5P_CLKDIV_DMC0_ACPPCLK_MASK |
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S5P_CLKDIV_DMC0_DPHY_MASK | S5P_CLKDIV_DMC0_DMC_MASK |
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S5P_CLKDIV_DMC0_DMCD_MASK | S5P_CLKDIV_DMC0_DMCP_MASK |
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S5P_CLKDIV_DMC0_COPY2_MASK | S5P_CLKDIV_DMC0_CORETI_MASK);
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tmp |= ((clkdiv_dmc0[div_index][0] << S5P_CLKDIV_DMC0_ACP_SHIFT) |
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(clkdiv_dmc0[div_index][1] << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
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(clkdiv_dmc0[div_index][2] << S5P_CLKDIV_DMC0_DPHY_SHIFT) |
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(clkdiv_dmc0[div_index][3] << S5P_CLKDIV_DMC0_DMC_SHIFT) |
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(clkdiv_dmc0[div_index][4] << S5P_CLKDIV_DMC0_DMCD_SHIFT) |
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(clkdiv_dmc0[div_index][5] << S5P_CLKDIV_DMC0_DMCP_SHIFT) |
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(clkdiv_dmc0[div_index][6] << S5P_CLKDIV_DMC0_COPY2_SHIFT) |
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(clkdiv_dmc0[div_index][7] << S5P_CLKDIV_DMC0_CORETI_SHIFT));
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__raw_writel(tmp, S5P_CLKDIV_DMC0);
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do {
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tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
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} while (tmp & 0x11111111);
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/* Change Divider - TOP */
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tmp = __raw_readl(S5P_CLKDIV_TOP);
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tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK | S5P_CLKDIV_TOP_ACLK100_MASK |
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S5P_CLKDIV_TOP_ACLK160_MASK | S5P_CLKDIV_TOP_ACLK133_MASK |
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S5P_CLKDIV_TOP_ONENAND_MASK);
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tmp |= ((clkdiv_top[div_index][0] << S5P_CLKDIV_TOP_ACLK200_SHIFT) |
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(clkdiv_top[div_index][1] << S5P_CLKDIV_TOP_ACLK100_SHIFT) |
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(clkdiv_top[div_index][2] << S5P_CLKDIV_TOP_ACLK160_SHIFT) |
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(clkdiv_top[div_index][3] << S5P_CLKDIV_TOP_ACLK133_SHIFT) |
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(clkdiv_top[div_index][4] << S5P_CLKDIV_TOP_ONENAND_SHIFT));
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__raw_writel(tmp, S5P_CLKDIV_TOP);
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do {
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tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
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} while (tmp & 0x11111);
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/* Change Divider - LEFTBUS */
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tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
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tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
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tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
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(clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
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__raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
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do {
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tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
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} while (tmp & 0x11);
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/* Change Divider - RIGHTBUS */
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tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
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tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
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tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
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(clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
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__raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
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do {
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tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
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} while (tmp & 0x11);
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}
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static void exynos4_set_apll(unsigned int index)
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@ -410,7 +265,7 @@ static int exynos4_target(struct cpufreq_policy *policy,
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unsigned int relation)
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{
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unsigned int index, old_index;
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unsigned int arm_volt, int_volt;
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unsigned int arm_volt;
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int err = -EINVAL;
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freqs.old = exynos4_getspeed(policy->cpu);
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@ -440,7 +295,6 @@ static int exynos4_target(struct cpufreq_policy *policy,
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/* get the voltage value */
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arm_volt = exynos4_volt_table[index].arm_volt;
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int_volt = exynos4_volt_table[index].int_volt;
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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@ -448,7 +302,6 @@ static int exynos4_target(struct cpufreq_policy *policy,
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if (freqs.new > freqs.old) {
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/* Voltage up */
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regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
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regulator_set_voltage(int_regulator, int_volt, int_volt);
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}
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/* Clock Configuration Procedure */
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@ -458,7 +311,6 @@ static int exynos4_target(struct cpufreq_policy *policy,
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if (freqs.new < freqs.old) {
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/* Voltage down */
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regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
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regulator_set_voltage(int_regulator, int_volt, int_volt);
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}
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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@ -636,27 +488,6 @@ static int __init exynos4_cpufreq_init(void)
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goto out;
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}
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int_regulator = regulator_get(NULL, "vdd_int");
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if (IS_ERR(int_regulator)) {
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printk(KERN_ERR "failed to get resource %s\n", "vdd_int");
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goto out;
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}
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/*
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* Check DRAM type.
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* Because DVFS level is different according to DRAM type.
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*/
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memtype = __raw_readl(S5P_VA_DMC0 + S5P_DMC0_MEMCON_OFFSET);
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memtype = (memtype >> S5P_DMC0_MEMTYPE_SHIFT);
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memtype &= S5P_DMC0_MEMTYPE_MASK;
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if ((memtype < DDR2) && (memtype > DDR3)) {
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printk(KERN_ERR "%s: wrong memtype= 0x%x\n", __func__, memtype);
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goto out;
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} else {
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printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
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}
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register_pm_notifier(&exynos4_cpufreq_nb);
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return cpufreq_register_driver(&exynos4_driver);
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@ -677,9 +508,6 @@ out:
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if (!IS_ERR(arm_regulator))
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regulator_put(arm_regulator);
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if (!IS_ERR(int_regulator))
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regulator_put(int_regulator);
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printk(KERN_ERR "%s: failed initialization\n", __func__);
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return -EINVAL;
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