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MLK-16530-1 ARM64: dts: imx8: enable rpmsg support

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enable imx8qm rpmsg support, and validated the
pingpong demo.
add the mu power and clk on imx8qxp.

BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
This commit is contained in:
Richard Zhu 2017-09-15 14:41:23 +08:00 committed by Jason Liu
parent 558204d601
commit c91cf3ce43
3 changed files with 86 additions and 0 deletions
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14
arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
View file

@ -836,3 +836,17 @@
reset-gpio = <&gpio5 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
&intmux_cm40 {
status = "okay";
};
&rpmsg{
/*
* 64K for one rpmsg instance:
* --0xb8000000~0xb800ffff: pingpong
*/
vdev-nums = <1>;
reg = <0x0 0xb8000000 0x0 0x10000>;
status = "okay";
};

63
arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
View file

@ -965,6 +965,26 @@
power-domains =<&pd_isi_ch0>;
};
};
pd_cm40: PD_CM40 {
compatible = "nxp,imx8-pd";
reg = <SC_R_LAST>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_cm40_mu0a0: PD_CM40_MU0A0{
reg = <SC_R_M4_0_MU_0A0>;
#power-domain-cells = <0>;
power-domains =<&pd_cm40>;
};
pd_cm40_intmux: PD_CM40_INTMUX {
reg = <SC_R_M4_0_INTMUX>;
#power-domain-cells = <0>;
power-domains =<&pd_cm40>;
};
};
};
tsens: thermal-sensor {
@ -2786,6 +2806,49 @@
cpu-base-addr = <0x80000000>;
status = "disabled";
};
intmux_cm40: intmux@37400000 {
compatible = "nxp,imx-intmux";
reg = <0x0 0x37400000 0x0 0x1000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
clocks = <&clk IMX8QM_CM40_IPG_CLK>;
clock-names = "ipg";
power-domains = <&pd_cm40_intmux>;
status = "disabled";
};
imx_rpmsg: imx_rpmsg {
compatible = "fsl,rpmsg-bus", "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
mu_rpmsg: mu_rpmsg@37440000 {
compatible = "fsl,imx8-mu", "fsl,imx6sx-mu";
reg = <0x0 0x37440000 0x0 0x10000>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intmux_cm40>;
clocks = <&clk IMX8QM_CM40_IPG_CLK>;
clock-names = "ipg";
power-domains = <&pd_cm40_mu0a0>;
status = "okay";
};
rpmsg: rpmsg {
compatible = "fsl,imx8qxp-rpmsg";
status = "disabled";
};
};
};
&A53_0 {

9
arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
View file

@ -674,6 +674,12 @@
#power-domain-cells = <0>;
power-domains =<&pd_cm40>;
};
pd_cm40_mu0a0: PD_CM40_MU0A0{
reg = <SC_R_M4_0_MU_0A0>;
#power-domain-cells = <0>;
power-domains =<&pd_cm40>;
};
};
@ -2094,6 +2100,9 @@
reg = <0x0 0x37440000 0x0 0x10000>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intmux_cm40>;
clocks = <&clk IMX8QXP_CM40_IPG_CLK>;
clock-names = "ipg";
power-domains = <&pd_cm40_mu0a0>;
status = "okay";
};