arm64: insn: remove BUG_ON from codegen
During code generation, we used to BUG_ON unknown/unsupported encoding or invalid parameters. Instead, now we report these as errors and simply return the instruction AARCH64_BREAK_FAULT. Users of these codegen helpers should check for and handle this failure condition as appropriate. Otherwise, unhandled codegen failure will result in trapping at run-time due to AARCH64_BREAK_FAULT, which is arguably better than a BUG_ON. Signed-off-by: Zi Shen Lim <zlim.lnx@gmail.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Zi Shen Lim
David S. Miller
parent
dd7445ad6b
commit
c94ae4f7c5
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@ -2,7 +2,7 @@
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* Copyright (C) 2013 Huawei Ltd.
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* Author: Jiang Liu <liuj97@gmail.com>
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*
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* Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
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* Copyright (C) 2014-2016 Zi Shen Lim <zlim.lnx@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -363,6 +363,9 @@ u32 __kprobes aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
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u32 immlo, immhi, mask;
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int shift;
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if (insn == AARCH64_BREAK_FAULT)
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return AARCH64_BREAK_FAULT;
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switch (type) {
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case AARCH64_INSN_IMM_ADR:
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shift = 0;
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@ -377,7 +380,7 @@ u32 __kprobes aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
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if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) {
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pr_err("aarch64_insn_encode_immediate: unknown immediate encoding %d\n",
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type);
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return 0;
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return AARCH64_BREAK_FAULT;
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}
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}
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@ -394,9 +397,12 @@ static u32 aarch64_insn_encode_register(enum aarch64_insn_register_type type,
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{
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int shift;
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if (insn == AARCH64_BREAK_FAULT)
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return AARCH64_BREAK_FAULT;
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if (reg < AARCH64_INSN_REG_0 || reg > AARCH64_INSN_REG_SP) {
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pr_err("%s: unknown register encoding %d\n", __func__, reg);
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return 0;
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return AARCH64_BREAK_FAULT;
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}
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switch (type) {
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@ -417,7 +423,7 @@ static u32 aarch64_insn_encode_register(enum aarch64_insn_register_type type,
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default:
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pr_err("%s: unknown register type encoding %d\n", __func__,
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type);
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return 0;
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return AARCH64_BREAK_FAULT;
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}
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insn &= ~(GENMASK(4, 0) << shift);
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@ -446,7 +452,7 @@ static u32 aarch64_insn_encode_ldst_size(enum aarch64_insn_size_type type,
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break;
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default:
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pr_err("%s: unknown size encoding %d\n", __func__, type);
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return 0;
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return AARCH64_BREAK_FAULT;
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}
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insn &= ~GENMASK(31, 30);
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@ -460,14 +466,17 @@ static inline long branch_imm_common(unsigned long pc, unsigned long addr,
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{
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long offset;
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/*
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* PC: A 64-bit Program Counter holding the address of the current
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* instruction. A64 instructions must be word-aligned.
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*/
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BUG_ON((pc & 0x3) || (addr & 0x3));
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if ((pc & 0x3) || (addr & 0x3)) {
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pr_err("%s: A64 instructions must be word aligned\n", __func__);
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return range;
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}
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offset = ((long)addr - (long)pc);
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BUG_ON(offset < -range || offset >= range);
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if (offset < -range || offset >= range) {
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pr_err("%s: offset out of range\n", __func__);
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return range;
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}
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return offset;
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}
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@ -484,6 +493,8 @@ u32 __kprobes aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
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* texts are within +/-128M.
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*/
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offset = branch_imm_common(pc, addr, SZ_128M);
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if (offset >= SZ_128M)
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return AARCH64_BREAK_FAULT;
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switch (type) {
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case AARCH64_INSN_BRANCH_LINK:
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@ -493,7 +504,7 @@ u32 __kprobes aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
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insn = aarch64_insn_get_b_value();
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break;
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default:
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BUG_ON(1);
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pr_err("%s: unknown branch encoding %d\n", __func__, type);
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return AARCH64_BREAK_FAULT;
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}
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@ -510,6 +521,8 @@ u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
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long offset;
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offset = branch_imm_common(pc, addr, SZ_1M);
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if (offset >= SZ_1M)
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return AARCH64_BREAK_FAULT;
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switch (type) {
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case AARCH64_INSN_BRANCH_COMP_ZERO:
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@ -519,7 +532,7 @@ u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
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insn = aarch64_insn_get_cbnz_value();
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break;
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default:
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BUG_ON(1);
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pr_err("%s: unknown branch encoding %d\n", __func__, type);
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return AARCH64_BREAK_FAULT;
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}
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@ -530,7 +543,7 @@ u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
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insn |= AARCH64_INSN_SF_BIT;
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break;
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default:
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BUG_ON(1);
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pr_err("%s: unknown variant encoding %d\n", __func__, variant);
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return AARCH64_BREAK_FAULT;
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}
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@ -550,7 +563,10 @@ u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
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insn = aarch64_insn_get_bcond_value();
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BUG_ON(cond < AARCH64_INSN_COND_EQ || cond > AARCH64_INSN_COND_AL);
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if (cond < AARCH64_INSN_COND_EQ || cond > AARCH64_INSN_COND_AL) {
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pr_err("%s: unknown condition encoding %d\n", __func__, cond);
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return AARCH64_BREAK_FAULT;
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}
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insn |= cond;
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return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
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@ -583,7 +599,7 @@ u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
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insn = aarch64_insn_get_ret_value();
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break;
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default:
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BUG_ON(1);
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pr_err("%s: unknown branch encoding %d\n", __func__, type);
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return AARCH64_BREAK_FAULT;
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}
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@ -606,7 +622,7 @@ u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
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insn = aarch64_insn_get_str_reg_value();
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break;
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default:
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BUG_ON(1);
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pr_err("%s: unknown load/store encoding %d\n", __func__, type);
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return AARCH64_BREAK_FAULT;
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}
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@ -645,26 +661,30 @@ u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
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insn = aarch64_insn_get_stp_post_value();
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break;
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default:
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BUG_ON(1);
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pr_err("%s: unknown load/store encoding %d\n", __func__, type);
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return AARCH64_BREAK_FAULT;
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}
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switch (variant) {
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case AARCH64_INSN_VARIANT_32BIT:
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/* offset must be multiples of 4 in the range [-256, 252] */
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BUG_ON(offset & 0x3);
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BUG_ON(offset < -256 || offset > 252);
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if ((offset & 0x3) || (offset < -256) || (offset > 252)) {
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pr_err("%s: offset must be multiples of 4 in the range of [-256, 252] %d\n",
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__func__, offset);
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return AARCH64_BREAK_FAULT;
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}
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shift = 2;
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break;
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case AARCH64_INSN_VARIANT_64BIT:
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/* offset must be multiples of 8 in the range [-512, 504] */
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BUG_ON(offset & 0x7);
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BUG_ON(offset < -512 || offset > 504);
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if ((offset & 0x7) || (offset < -512) || (offset > 504)) {
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pr_err("%s: offset must be multiples of 8 in the range of [-512, 504] %d\n",
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__func__, offset);
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return AARCH64_BREAK_FAULT;
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}
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shift = 3;
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insn |= AARCH64_INSN_SF_BIT;
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break;
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default:
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BUG_ON(1);
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pr_err("%s: unknown variant encoding %d\n", __func__, variant);
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return AARCH64_BREAK_FAULT;
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}
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@ -702,7 +722,7 @@ u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
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insn = aarch64_insn_get_subs_imm_value();
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break;
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default:
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BUG_ON(1);
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pr_err("%s: unknown add/sub encoding %d\n", __func__, type);
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return AARCH64_BREAK_FAULT;
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}
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@ -713,11 +733,14 @@ u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
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insn |= AARCH64_INSN_SF_BIT;
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break;
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default:
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BUG_ON(1);
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pr_err("%s: unknown variant encoding %d\n", __func__, variant);
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return AARCH64_BREAK_FAULT;
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}
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BUG_ON(imm & ~(SZ_4K - 1));
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if (imm & ~(SZ_4K - 1)) {
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pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
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return AARCH64_BREAK_FAULT;
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}
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insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
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@ -746,7 +769,7 @@ u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
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insn = aarch64_insn_get_sbfm_value();
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break;
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default:
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BUG_ON(1);
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pr_err("%s: unknown bitfield encoding %d\n", __func__, type);
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return AARCH64_BREAK_FAULT;
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}
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@ -759,12 +782,18 @@ u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
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mask = GENMASK(5, 0);
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break;
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default:
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BUG_ON(1);
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pr_err("%s: unknown variant encoding %d\n", __func__, variant);
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return AARCH64_BREAK_FAULT;
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}
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BUG_ON(immr & ~mask);
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BUG_ON(imms & ~mask);
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if (immr & ~mask) {
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pr_err("%s: invalid immr encoding %d\n", __func__, immr);
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return AARCH64_BREAK_FAULT;
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}
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if (imms & ~mask) {
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pr_err("%s: invalid imms encoding %d\n", __func__, imms);
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return AARCH64_BREAK_FAULT;
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}
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insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
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@ -793,23 +822,33 @@ u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
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insn = aarch64_insn_get_movn_value();
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break;
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default:
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BUG_ON(1);
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pr_err("%s: unknown movewide encoding %d\n", __func__, type);
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return AARCH64_BREAK_FAULT;
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}
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BUG_ON(imm & ~(SZ_64K - 1));
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if (imm & ~(SZ_64K - 1)) {
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pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
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return AARCH64_BREAK_FAULT;
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}
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switch (variant) {
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case AARCH64_INSN_VARIANT_32BIT:
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BUG_ON(shift != 0 && shift != 16);
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if (shift != 0 && shift != 16) {
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pr_err("%s: invalid shift encoding %d\n", __func__,
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shift);
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return AARCH64_BREAK_FAULT;
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}
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break;
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case AARCH64_INSN_VARIANT_64BIT:
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insn |= AARCH64_INSN_SF_BIT;
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BUG_ON(shift != 0 && shift != 16 && shift != 32 &&
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shift != 48);
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if (shift != 0 && shift != 16 && shift != 32 && shift != 48) {
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pr_err("%s: invalid shift encoding %d\n", __func__,
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shift);
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return AARCH64_BREAK_FAULT;
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}
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break;
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default:
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BUG_ON(1);
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pr_err("%s: unknown variant encoding %d\n", __func__, variant);
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return AARCH64_BREAK_FAULT;
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}
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@ -843,20 +882,28 @@ u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
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insn = aarch64_insn_get_subs_value();
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break;
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default:
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BUG_ON(1);
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pr_err("%s: unknown add/sub encoding %d\n", __func__, type);
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return AARCH64_BREAK_FAULT;
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}
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switch (variant) {
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case AARCH64_INSN_VARIANT_32BIT:
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BUG_ON(shift & ~(SZ_32 - 1));
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if (shift & ~(SZ_32 - 1)) {
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pr_err("%s: invalid shift encoding %d\n", __func__,
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shift);
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return AARCH64_BREAK_FAULT;
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}
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break;
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case AARCH64_INSN_VARIANT_64BIT:
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insn |= AARCH64_INSN_SF_BIT;
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BUG_ON(shift & ~(SZ_64 - 1));
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if (shift & ~(SZ_64 - 1)) {
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pr_err("%s: invalid shift encoding %d\n", __func__,
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shift);
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return AARCH64_BREAK_FAULT;
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}
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break;
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default:
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BUG_ON(1);
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pr_err("%s: unknown variant encoding %d\n", __func__, variant);
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return AARCH64_BREAK_FAULT;
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}
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@ -885,11 +932,15 @@ u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
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insn = aarch64_insn_get_rev32_value();
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break;
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case AARCH64_INSN_DATA1_REVERSE_64:
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BUG_ON(variant != AARCH64_INSN_VARIANT_64BIT);
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if (variant != AARCH64_INSN_VARIANT_64BIT) {
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pr_err("%s: invalid variant for reverse64 %d\n",
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__func__, variant);
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return AARCH64_BREAK_FAULT;
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}
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insn = aarch64_insn_get_rev64_value();
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break;
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default:
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BUG_ON(1);
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pr_err("%s: unknown data1 encoding %d\n", __func__, type);
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return AARCH64_BREAK_FAULT;
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}
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@ -900,7 +951,7 @@ u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
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insn |= AARCH64_INSN_SF_BIT;
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break;
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default:
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BUG_ON(1);
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pr_err("%s: unknown variant encoding %d\n", __func__, variant);
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return AARCH64_BREAK_FAULT;
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}
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@ -937,7 +988,7 @@ u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
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insn = aarch64_insn_get_rorv_value();
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break;
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default:
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BUG_ON(1);
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pr_err("%s: unknown data2 encoding %d\n", __func__, type);
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return AARCH64_BREAK_FAULT;
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}
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@ -948,7 +999,7 @@ u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
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insn |= AARCH64_INSN_SF_BIT;
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break;
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default:
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BUG_ON(1);
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pr_err("%s: unknown variant encoding %d\n", __func__, variant);
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return AARCH64_BREAK_FAULT;
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}
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@ -976,7 +1027,7 @@ u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
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insn = aarch64_insn_get_msub_value();
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break;
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default:
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BUG_ON(1);
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pr_err("%s: unknown data3 encoding %d\n", __func__, type);
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return AARCH64_BREAK_FAULT;
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}
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@ -987,7 +1038,7 @@ u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
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insn |= AARCH64_INSN_SF_BIT;
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break;
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default:
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BUG_ON(1);
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pr_err("%s: unknown variant encoding %d\n", __func__, variant);
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return AARCH64_BREAK_FAULT;
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}
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@ -1037,20 +1088,28 @@ u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
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insn = aarch64_insn_get_bics_value();
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break;
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default:
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BUG_ON(1);
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pr_err("%s: unknown logical encoding %d\n", __func__, type);
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return AARCH64_BREAK_FAULT;
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}
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switch (variant) {
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case AARCH64_INSN_VARIANT_32BIT:
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BUG_ON(shift & ~(SZ_32 - 1));
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if (shift & ~(SZ_32 - 1)) {
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pr_err("%s: invalid shift encoding %d\n", __func__,
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shift);
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return AARCH64_BREAK_FAULT;
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}
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break;
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case AARCH64_INSN_VARIANT_64BIT:
|
||||
insn |= AARCH64_INSN_SF_BIT;
|
||||
BUG_ON(shift & ~(SZ_64 - 1));
|
||||
if (shift & ~(SZ_64 - 1)) {
|
||||
pr_err("%s: invalid shift encoding %d\n", __func__,
|
||||
shift);
|
||||
return AARCH64_BREAK_FAULT;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
BUG_ON(1);
|
||||
pr_err("%s: unknown variant encoding %d\n", __func__, variant);
|
||||
return AARCH64_BREAK_FAULT;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue