Adding in EEH support to the IBM FlashSystem 70/80 device driver
Changes in v2 include: o Fixed spelling of guarantee. o Fixed potential memory leak if slot reset fails out. o Changed list_for_each_entry_safe with list_for_each_entry. Signed-off-by: Philip J Kelleher <pjk1939@linux.vnet.ibm.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
This commit is contained in:
Philip J Kelleher
Jens Axboe
parent
1ebfd10982
commit
c95246c3a2
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@ -30,6 +30,7 @@
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#include <linux/reboot.h>
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#include <linux/slab.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/genhd.h>
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#include <linux/idr.h>
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@ -52,6 +53,13 @@ static DEFINE_IDA(rsxx_disk_ida);
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static DEFINE_SPINLOCK(rsxx_ida_lock);
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/*----------------- Interrupt Control & Handling -------------------*/
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static void rsxx_mask_interrupts(struct rsxx_cardinfo *card)
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{
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card->isr_mask = 0;
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card->ier_mask = 0;
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}
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static void __enable_intr(unsigned int *mask, unsigned int intr)
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{
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*mask |= intr;
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@ -71,7 +79,8 @@ static void __disable_intr(unsigned int *mask, unsigned int intr)
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*/
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void rsxx_enable_ier(struct rsxx_cardinfo *card, unsigned int intr)
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{
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if (unlikely(card->halt))
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if (unlikely(card->halt) ||
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unlikely(card->eeh_state))
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return;
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__enable_intr(&card->ier_mask, intr);
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@ -80,6 +89,9 @@ void rsxx_enable_ier(struct rsxx_cardinfo *card, unsigned int intr)
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void rsxx_disable_ier(struct rsxx_cardinfo *card, unsigned int intr)
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{
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if (unlikely(card->eeh_state))
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return;
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__disable_intr(&card->ier_mask, intr);
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iowrite32(card->ier_mask, card->regmap + IER);
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}
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@ -87,7 +99,8 @@ void rsxx_disable_ier(struct rsxx_cardinfo *card, unsigned int intr)
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void rsxx_enable_ier_and_isr(struct rsxx_cardinfo *card,
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unsigned int intr)
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{
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if (unlikely(card->halt))
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if (unlikely(card->halt) ||
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unlikely(card->eeh_state))
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return;
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__enable_intr(&card->isr_mask, intr);
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@ -97,6 +110,9 @@ void rsxx_enable_ier_and_isr(struct rsxx_cardinfo *card,
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void rsxx_disable_ier_and_isr(struct rsxx_cardinfo *card,
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unsigned int intr)
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{
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if (unlikely(card->eeh_state))
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return;
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__disable_intr(&card->isr_mask, intr);
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__disable_intr(&card->ier_mask, intr);
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iowrite32(card->ier_mask, card->regmap + IER);
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@ -115,6 +131,9 @@ static irqreturn_t rsxx_isr(int irq, void *pdata)
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do {
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reread_isr = 0;
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if (unlikely(card->eeh_state))
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break;
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isr = ioread32(card->regmap + ISR);
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if (isr == 0xffffffff) {
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/*
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@ -304,6 +323,179 @@ static int card_shutdown(struct rsxx_cardinfo *card)
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return 0;
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}
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static void rsxx_eeh_frozen(struct pci_dev *dev)
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{
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struct rsxx_cardinfo *card = pci_get_drvdata(dev);
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int i;
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dev_warn(&dev->dev, "IBM FlashSystem PCI: preparing for slot reset.\n");
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card->eeh_state = 1;
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rsxx_mask_interrupts(card);
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/*
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* We need to guarantee that the write for eeh_state and masking
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* interrupts does not become reordered. This will prevent a possible
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* race condition with the EEH code.
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*/
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wmb();
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pci_disable_device(dev);
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rsxx_eeh_save_issued_dmas(card);
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rsxx_eeh_save_issued_creg(card);
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for (i = 0; i < card->n_targets; i++) {
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if (card->ctrl[i].status.buf)
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pci_free_consistent(card->dev, STATUS_BUFFER_SIZE8,
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card->ctrl[i].status.buf,
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card->ctrl[i].status.dma_addr);
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if (card->ctrl[i].cmd.buf)
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pci_free_consistent(card->dev, COMMAND_BUFFER_SIZE8,
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card->ctrl[i].cmd.buf,
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card->ctrl[i].cmd.dma_addr);
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}
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}
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static void rsxx_eeh_failure(struct pci_dev *dev)
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{
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struct rsxx_cardinfo *card = pci_get_drvdata(dev);
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int i;
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dev_err(&dev->dev, "IBM FlashSystem PCI: disabling failed card.\n");
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card->eeh_state = 1;
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for (i = 0; i < card->n_targets; i++)
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del_timer_sync(&card->ctrl[i].activity_timer);
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rsxx_eeh_cancel_dmas(card);
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}
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static int rsxx_eeh_fifo_flush_poll(struct rsxx_cardinfo *card)
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{
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unsigned int status;
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int iter = 0;
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/* We need to wait for the hardware to reset */
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while (iter++ < 10) {
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status = ioread32(card->regmap + PCI_RECONFIG);
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if (status & RSXX_FLUSH_BUSY) {
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ssleep(1);
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continue;
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}
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if (status & RSXX_FLUSH_TIMEOUT)
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dev_warn(CARD_TO_DEV(card), "HW: flash controller timeout\n");
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return 0;
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}
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/* Hardware failed resetting itself. */
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return -1;
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}
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static pci_ers_result_t rsxx_error_detected(struct pci_dev *dev,
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enum pci_channel_state error)
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{
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if (dev->revision < RSXX_EEH_SUPPORT)
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return PCI_ERS_RESULT_NONE;
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if (error == pci_channel_io_perm_failure) {
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rsxx_eeh_failure(dev);
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return PCI_ERS_RESULT_DISCONNECT;
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}
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rsxx_eeh_frozen(dev);
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return PCI_ERS_RESULT_NEED_RESET;
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}
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static pci_ers_result_t rsxx_slot_reset(struct pci_dev *dev)
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{
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struct rsxx_cardinfo *card = pci_get_drvdata(dev);
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unsigned long flags;
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int i;
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int st;
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dev_warn(&dev->dev,
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"IBM FlashSystem PCI: recovering from slot reset.\n");
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st = pci_enable_device(dev);
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if (st)
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goto failed_hw_setup;
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pci_set_master(dev);
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st = rsxx_eeh_fifo_flush_poll(card);
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if (st)
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goto failed_hw_setup;
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rsxx_dma_queue_reset(card);
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for (i = 0; i < card->n_targets; i++) {
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st = rsxx_hw_buffers_init(dev, &card->ctrl[i]);
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if (st)
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goto failed_hw_buffers_init;
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}
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if (card->config_valid)
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rsxx_dma_configure(card);
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/* Clears the ISR register from spurious interrupts */
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st = ioread32(card->regmap + ISR);
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card->eeh_state = 0;
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st = rsxx_eeh_remap_dmas(card);
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if (st)
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goto failed_remap_dmas;
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spin_lock_irqsave(&card->irq_lock, flags);
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if (card->n_targets & RSXX_MAX_TARGETS)
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rsxx_enable_ier_and_isr(card, CR_INTR_ALL_G);
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else
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rsxx_enable_ier_and_isr(card, CR_INTR_ALL_C);
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spin_unlock_irqrestore(&card->irq_lock, flags);
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rsxx_kick_creg_queue(card);
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for (i = 0; i < card->n_targets; i++) {
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spin_lock(&card->ctrl[i].queue_lock);
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if (list_empty(&card->ctrl[i].queue)) {
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spin_unlock(&card->ctrl[i].queue_lock);
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continue;
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}
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spin_unlock(&card->ctrl[i].queue_lock);
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queue_work(card->ctrl[i].issue_wq,
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&card->ctrl[i].issue_dma_work);
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}
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dev_info(&dev->dev, "IBM FlashSystem PCI: recovery complete.\n");
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return PCI_ERS_RESULT_RECOVERED;
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failed_hw_buffers_init:
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failed_remap_dmas:
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for (i = 0; i < card->n_targets; i++) {
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if (card->ctrl[i].status.buf)
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pci_free_consistent(card->dev,
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STATUS_BUFFER_SIZE8,
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card->ctrl[i].status.buf,
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card->ctrl[i].status.dma_addr);
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if (card->ctrl[i].cmd.buf)
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pci_free_consistent(card->dev,
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COMMAND_BUFFER_SIZE8,
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card->ctrl[i].cmd.buf,
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card->ctrl[i].cmd.dma_addr);
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}
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failed_hw_setup:
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rsxx_eeh_failure(dev);
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return PCI_ERS_RESULT_DISCONNECT;
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}
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/*----------------- Driver Initialization & Setup -------------------*/
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/* Returns: 0 if the driver is compatible with the device
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-1 if the driver is NOT compatible with the device */
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@ -383,6 +575,7 @@ static int rsxx_pci_probe(struct pci_dev *dev,
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spin_lock_init(&card->irq_lock);
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card->halt = 0;
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card->eeh_state = 0;
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spin_lock_irq(&card->irq_lock);
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rsxx_disable_ier_and_isr(card, CR_INTR_ALL);
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@ -593,6 +786,11 @@ static void rsxx_pci_shutdown(struct pci_dev *dev)
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card_shutdown(card);
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}
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static const struct pci_error_handlers rsxx_err_handler = {
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.error_detected = rsxx_error_detected,
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.slot_reset = rsxx_slot_reset,
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};
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static DEFINE_PCI_DEVICE_TABLE(rsxx_pci_ids) = {
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{PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_FS70_FLASH)},
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{PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_FS80_FLASH)},
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@ -608,6 +806,7 @@ static struct pci_driver rsxx_pci_driver = {
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.remove = rsxx_pci_remove,
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.suspend = rsxx_pci_suspend,
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.shutdown = rsxx_pci_shutdown,
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.err_handler = &rsxx_err_handler,
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};
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static int __init rsxx_core_init(void)
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@ -58,7 +58,7 @@ static struct kmem_cache *creg_cmd_pool;
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#error Unknown endianess!!! Aborting...
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#endif
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static void copy_to_creg_data(struct rsxx_cardinfo *card,
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static int copy_to_creg_data(struct rsxx_cardinfo *card,
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int cnt8,
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void *buf,
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unsigned int stream)
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@ -66,6 +66,9 @@ static void copy_to_creg_data(struct rsxx_cardinfo *card,
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int i = 0;
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u32 *data = buf;
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if (unlikely(card->eeh_state))
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return -EIO;
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for (i = 0; cnt8 > 0; i++, cnt8 -= 4) {
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/*
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* Firmware implementation makes it necessary to byte swap on
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@ -76,10 +79,12 @@ static void copy_to_creg_data(struct rsxx_cardinfo *card,
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else
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iowrite32(data[i], card->regmap + CREG_DATA(i));
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}
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return 0;
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}
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static void copy_from_creg_data(struct rsxx_cardinfo *card,
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static int copy_from_creg_data(struct rsxx_cardinfo *card,
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int cnt8,
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void *buf,
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unsigned int stream)
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@ -87,6 +92,9 @@ static void copy_from_creg_data(struct rsxx_cardinfo *card,
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int i = 0;
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u32 *data = buf;
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if (unlikely(card->eeh_state))
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return -EIO;
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for (i = 0; cnt8 > 0; i++, cnt8 -= 4) {
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/*
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* Firmware implementation makes it necessary to byte swap on
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@ -97,19 +105,32 @@ static void copy_from_creg_data(struct rsxx_cardinfo *card,
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else
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data[i] = ioread32(card->regmap + CREG_DATA(i));
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}
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return 0;
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}
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static void creg_issue_cmd(struct rsxx_cardinfo *card, struct creg_cmd *cmd)
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{
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int st;
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if (unlikely(card->eeh_state))
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return;
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iowrite32(cmd->addr, card->regmap + CREG_ADD);
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iowrite32(cmd->cnt8, card->regmap + CREG_CNT);
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if (cmd->op == CREG_OP_WRITE) {
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if (cmd->buf)
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copy_to_creg_data(card, cmd->cnt8,
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cmd->buf, cmd->stream);
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if (cmd->buf) {
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st = copy_to_creg_data(card, cmd->cnt8,
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cmd->buf, cmd->stream);
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if (st)
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return;
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}
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}
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if (unlikely(card->eeh_state))
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return;
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/* Setting the valid bit will kick off the command. */
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iowrite32(cmd->op, card->regmap + CREG_CMD);
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}
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@ -272,7 +293,7 @@ static void creg_cmd_done(struct work_struct *work)
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goto creg_done;
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}
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copy_from_creg_data(card, cnt8, cmd->buf, cmd->stream);
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st = copy_from_creg_data(card, cnt8, cmd->buf, cmd->stream);
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}
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creg_done:
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@ -675,6 +696,32 @@ int rsxx_reg_access(struct rsxx_cardinfo *card,
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return 0;
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}
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void rsxx_eeh_save_issued_creg(struct rsxx_cardinfo *card)
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{
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struct creg_cmd *cmd = NULL;
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cmd = card->creg_ctrl.active_cmd;
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card->creg_ctrl.active_cmd = NULL;
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if (cmd) {
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del_timer_sync(&card->creg_ctrl.cmd_timer);
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spin_lock_bh(&card->creg_ctrl.lock);
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list_add(&cmd->list, &card->creg_ctrl.queue);
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card->creg_ctrl.q_depth++;
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card->creg_ctrl.active = 0;
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spin_unlock_bh(&card->creg_ctrl.lock);
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}
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}
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void rsxx_kick_creg_queue(struct rsxx_cardinfo *card)
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{
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spin_lock_bh(&card->creg_ctrl.lock);
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if (!list_empty(&card->creg_ctrl.queue))
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creg_kick_queue(card);
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spin_unlock_bh(&card->creg_ctrl.lock);
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}
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/*------------ Initialization & Setup --------------*/
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int rsxx_creg_setup(struct rsxx_cardinfo *card)
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{
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|
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@ -81,9 +81,6 @@ enum rsxx_hw_status {
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HW_STATUS_FAULT = 0x08,
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};
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#define STATUS_BUFFER_SIZE8 4096
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#define COMMAND_BUFFER_SIZE8 4096
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static struct kmem_cache *rsxx_dma_pool;
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struct dma_tracker {
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@ -122,7 +119,7 @@ static unsigned int rsxx_get_dma_tgt(struct rsxx_cardinfo *card, u64 addr8)
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return tgt;
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}
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static void rsxx_dma_queue_reset(struct rsxx_cardinfo *card)
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void rsxx_dma_queue_reset(struct rsxx_cardinfo *card)
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{
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/* Reset all DMA Command/Status Queues */
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iowrite32(DMA_QUEUE_RESET, card->regmap + RESET);
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@ -210,7 +207,8 @@ static void dma_intr_coal_auto_tune(struct rsxx_cardinfo *card)
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u32 q_depth = 0;
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u32 intr_coal;
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if (card->config.data.intr_coal.mode != RSXX_INTR_COAL_AUTO_TUNE)
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if (card->config.data.intr_coal.mode != RSXX_INTR_COAL_AUTO_TUNE ||
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unlikely(card->eeh_state))
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return;
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for (i = 0; i < card->n_targets; i++)
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|
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@ -223,31 +221,26 @@ static void dma_intr_coal_auto_tune(struct rsxx_cardinfo *card)
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}
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/*----------------- RSXX DMA Handling -------------------*/
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static void rsxx_complete_dma(struct rsxx_cardinfo *card,
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static void rsxx_complete_dma(struct rsxx_dma_ctrl *ctrl,
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struct rsxx_dma *dma,
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unsigned int status)
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{
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if (status & DMA_SW_ERR)
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printk_ratelimited(KERN_ERR
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"SW Error in DMA(cmd x%02x, laddr x%08x)\n",
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dma->cmd, dma->laddr);
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ctrl->stats.dma_sw_err++;
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if (status & DMA_HW_FAULT)
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printk_ratelimited(KERN_ERR
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"HW Fault in DMA(cmd x%02x, laddr x%08x)\n",
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dma->cmd, dma->laddr);
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ctrl->stats.dma_hw_fault++;
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if (status & DMA_CANCELLED)
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printk_ratelimited(KERN_ERR
|
||||
"DMA Cancelled(cmd x%02x, laddr x%08x)\n",
|
||||
dma->cmd, dma->laddr);
|
||||
ctrl->stats.dma_cancelled++;
|
||||
|
||||
if (dma->dma_addr)
|
||||
pci_unmap_page(card->dev, dma->dma_addr, get_dma_size(dma),
|
||||
pci_unmap_page(ctrl->card->dev, dma->dma_addr,
|
||||
get_dma_size(dma),
|
||||
dma->cmd == HW_CMD_BLK_WRITE ?
|
||||
PCI_DMA_TODEVICE :
|
||||
PCI_DMA_FROMDEVICE);
|
||||
|
||||
if (dma->cb)
|
||||
dma->cb(card, dma->cb_data, status ? 1 : 0);
|
||||
dma->cb(ctrl->card, dma->cb_data, status ? 1 : 0);
|
||||
|
||||
kmem_cache_free(rsxx_dma_pool, dma);
|
||||
}
|
||||
|
|
@ -330,14 +323,15 @@ static void rsxx_handle_dma_error(struct rsxx_dma_ctrl *ctrl,
|
|||
if (requeue_cmd)
|
||||
rsxx_requeue_dma(ctrl, dma);
|
||||
else
|
||||
rsxx_complete_dma(ctrl->card, dma, status);
|
||||
rsxx_complete_dma(ctrl, dma, status);
|
||||
}
|
||||
|
||||
static void dma_engine_stalled(unsigned long data)
|
||||
{
|
||||
struct rsxx_dma_ctrl *ctrl = (struct rsxx_dma_ctrl *)data;
|
||||
|
||||
if (atomic_read(&ctrl->stats.hw_q_depth) == 0)
|
||||
if (atomic_read(&ctrl->stats.hw_q_depth) == 0 ||
|
||||
unlikely(ctrl->card->eeh_state))
|
||||
return;
|
||||
|
||||
if (ctrl->cmd.idx != ioread32(ctrl->regmap + SW_CMD_IDX)) {
|
||||
|
|
@ -369,7 +363,8 @@ static void rsxx_issue_dmas(struct work_struct *work)
|
|||
ctrl = container_of(work, struct rsxx_dma_ctrl, issue_dma_work);
|
||||
hw_cmd_buf = ctrl->cmd.buf;
|
||||
|
||||
if (unlikely(ctrl->card->halt))
|
||||
if (unlikely(ctrl->card->halt) ||
|
||||
unlikely(ctrl->card->eeh_state))
|
||||
return;
|
||||
|
||||
while (1) {
|
||||
|
|
@ -397,7 +392,7 @@ static void rsxx_issue_dmas(struct work_struct *work)
|
|||
*/
|
||||
if (unlikely(ctrl->card->dma_fault)) {
|
||||
push_tracker(ctrl->trackers, tag);
|
||||
rsxx_complete_dma(ctrl->card, dma, DMA_CANCELLED);
|
||||
rsxx_complete_dma(ctrl, dma, DMA_CANCELLED);
|
||||
continue;
|
||||
}
|
||||
|
||||
|
|
@ -435,6 +430,12 @@ static void rsxx_issue_dmas(struct work_struct *work)
|
|||
atomic_add(cmds_pending, &ctrl->stats.hw_q_depth);
|
||||
mod_timer(&ctrl->activity_timer,
|
||||
jiffies + DMA_ACTIVITY_TIMEOUT);
|
||||
|
||||
if (unlikely(ctrl->card->eeh_state)) {
|
||||
del_timer_sync(&ctrl->activity_timer);
|
||||
return;
|
||||
}
|
||||
|
||||
iowrite32(ctrl->cmd.idx, ctrl->regmap + SW_CMD_IDX);
|
||||
}
|
||||
}
|
||||
|
|
@ -453,7 +454,8 @@ static void rsxx_dma_done(struct work_struct *work)
|
|||
hw_st_buf = ctrl->status.buf;
|
||||
|
||||
if (unlikely(ctrl->card->halt) ||
|
||||
unlikely(ctrl->card->dma_fault))
|
||||
unlikely(ctrl->card->dma_fault) ||
|
||||
unlikely(ctrl->card->eeh_state))
|
||||
return;
|
||||
|
||||
count = le16_to_cpu(hw_st_buf[ctrl->status.idx].count);
|
||||
|
|
@ -498,7 +500,7 @@ static void rsxx_dma_done(struct work_struct *work)
|
|||
if (status)
|
||||
rsxx_handle_dma_error(ctrl, dma, status);
|
||||
else
|
||||
rsxx_complete_dma(ctrl->card, dma, 0);
|
||||
rsxx_complete_dma(ctrl, dma, 0);
|
||||
|
||||
push_tracker(ctrl->trackers, tag);
|
||||
|
||||
|
|
@ -717,20 +719,54 @@ bvec_err:
|
|||
|
||||
|
||||
/*----------------- DMA Engine Initialization & Setup -------------------*/
|
||||
int rsxx_hw_buffers_init(struct pci_dev *dev, struct rsxx_dma_ctrl *ctrl)
|
||||
{
|
||||
ctrl->status.buf = pci_alloc_consistent(dev, STATUS_BUFFER_SIZE8,
|
||||
&ctrl->status.dma_addr);
|
||||
ctrl->cmd.buf = pci_alloc_consistent(dev, COMMAND_BUFFER_SIZE8,
|
||||
&ctrl->cmd.dma_addr);
|
||||
if (ctrl->status.buf == NULL || ctrl->cmd.buf == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
memset(ctrl->status.buf, 0xac, STATUS_BUFFER_SIZE8);
|
||||
iowrite32(lower_32_bits(ctrl->status.dma_addr),
|
||||
ctrl->regmap + SB_ADD_LO);
|
||||
iowrite32(upper_32_bits(ctrl->status.dma_addr),
|
||||
ctrl->regmap + SB_ADD_HI);
|
||||
|
||||
memset(ctrl->cmd.buf, 0x83, COMMAND_BUFFER_SIZE8);
|
||||
iowrite32(lower_32_bits(ctrl->cmd.dma_addr), ctrl->regmap + CB_ADD_LO);
|
||||
iowrite32(upper_32_bits(ctrl->cmd.dma_addr), ctrl->regmap + CB_ADD_HI);
|
||||
|
||||
ctrl->status.idx = ioread32(ctrl->regmap + HW_STATUS_CNT);
|
||||
if (ctrl->status.idx > RSXX_MAX_OUTSTANDING_CMDS) {
|
||||
dev_crit(&dev->dev, "Failed reading status cnt x%x\n",
|
||||
ctrl->status.idx);
|
||||
return -EINVAL;
|
||||
}
|
||||
iowrite32(ctrl->status.idx, ctrl->regmap + HW_STATUS_CNT);
|
||||
iowrite32(ctrl->status.idx, ctrl->regmap + SW_STATUS_CNT);
|
||||
|
||||
ctrl->cmd.idx = ioread32(ctrl->regmap + HW_CMD_IDX);
|
||||
if (ctrl->cmd.idx > RSXX_MAX_OUTSTANDING_CMDS) {
|
||||
dev_crit(&dev->dev, "Failed reading cmd cnt x%x\n",
|
||||
ctrl->status.idx);
|
||||
return -EINVAL;
|
||||
}
|
||||
iowrite32(ctrl->cmd.idx, ctrl->regmap + HW_CMD_IDX);
|
||||
iowrite32(ctrl->cmd.idx, ctrl->regmap + SW_CMD_IDX);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rsxx_dma_ctrl_init(struct pci_dev *dev,
|
||||
struct rsxx_dma_ctrl *ctrl)
|
||||
{
|
||||
int i;
|
||||
int st;
|
||||
|
||||
memset(&ctrl->stats, 0, sizeof(ctrl->stats));
|
||||
|
||||
ctrl->status.buf = pci_alloc_consistent(dev, STATUS_BUFFER_SIZE8,
|
||||
&ctrl->status.dma_addr);
|
||||
ctrl->cmd.buf = pci_alloc_consistent(dev, COMMAND_BUFFER_SIZE8,
|
||||
&ctrl->cmd.dma_addr);
|
||||
if (ctrl->status.buf == NULL || ctrl->cmd.buf == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
ctrl->trackers = vmalloc(DMA_TRACKER_LIST_SIZE8);
|
||||
if (!ctrl->trackers)
|
||||
return -ENOMEM;
|
||||
|
|
@ -760,33 +796,9 @@ static int rsxx_dma_ctrl_init(struct pci_dev *dev,
|
|||
INIT_WORK(&ctrl->issue_dma_work, rsxx_issue_dmas);
|
||||
INIT_WORK(&ctrl->dma_done_work, rsxx_dma_done);
|
||||
|
||||
memset(ctrl->status.buf, 0xac, STATUS_BUFFER_SIZE8);
|
||||
iowrite32(lower_32_bits(ctrl->status.dma_addr),
|
||||
ctrl->regmap + SB_ADD_LO);
|
||||
iowrite32(upper_32_bits(ctrl->status.dma_addr),
|
||||
ctrl->regmap + SB_ADD_HI);
|
||||
|
||||
memset(ctrl->cmd.buf, 0x83, COMMAND_BUFFER_SIZE8);
|
||||
iowrite32(lower_32_bits(ctrl->cmd.dma_addr), ctrl->regmap + CB_ADD_LO);
|
||||
iowrite32(upper_32_bits(ctrl->cmd.dma_addr), ctrl->regmap + CB_ADD_HI);
|
||||
|
||||
ctrl->status.idx = ioread32(ctrl->regmap + HW_STATUS_CNT);
|
||||
if (ctrl->status.idx > RSXX_MAX_OUTSTANDING_CMDS) {
|
||||
dev_crit(&dev->dev, "Failed reading status cnt x%x\n",
|
||||
ctrl->status.idx);
|
||||
return -EINVAL;
|
||||
}
|
||||
iowrite32(ctrl->status.idx, ctrl->regmap + HW_STATUS_CNT);
|
||||
iowrite32(ctrl->status.idx, ctrl->regmap + SW_STATUS_CNT);
|
||||
|
||||
ctrl->cmd.idx = ioread32(ctrl->regmap + HW_CMD_IDX);
|
||||
if (ctrl->cmd.idx > RSXX_MAX_OUTSTANDING_CMDS) {
|
||||
dev_crit(&dev->dev, "Failed reading cmd cnt x%x\n",
|
||||
ctrl->status.idx);
|
||||
return -EINVAL;
|
||||
}
|
||||
iowrite32(ctrl->cmd.idx, ctrl->regmap + HW_CMD_IDX);
|
||||
iowrite32(ctrl->cmd.idx, ctrl->regmap + SW_CMD_IDX);
|
||||
st = rsxx_hw_buffers_init(dev, ctrl);
|
||||
if (st)
|
||||
return st;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -822,7 +834,7 @@ static int rsxx_dma_stripe_setup(struct rsxx_cardinfo *card,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int rsxx_dma_configure(struct rsxx_cardinfo *card)
|
||||
int rsxx_dma_configure(struct rsxx_cardinfo *card)
|
||||
{
|
||||
u32 intr_coal;
|
||||
|
||||
|
|
@ -968,6 +980,94 @@ void rsxx_dma_destroy(struct rsxx_cardinfo *card)
|
|||
}
|
||||
}
|
||||
|
||||
void rsxx_eeh_save_issued_dmas(struct rsxx_cardinfo *card)
|
||||
{
|
||||
int i;
|
||||
int j;
|
||||
int cnt;
|
||||
struct rsxx_dma *dma;
|
||||
struct list_head issued_dmas[card->n_targets];
|
||||
|
||||
for (i = 0; i < card->n_targets; i++) {
|
||||
INIT_LIST_HEAD(&issued_dmas[i]);
|
||||
cnt = 0;
|
||||
for (j = 0; j < RSXX_MAX_OUTSTANDING_CMDS; j++) {
|
||||
dma = get_tracker_dma(card->ctrl[i].trackers, j);
|
||||
if (dma == NULL)
|
||||
continue;
|
||||
|
||||
if (dma->cmd == HW_CMD_BLK_WRITE)
|
||||
card->ctrl[i].stats.writes_issued--;
|
||||
else if (dma->cmd == HW_CMD_BLK_DISCARD)
|
||||
card->ctrl[i].stats.discards_issued--;
|
||||
else
|
||||
card->ctrl[i].stats.reads_issued--;
|
||||
|
||||
list_add_tail(&dma->list, &issued_dmas[i]);
|
||||
push_tracker(card->ctrl[i].trackers, j);
|
||||
cnt++;
|
||||
}
|
||||
|
||||
spin_lock(&card->ctrl[i].queue_lock);
|
||||
list_splice(&issued_dmas[i], &card->ctrl[i].queue);
|
||||
|
||||
atomic_sub(cnt, &card->ctrl[i].stats.hw_q_depth);
|
||||
card->ctrl[i].stats.sw_q_depth += cnt;
|
||||
card->ctrl[i].e_cnt = 0;
|
||||
|
||||
list_for_each_entry(dma, &card->ctrl[i].queue, list) {
|
||||
if (dma->dma_addr)
|
||||
pci_unmap_page(card->dev, dma->dma_addr,
|
||||
get_dma_size(dma),
|
||||
dma->cmd == HW_CMD_BLK_WRITE ?
|
||||
PCI_DMA_TODEVICE :
|
||||
PCI_DMA_FROMDEVICE);
|
||||
}
|
||||
spin_unlock(&card->ctrl[i].queue_lock);
|
||||
}
|
||||
}
|
||||
|
||||
void rsxx_eeh_cancel_dmas(struct rsxx_cardinfo *card)
|
||||
{
|
||||
struct rsxx_dma *dma;
|
||||
struct rsxx_dma *tmp;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < card->n_targets; i++) {
|
||||
spin_lock(&card->ctrl[i].queue_lock);
|
||||
list_for_each_entry_safe(dma, tmp, &card->ctrl[i].queue, list) {
|
||||
list_del(&dma->list);
|
||||
|
||||
rsxx_complete_dma(&card->ctrl[i], dma, DMA_CANCELLED);
|
||||
}
|
||||
spin_unlock(&card->ctrl[i].queue_lock);
|
||||
}
|
||||
}
|
||||
|
||||
int rsxx_eeh_remap_dmas(struct rsxx_cardinfo *card)
|
||||
{
|
||||
struct rsxx_dma *dma;
|
||||
struct rsxx_dma *tmp;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < card->n_targets; i++) {
|
||||
spin_lock(&card->ctrl[i].queue_lock);
|
||||
list_for_each_entry(dma, &card->ctrl[i].queue, list) {
|
||||
dma->dma_addr = pci_map_page(card->dev, dma->page,
|
||||
dma->pg_off, get_dma_size(dma),
|
||||
dma->cmd == HW_CMD_BLK_WRITE ?
|
||||
PCI_DMA_TODEVICE :
|
||||
PCI_DMA_FROMDEVICE);
|
||||
if (!dma->dma_addr) {
|
||||
kmem_cache_free(rsxx_dma_pool, dma);
|
||||
return -ENOMEM;
|
||||
}
|
||||
}
|
||||
spin_unlock(&card->ctrl[i].queue_lock);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rsxx_dma_init(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -64,6 +64,9 @@ struct proc_cmd;
|
|||
#define RSXX_MAX_OUTSTANDING_CMDS 255
|
||||
#define RSXX_CS_IDX_MASK 0xff
|
||||
|
||||
#define STATUS_BUFFER_SIZE8 4096
|
||||
#define COMMAND_BUFFER_SIZE8 4096
|
||||
|
||||
#define RSXX_MAX_TARGETS 8
|
||||
|
||||
struct dma_tracker_list;
|
||||
|
|
@ -88,6 +91,9 @@ struct rsxx_dma_stats {
|
|||
u32 discards_failed;
|
||||
u32 done_rescheduled;
|
||||
u32 issue_rescheduled;
|
||||
u32 dma_sw_err;
|
||||
u32 dma_hw_fault;
|
||||
u32 dma_cancelled;
|
||||
u32 sw_q_depth; /* Number of DMAs on the SW queue. */
|
||||
atomic_t hw_q_depth; /* Number of DMAs queued to HW. */
|
||||
};
|
||||
|
|
@ -113,6 +119,7 @@ struct rsxx_dma_ctrl {
|
|||
struct rsxx_cardinfo {
|
||||
struct pci_dev *dev;
|
||||
unsigned int halt;
|
||||
unsigned int eeh_state;
|
||||
|
||||
void __iomem *regmap;
|
||||
spinlock_t irq_lock;
|
||||
|
|
@ -221,6 +228,7 @@ enum rsxx_pci_regmap {
|
|||
PERF_RD512_HI = 0xac,
|
||||
PERF_WR512_LO = 0xb0,
|
||||
PERF_WR512_HI = 0xb4,
|
||||
PCI_RECONFIG = 0xb8,
|
||||
};
|
||||
|
||||
enum rsxx_intr {
|
||||
|
|
@ -234,6 +242,8 @@ enum rsxx_intr {
|
|||
CR_INTR_DMA5 = 0x00000080,
|
||||
CR_INTR_DMA6 = 0x00000100,
|
||||
CR_INTR_DMA7 = 0x00000200,
|
||||
CR_INTR_ALL_C = 0x0000003f,
|
||||
CR_INTR_ALL_G = 0x000003ff,
|
||||
CR_INTR_DMA_ALL = 0x000003f5,
|
||||
CR_INTR_ALL = 0xffffffff,
|
||||
};
|
||||
|
|
@ -250,8 +260,14 @@ enum rsxx_pci_reset {
|
|||
DMA_QUEUE_RESET = 0x00000001,
|
||||
};
|
||||
|
||||
enum rsxx_hw_fifo_flush {
|
||||
RSXX_FLUSH_BUSY = 0x00000002,
|
||||
RSXX_FLUSH_TIMEOUT = 0x00000004,
|
||||
};
|
||||
|
||||
enum rsxx_pci_revision {
|
||||
RSXX_DISCARD_SUPPORT = 2,
|
||||
RSXX_EEH_SUPPORT = 3,
|
||||
};
|
||||
|
||||
enum rsxx_creg_cmd {
|
||||
|
|
@ -357,11 +373,17 @@ int rsxx_dma_setup(struct rsxx_cardinfo *card);
|
|||
void rsxx_dma_destroy(struct rsxx_cardinfo *card);
|
||||
int rsxx_dma_init(void);
|
||||
void rsxx_dma_cleanup(void);
|
||||
void rsxx_dma_queue_reset(struct rsxx_cardinfo *card);
|
||||
int rsxx_dma_configure(struct rsxx_cardinfo *card);
|
||||
int rsxx_dma_queue_bio(struct rsxx_cardinfo *card,
|
||||
struct bio *bio,
|
||||
atomic_t *n_dmas,
|
||||
rsxx_dma_cb cb,
|
||||
void *cb_data);
|
||||
int rsxx_hw_buffers_init(struct pci_dev *dev, struct rsxx_dma_ctrl *ctrl);
|
||||
void rsxx_eeh_save_issued_dmas(struct rsxx_cardinfo *card);
|
||||
void rsxx_eeh_cancel_dmas(struct rsxx_cardinfo *card);
|
||||
int rsxx_eeh_remap_dmas(struct rsxx_cardinfo *card);
|
||||
|
||||
/***** cregs.c *****/
|
||||
int rsxx_creg_write(struct rsxx_cardinfo *card, u32 addr,
|
||||
|
|
@ -386,10 +408,11 @@ int rsxx_creg_setup(struct rsxx_cardinfo *card);
|
|||
void rsxx_creg_destroy(struct rsxx_cardinfo *card);
|
||||
int rsxx_creg_init(void);
|
||||
void rsxx_creg_cleanup(void);
|
||||
|
||||
int rsxx_reg_access(struct rsxx_cardinfo *card,
|
||||
struct rsxx_reg_access __user *ucmd,
|
||||
int read);
|
||||
void rsxx_eeh_save_issued_creg(struct rsxx_cardinfo *card);
|
||||
void rsxx_kick_creg_queue(struct rsxx_cardinfo *card);
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue