One new clock controller for the rk3128 soc, a fixup for the rk3228 cpuclk
table and the usual bunch of some new clock-ids and some clocks marked as critical. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlk5xMgQHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgQhdCACyqXbTUEGQDaqKa40f0IPOQCPZ31XYuz8t 3kQRV08ZkBQlI0tAKgxS4+tTERtpWBA3PjIlnZQ/VRogQsiJpWj6//98Z8jJ9oEx 2lsKTw3XAb/BVsvW4Awi7VbStt5LNxRxwuIU4uXgHaapTi7wQrqAlam+2iXNOW7h 05/piVKlKOyS52009UeiO3bzFojiTlElC1JQPqnVA65KxqhYvb/9rt3hn8Y8ZqF1 KuLibE/AC5eDX7XaCFe+a7dbJpA6b+ciHg24jk+BMuksy53yYbngLbDwlOs7YFjo PjFgbdsJw25uE2i0ZwtarAOJoLOtBJiSNib6FJCmC6yHLy5Sc8l/ =kKnC -----END PGP SIGNATURE----- Merge tag 'v4.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk driver updates from Heiko Stuebner: One new clock controller for the rk3128 soc, a fixup for the rk3228 cpuclk table and the usual bunch of some new clock-ids and some clocks marked as critical. * tag 'v4.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: mark some special clk as critical on rk3368 clk: rockchip: mark noc and some special clk as critical on rk3288 clk: rockchip: mark noc and some special clk as critical on rk3228 clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036 clk: rockchip: add clock controller for rk3128 dt-bindings: add bindings for rk3128 clock controller clk: rockchip: export more rk3228 clocks ids clk: rockchip: add ids for rk3399 testclks used for camera handling clk: rockchip: add dt-binding header for rk3128 clk: rockchip: fix up the RK3228 clk cpu setting table clk: rockchip: add clock-ids for more rk3228 clocks clk: rockchip: add ids for camera on rk3399
This commit is contained in:
Stephen Boyd
commit
c96da4dd39
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@ -0,0 +1,56 @@
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* Rockchip RK3128 Clock and Reset Unit
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The RK3128 clock controller generates and supplies clock to various
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controllers within the SoC and also implements a reset controller for SoC
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peripherals.
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Required Properties:
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- compatible: should be "rockchip,rk3128-cru"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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- #reset-cells: should be 1.
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Optional Properties:
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- rockchip,grf: phandle to the syscon managing the "general register files"
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If missing pll rates are not changeable, due to the missing pll lock status.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be
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used in device tree sources. Similar macros exist for the reset sources in
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these files.
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External clocks:
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There are several clocks that are generated outside the SoC. It is expected
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that they are defined using standard clock bindings with following
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clock-output-names:
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- "xin24m" - crystal input - required,
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- "ext_i2s" - external I2S clock - optional,
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- "gmac_clkin" - external GMAC clock - optional
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Example: Clock controller node:
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cru: cru@20000000 {
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compatible = "rockchip,rk3128-cru";
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reg = <0x20000000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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Example: UART controller node that consumes the clock generated by the clock
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controller:
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uart2: serial@20068000 {
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compatible = "rockchip,serial";
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reg = <0x20068000 0x100>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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clock-names = "sclk_uart", "pclk_uart";
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};
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@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
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obj-y += clk-rv1108.o
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obj-y += clk-rk3036.o
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obj-y += clk-rk3128.o
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obj-y += clk-rk3188.o
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obj-y += clk-rk3228.o
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obj-y += clk-rk3288.o
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@ -436,6 +436,7 @@ static const char *const rk3036_critical_clocks[] __initconst = {
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"aclk_peri",
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"hclk_peri",
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"pclk_peri",
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"pclk_ddrupctl",
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};
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static void __init rk3036_clk_init(struct device_node *np)
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612
drivers/clk/rockchip/clk-rk3128.c
Normal file
612
drivers/clk/rockchip/clk-rk3128.c
Normal file
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@ -0,0 +1,612 @@
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/*
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* Copyright (c) 2017 Rockchip Electronics Co. Ltd.
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* Author: Elaine <zhangqing@rock-chips.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/syscore_ops.h>
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#include <dt-bindings/clock/rk3128-cru.h>
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#include "clk.h"
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#define RK3128_GRF_SOC_STATUS0 0x14c
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enum rk3128_plls {
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apll, dpll, cpll, gpll,
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};
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static struct rockchip_pll_rate_table rk3128_pll_rates[] = {
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/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
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RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
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RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
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RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
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RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
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RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
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RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
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RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
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RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
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RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
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RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
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RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
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RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
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RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
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RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
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RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
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RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
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RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
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RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
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RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
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RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
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RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
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RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
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RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
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RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
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RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
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RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
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RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
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RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
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RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
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RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
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RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
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RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
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RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
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RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
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RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
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RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
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RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
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RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
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RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
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RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
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RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
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RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
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{ /* sentinel */ },
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};
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#define RK3128_DIV_CPU_MASK 0x1f
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#define RK3128_DIV_CPU_SHIFT 8
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#define RK3128_DIV_PERI_MASK 0xf
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#define RK3128_DIV_PERI_SHIFT 0
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#define RK3128_DIV_ACLK_MASK 0x7
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#define RK3128_DIV_ACLK_SHIFT 4
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#define RK3128_DIV_HCLK_MASK 0x3
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#define RK3128_DIV_HCLK_SHIFT 8
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#define RK3128_DIV_PCLK_MASK 0x7
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#define RK3128_DIV_PCLK_SHIFT 12
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#define RK3128_CLKSEL1(_core_aclk_div, _pclk_dbg_div) \
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{ \
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.reg = RK2928_CLKSEL_CON(1), \
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.val = HIWORD_UPDATE(_pclk_dbg_div, RK3128_DIV_PERI_MASK, \
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RK3128_DIV_PERI_SHIFT) | \
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HIWORD_UPDATE(_core_aclk_div, RK3128_DIV_ACLK_MASK, \
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RK3128_DIV_ACLK_SHIFT), \
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}
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#define RK3128_CPUCLK_RATE(_prate, _core_aclk_div, _pclk_dbg_div) \
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{ \
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.prate = _prate, \
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.divs = { \
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RK3128_CLKSEL1(_core_aclk_div, _pclk_dbg_div), \
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}, \
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}
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static struct rockchip_cpuclk_rate_table rk3128_cpuclk_rates[] __initdata = {
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RK3128_CPUCLK_RATE(1800000000, 1, 7),
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RK3128_CPUCLK_RATE(1704000000, 1, 7),
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RK3128_CPUCLK_RATE(1608000000, 1, 7),
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RK3128_CPUCLK_RATE(1512000000, 1, 7),
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RK3128_CPUCLK_RATE(1488000000, 1, 5),
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RK3128_CPUCLK_RATE(1416000000, 1, 5),
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RK3128_CPUCLK_RATE(1392000000, 1, 5),
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RK3128_CPUCLK_RATE(1296000000, 1, 5),
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RK3128_CPUCLK_RATE(1200000000, 1, 5),
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RK3128_CPUCLK_RATE(1104000000, 1, 5),
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RK3128_CPUCLK_RATE(1008000000, 1, 5),
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RK3128_CPUCLK_RATE(912000000, 1, 5),
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RK3128_CPUCLK_RATE(816000000, 1, 3),
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RK3128_CPUCLK_RATE(696000000, 1, 3),
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RK3128_CPUCLK_RATE(600000000, 1, 3),
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RK3128_CPUCLK_RATE(408000000, 1, 1),
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RK3128_CPUCLK_RATE(312000000, 1, 1),
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RK3128_CPUCLK_RATE(216000000, 1, 1),
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RK3128_CPUCLK_RATE(96000000, 1, 1),
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};
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static const struct rockchip_cpuclk_reg_data rk3128_cpuclk_data = {
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.core_reg = RK2928_CLKSEL_CON(0),
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.div_core_shift = 0,
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.div_core_mask = 0x1f,
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.mux_core_alt = 1,
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.mux_core_main = 0,
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.mux_core_shift = 7,
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.mux_core_mask = 0x1,
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};
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PNAME(mux_pll_p) = { "clk_24m", "xin24m" };
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PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_div2_ddr" };
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PNAME(mux_armclk_p) = { "apll_core", "gpll_div2_core" };
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PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
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PNAME(mux_aclk_cpu_src_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3" };
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PNAME(mux_pll_src_5plls_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3", "usb480m" };
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PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "gpll_div2", "usb480m" };
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PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "gpll_div2" };
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PNAME(mux_aclk_peri_src_p) = { "gpll_peri", "cpll_peri", "gpll_div2_peri", "gpll_div3_peri" };
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PNAME(mux_mmc_src_p) = { "cpll", "gpll", "gpll_div2", "xin24m" };
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PNAME(mux_clk_cif_out_src_p) = { "clk_cif_src", "xin24m" };
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PNAME(mux_sclk_vop_src_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3" };
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PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
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PNAME(mux_i2s1_pre_p) = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" };
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PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" };
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PNAME(mux_sclk_spdif_p) = { "sclk_spdif_src", "spdif_frac", "xin12m" };
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PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
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PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
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PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
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PNAME(mux_sclk_gmac_p) = { "sclk_gmac_src", "gmac_clkin" };
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PNAME(mux_sclk_sfc_src_p) = { "cpll", "gpll", "gpll_div2", "xin24m" };
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static struct rockchip_pll_clock rk3128_pll_clks[] __initdata = {
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[apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
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RK2928_MODE_CON, 0, 1, 0, rk3128_pll_rates),
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[dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
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RK2928_MODE_CON, 4, 0, 0, NULL),
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[cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
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RK2928_MODE_CON, 8, 2, 0, rk3128_pll_rates),
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[gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
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RK2928_MODE_CON, 12, 3, ROCKCHIP_PLL_SYNC_RATE, rk3128_pll_rates),
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};
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#define MFLAGS CLK_MUX_HIWORD_MASK
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#define DFLAGS CLK_DIVIDER_HIWORD_MASK
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#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
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static struct rockchip_clk_branch rk3128_i2s0_fracmux __initdata =
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MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(9), 8, 2, MFLAGS);
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static struct rockchip_clk_branch rk3128_i2s1_fracmux __initdata =
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MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
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static struct rockchip_clk_branch rk3128_spdif_fracmux __initdata =
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MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(6), 8, 2, MFLAGS);
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static struct rockchip_clk_branch rk3128_uart0_fracmux __initdata =
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MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
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static struct rockchip_clk_branch rk3128_uart1_fracmux __initdata =
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MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
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static struct rockchip_clk_branch rk3128_uart2_fracmux __initdata =
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MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
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static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
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/*
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* Clock-Architecture Diagram 1
|
||||
*/
|
||||
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FACTOR(PLL_GPLL_DIV2, "gpll_div2", "gpll", 0, 1, 2),
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FACTOR(PLL_GPLL_DIV3, "gpll_div3", "gpll", 0, 1, 3),
|
||||
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DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
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RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
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/* PD_DDR */
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GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
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RK2928_CLKGATE_CON(0), 2, GFLAGS),
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GATE(0, "gpll_div2_ddr", "gpll_div2", CLK_IGNORE_UNUSED,
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RK2928_CLKGATE_CON(0), 2, GFLAGS),
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COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
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RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
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FACTOR(SCLK_DDRC, "clk_ddrc", "ddrphy2x", 0, 1, 2),
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FACTOR(0, "clk_ddrphy", "ddrphy2x", 0, 1, 2),
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/* PD_CORE */
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GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
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RK2928_CLKGATE_CON(0), 6, GFLAGS),
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GATE(0, "gpll_div2_core", "gpll_div2", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(0), 6, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
|
||||
RK2928_CLKGATE_CON(0), 0, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
|
||||
RK2928_CLKGATE_CON(0), 7, GFLAGS),
|
||||
|
||||
/* PD_MISC */
|
||||
MUX(SCLK_USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
|
||||
RK2928_MISC_CON, 15, 1, MFLAGS),
|
||||
|
||||
/* PD_CPU */
|
||||
COMPOSITE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
|
||||
RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(0), 1, GFLAGS),
|
||||
GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0,
|
||||
RK2928_CLKGATE_CON(0), 3, GFLAGS),
|
||||
COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", 0,
|
||||
RK2928_CLKSEL_CON(1), 8, 2, DFLAGS,
|
||||
RK2928_CLKGATE_CON(0), 4, GFLAGS),
|
||||
COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_src", 0,
|
||||
RK2928_CLKSEL_CON(1), 12, 2, DFLAGS,
|
||||
RK2928_CLKGATE_CON(0), 5, GFLAGS),
|
||||
COMPOSITE_NOMUX(SCLK_CRYPTO, "clk_crypto", "aclk_cpu_src", 0,
|
||||
RK2928_CLKSEL_CON(24), 0, 2, DFLAGS,
|
||||
RK2928_CLKGATE_CON(0), 12, GFLAGS),
|
||||
|
||||
/* PD_VIDEO */
|
||||
COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_5plls_p, 0,
|
||||
RK2928_CLKSEL_CON(32), 5, 3, MFLAGS, 0, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 9, GFLAGS),
|
||||
FACTOR(HCLK_VEPU, "hclk_vepu", "aclk_vepu", 0, 1, 4),
|
||||
|
||||
COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_5plls_p, 0,
|
||||
RK2928_CLKSEL_CON(32), 13, 3, MFLAGS, 8, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 11, GFLAGS),
|
||||
FACTOR_GATE(HCLK_VDPU, "hclk_vdpu", "aclk_vdpu", 0, 1, 4,
|
||||
RK2928_CLKGATE_CON(3), 12, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_5plls_p, 0,
|
||||
RK2928_CLKSEL_CON(34), 13, 3, MFLAGS, 8, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 10, GFLAGS),
|
||||
|
||||
/* PD_VIO */
|
||||
COMPOSITE(ACLK_VIO0, "aclk_vio0", mux_pll_src_5plls_p, 0,
|
||||
RK2928_CLKSEL_CON(31), 5, 3, MFLAGS, 0, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 0, GFLAGS),
|
||||
COMPOSITE(ACLK_VIO1, "aclk_vio1", mux_pll_src_5plls_p, 0,
|
||||
RK2928_CLKSEL_CON(31), 13, 3, MFLAGS, 8, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 4, GFLAGS),
|
||||
COMPOSITE(HCLK_VIO, "hclk_vio", mux_pll_src_4plls_p, 0,
|
||||
RK2928_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(0), 11, GFLAGS),
|
||||
|
||||
/* PD_PERI */
|
||||
GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(2), 0, GFLAGS),
|
||||
GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(2), 0, GFLAGS),
|
||||
GATE(0, "gpll_div2_peri", "gpll_div2", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(2), 0, GFLAGS),
|
||||
GATE(0, "gpll_div3_peri", "gpll_div3", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(2), 0, GFLAGS),
|
||||
COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0,
|
||||
RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS),
|
||||
COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
|
||||
RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
|
||||
RK2928_CLKGATE_CON(2), 3, GFLAGS),
|
||||
COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,
|
||||
RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
|
||||
RK2928_CLKGATE_CON(2), 2, GFLAGS),
|
||||
GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
|
||||
RK2928_CLKGATE_CON(2), 1, GFLAGS),
|
||||
|
||||
GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
|
||||
RK2928_CLKGATE_CON(10), 3, GFLAGS),
|
||||
GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
|
||||
RK2928_CLKGATE_CON(10), 4, GFLAGS),
|
||||
GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
|
||||
RK2928_CLKGATE_CON(10), 5, GFLAGS),
|
||||
GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
|
||||
RK2928_CLKGATE_CON(10), 6, GFLAGS),
|
||||
GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
|
||||
RK2928_CLKGATE_CON(10), 7, GFLAGS),
|
||||
GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
|
||||
RK2928_CLKGATE_CON(10), 8, GFLAGS),
|
||||
|
||||
GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
|
||||
RK2928_CLKGATE_CON(10), 8, GFLAGS),
|
||||
GATE(SCLK_PVTM_GPU, "clk_pvtm_gpu", "xin24m", 0,
|
||||
RK2928_CLKGATE_CON(10), 8, GFLAGS),
|
||||
GATE(SCLK_PVTM_FUNC, "clk_pvtm_func", "xin24m", 0,
|
||||
RK2928_CLKGATE_CON(10), 8, GFLAGS),
|
||||
GATE(SCLK_MIPI_24M, "clk_mipi_24m", "xin24m", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(10), 8, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,
|
||||
RK2928_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 11, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_SDIO, "sclk_sdio", mux_mmc_src_p, 0,
|
||||
RK2928_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 6, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 13, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
|
||||
RK2928_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 14, GFLAGS),
|
||||
|
||||
DIV(SCLK_PVTM, "clk_pvtm", "clk_pvtm_func", 0,
|
||||
RK2928_CLKSEL_CON(2), 0, 7, DFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 2
|
||||
*/
|
||||
COMPOSITE(DCLK_VOP, "dclk_vop", mux_sclk_vop_src_p, 0,
|
||||
RK2928_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 1, GFLAGS),
|
||||
COMPOSITE(SCLK_VOP, "sclk_vop", mux_sclk_vop_src_p, 0,
|
||||
RK2928_CLKSEL_CON(28), 0, 2, MFLAGS, 8, 8, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 2, GFLAGS),
|
||||
COMPOSITE(DCLK_EBC, "dclk_ebc", mux_pll_src_3plls_p, 0,
|
||||
RK2928_CLKSEL_CON(23), 0, 2, MFLAGS, 8, 8, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 4, GFLAGS),
|
||||
|
||||
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
|
||||
|
||||
COMPOSITE_NODIV(SCLK_CIF_SRC, "sclk_cif_src", mux_pll_src_4plls_p, 0,
|
||||
RK2928_CLKSEL_CON(29), 0, 2, MFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 7, GFLAGS),
|
||||
MUX(SCLK_CIF_OUT_SRC, "sclk_cif_out_src", mux_clk_cif_out_src_p, 0,
|
||||
RK2928_CLKSEL_CON(13), 14, 2, MFLAGS),
|
||||
DIV(SCLK_CIF_OUT, "sclk_cif_out", "sclk_cif_out_src", 0,
|
||||
RK2928_CLKSEL_CON(29), 2, 5, DFLAGS),
|
||||
|
||||
COMPOSITE(0, "i2s0_src", mux_pll_src_3plls_p, 0,
|
||||
RK2928_CLKSEL_CON(9), 14, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(4), 4, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(8), 0,
|
||||
RK2928_CLKGATE_CON(4), 5, GFLAGS,
|
||||
&rk3128_i2s0_fracmux),
|
||||
GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKGATE_CON(4), 6, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "i2s1_src", mux_pll_src_3plls_p, 0,
|
||||
RK2928_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(0), 9, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(7), 0,
|
||||
RK2928_CLKGATE_CON(0), 10, GFLAGS,
|
||||
&rk3128_i2s1_fracmux),
|
||||
GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKGATE_CON(0), 14, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0,
|
||||
RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
|
||||
RK2928_CLKGATE_CON(0), 13, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "sclk_spdif_src", mux_pll_src_3plls_p, 0,
|
||||
RK2928_CLKSEL_CON(6), 14, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 10, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(20), 0,
|
||||
RK2928_CLKGATE_CON(2), 12, GFLAGS,
|
||||
&rk3128_spdif_fracmux),
|
||||
|
||||
GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(1), 3, GFLAGS),
|
||||
|
||||
GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", 0,
|
||||
RK2928_CLKGATE_CON(1), 5, GFLAGS),
|
||||
GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin12m", 0,
|
||||
RK2928_CLKGATE_CON(1), 6, GFLAGS),
|
||||
|
||||
COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
|
||||
RK2928_CLKSEL_CON(24), 8, 8, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 8, GFLAGS),
|
||||
|
||||
COMPOSITE(ACLK_GPU, "aclk_gpu", mux_pll_src_5plls_p, 0,
|
||||
RK2928_CLKSEL_CON(34), 5, 3, MFLAGS, 0, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 13, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_3plls_p, 0,
|
||||
RK2928_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 9, GFLAGS),
|
||||
|
||||
/* PD_UART */
|
||||
COMPOSITE(0, "uart0_src", mux_pll_src_4plls_p, 0,
|
||||
RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 8, GFLAGS),
|
||||
MUX(0, "uart12_src", mux_pll_src_4plls_p, 0,
|
||||
RK2928_CLKSEL_CON(13), 14, 2, MFLAGS),
|
||||
COMPOSITE_NOMUX(0, "uart1_src", "uart12_src", 0,
|
||||
RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 10, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "uart2_src", "uart12_src", 0,
|
||||
RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 13, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(17), 0,
|
||||
RK2928_CLKGATE_CON(1), 9, GFLAGS,
|
||||
&rk3128_uart0_fracmux),
|
||||
COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(18), 0,
|
||||
RK2928_CLKGATE_CON(1), 11, GFLAGS,
|
||||
&rk3128_uart1_fracmux),
|
||||
COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(19), 0,
|
||||
RK2928_CLKGATE_CON(1), 13, GFLAGS,
|
||||
&rk3128_uart2_fracmux),
|
||||
|
||||
COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_3plls_p, 0,
|
||||
RK2928_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 7, GFLAGS),
|
||||
MUX(SCLK_MAC, "sclk_gmac", mux_sclk_gmac_p, 0,
|
||||
RK2928_CLKSEL_CON(5), 15, 1, MFLAGS),
|
||||
GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_gmac", 0,
|
||||
RK2928_CLKGATE_CON(2), 5, GFLAGS),
|
||||
GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_gmac", 0,
|
||||
RK2928_CLKGATE_CON(2), 4, GFLAGS),
|
||||
GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_gmac", 0,
|
||||
RK2928_CLKGATE_CON(2), 6, GFLAGS),
|
||||
GATE(SCLK_MAC_TX, "sclk_mac_tx", "sclk_gmac", 0,
|
||||
RK2928_CLKGATE_CON(2), 7, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_3plls_p, 0,
|
||||
RK2928_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 14, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0,
|
||||
RK2928_CLKSEL_CON(2), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(10), 15, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_SFC, "sclk_sfc", mux_sclk_sfc_src_p, 0,
|
||||
RK2928_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 15, GFLAGS),
|
||||
|
||||
COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "cpll", 0,
|
||||
RK2928_CLKSEL_CON(29), 8, 6, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 0, GFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 3
|
||||
*/
|
||||
|
||||
/* PD_VOP */
|
||||
GATE(ACLK_LCDC0, "aclk_lcdc0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 0, GFLAGS),
|
||||
GATE(ACLK_CIF, "aclk_cif", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 5, GFLAGS),
|
||||
GATE(ACLK_RGA, "aclk_rga", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 11, GFLAGS),
|
||||
GATE(0, "aclk_vio0_niu", "aclk_vio0", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 13, GFLAGS),
|
||||
|
||||
GATE(ACLK_IEP, "aclk_iep", "aclk_vio1", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS),
|
||||
GATE(0, "aclk_vio1_niu", "aclk_vio1", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 10, GFLAGS),
|
||||
|
||||
GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
|
||||
GATE(PCLK_MIPI, "pclk_mipi", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
|
||||
GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),
|
||||
GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_vio", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS),
|
||||
GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS),
|
||||
GATE(0, "hclk_vio_niu", "hclk_vio", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 12, GFLAGS),
|
||||
GATE(HCLK_CIF, "hclk_cif", "hclk_vio", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS),
|
||||
GATE(HCLK_EBC, "hclk_ebc", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 9, GFLAGS),
|
||||
|
||||
/* PD_PERI */
|
||||
GATE(0, "aclk_peri_axi", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS),
|
||||
GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(10), 10, GFLAGS),
|
||||
GATE(ACLK_DMAC, "aclk_dmac", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
|
||||
GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 15, GFLAGS),
|
||||
GATE(0, "aclk_cpu_to_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
|
||||
GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
|
||||
|
||||
GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
|
||||
GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
|
||||
GATE(HCLK_I2S_2CH, "hclk_i2s_2ch", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
|
||||
GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 13, GFLAGS),
|
||||
GATE(HCLK_HOST2, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
|
||||
GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 13, GFLAGS),
|
||||
GATE(0, "hclk_peri_ahb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 14, GFLAGS),
|
||||
GATE(HCLK_SPDIF, "hclk_spdif", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
|
||||
GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 12, GFLAGS),
|
||||
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
|
||||
GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS),
|
||||
GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
|
||||
GATE(0, "hclk_emmc_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 6, GFLAGS),
|
||||
GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
|
||||
GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 14, GFLAGS),
|
||||
|
||||
GATE(PCLK_SIM_CARD, "pclk_sim_card", "pclk_peri", 0, RK2928_CLKGATE_CON(9), 12, GFLAGS),
|
||||
GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS),
|
||||
GATE(0, "pclk_peri_axi", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
|
||||
GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
|
||||
GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
|
||||
GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
|
||||
GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
|
||||
GATE(PCLK_PWM, "pclk_pwm", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
|
||||
GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
|
||||
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
|
||||
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS),
|
||||
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
|
||||
GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
|
||||
GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS),
|
||||
GATE(PCLK_EFUSE, "pclk_efuse", "pclk_peri", 0, RK2928_CLKGATE_CON(5), 2, GFLAGS),
|
||||
GATE(PCLK_TIMER, "pclk_timer", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 7, GFLAGS),
|
||||
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
|
||||
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
|
||||
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
|
||||
GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
|
||||
|
||||
/* PD_BUS */
|
||||
GATE(0, "aclk_initmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS),
|
||||
GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS),
|
||||
|
||||
GATE(0, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 6, GFLAGS),
|
||||
GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
|
||||
|
||||
GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
|
||||
GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
|
||||
GATE(0, "pclk_ddrupctl", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 7, GFLAGS),
|
||||
GATE(0, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
|
||||
GATE(0, "pclk_mipiphy", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 0, GFLAGS),
|
||||
|
||||
GATE(0, "pclk_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 2, GFLAGS),
|
||||
GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 3, GFLAGS),
|
||||
|
||||
/* PD_MMC */
|
||||
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
|
||||
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 0),
|
||||
|
||||
MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1),
|
||||
MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 0),
|
||||
|
||||
MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1),
|
||||
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 0),
|
||||
};
|
||||
|
||||
static const char *const rk3128_critical_clocks[] __initconst = {
|
||||
"aclk_cpu",
|
||||
"hclk_cpu",
|
||||
"pclk_cpu",
|
||||
"aclk_peri",
|
||||
"hclk_peri",
|
||||
"pclk_peri",
|
||||
};
|
||||
|
||||
static void __init rk3128_clk_init(struct device_node *np)
|
||||
{
|
||||
struct rockchip_clk_provider *ctx;
|
||||
void __iomem *reg_base;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base) {
|
||||
pr_err("%s: could not map cru region\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
|
||||
if (IS_ERR(ctx)) {
|
||||
pr_err("%s: rockchip clk init failed\n", __func__);
|
||||
iounmap(reg_base);
|
||||
return;
|
||||
}
|
||||
|
||||
rockchip_clk_register_plls(ctx, rk3128_pll_clks,
|
||||
ARRAY_SIZE(rk3128_pll_clks),
|
||||
RK3128_GRF_SOC_STATUS0);
|
||||
rockchip_clk_register_branches(ctx, rk3128_clk_branches,
|
||||
ARRAY_SIZE(rk3128_clk_branches));
|
||||
rockchip_clk_protect_critical(rk3128_critical_clocks,
|
||||
ARRAY_SIZE(rk3128_critical_clocks));
|
||||
|
||||
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
|
||||
mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
|
||||
&rk3128_cpuclk_data, rk3128_cpuclk_rates,
|
||||
ARRAY_SIZE(rk3128_cpuclk_rates));
|
||||
|
||||
rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
|
||||
ROCKCHIP_SOFTRST_HIWORD_MASK);
|
||||
|
||||
rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);
|
||||
|
||||
rockchip_clk_of_add_provider(np, ctx);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(rk3128_cru, "rockchip,rk3128-cru", rk3128_clk_init);
|
||||
|
|
@ -86,25 +86,43 @@ static struct rockchip_pll_rate_table rk3228_pll_rates[] = {
|
|||
#define RK3228_DIV_PCLK_MASK 0x7
|
||||
#define RK3228_DIV_PCLK_SHIFT 12
|
||||
|
||||
#define RK3228_CLKSEL1(_core_peri_div) \
|
||||
#define RK3228_CLKSEL1(_core_aclk_div, _core_peri_div) \
|
||||
{ \
|
||||
.reg = RK2928_CLKSEL_CON(1), \
|
||||
.val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \
|
||||
RK3228_DIV_PERI_SHIFT) \
|
||||
}
|
||||
RK3228_DIV_PERI_SHIFT) | \
|
||||
HIWORD_UPDATE(_core_aclk_div, RK3228_DIV_ACLK_MASK, \
|
||||
RK3228_DIV_ACLK_SHIFT), \
|
||||
}
|
||||
|
||||
#define RK3228_CPUCLK_RATE(_prate, _core_peri_div) \
|
||||
{ \
|
||||
.prate = _prate, \
|
||||
.divs = { \
|
||||
RK3228_CLKSEL1(_core_peri_div), \
|
||||
}, \
|
||||
#define RK3228_CPUCLK_RATE(_prate, _core_aclk_div, _core_peri_div) \
|
||||
{ \
|
||||
.prate = _prate, \
|
||||
.divs = { \
|
||||
RK3228_CLKSEL1(_core_aclk_div, _core_peri_div), \
|
||||
}, \
|
||||
}
|
||||
|
||||
static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = {
|
||||
RK3228_CPUCLK_RATE(816000000, 4),
|
||||
RK3228_CPUCLK_RATE(600000000, 4),
|
||||
RK3228_CPUCLK_RATE(312000000, 4),
|
||||
RK3228_CPUCLK_RATE(1800000000, 1, 7),
|
||||
RK3228_CPUCLK_RATE(1704000000, 1, 7),
|
||||
RK3228_CPUCLK_RATE(1608000000, 1, 7),
|
||||
RK3228_CPUCLK_RATE(1512000000, 1, 7),
|
||||
RK3228_CPUCLK_RATE(1488000000, 1, 5),
|
||||
RK3228_CPUCLK_RATE(1416000000, 1, 5),
|
||||
RK3228_CPUCLK_RATE(1392000000, 1, 5),
|
||||
RK3228_CPUCLK_RATE(1296000000, 1, 5),
|
||||
RK3228_CPUCLK_RATE(1200000000, 1, 5),
|
||||
RK3228_CPUCLK_RATE(1104000000, 1, 5),
|
||||
RK3228_CPUCLK_RATE(1008000000, 1, 5),
|
||||
RK3228_CPUCLK_RATE(912000000, 1, 5),
|
||||
RK3228_CPUCLK_RATE(816000000, 1, 3),
|
||||
RK3228_CPUCLK_RATE(696000000, 1, 3),
|
||||
RK3228_CPUCLK_RATE(600000000, 1, 3),
|
||||
RK3228_CPUCLK_RATE(408000000, 1, 1),
|
||||
RK3228_CPUCLK_RATE(312000000, 1, 1),
|
||||
RK3228_CPUCLK_RATE(216000000, 1, 1),
|
||||
RK3228_CPUCLK_RATE(96000000, 1, 1),
|
||||
};
|
||||
|
||||
static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = {
|
||||
|
|
@ -252,15 +270,15 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
|||
RK2928_CLKGATE_CON(0), 1, GFLAGS),
|
||||
COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
|
||||
RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS),
|
||||
GATE(ARMCLK, "aclk_cpu", "aclk_cpu_src", 0,
|
||||
GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0,
|
||||
RK2928_CLKGATE_CON(6), 0, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "hclk_cpu", "aclk_cpu_src", 0,
|
||||
COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", 0,
|
||||
RK2928_CLKSEL_CON(1), 8, 2, DFLAGS,
|
||||
RK2928_CLKGATE_CON(6), 1, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", 0,
|
||||
RK2928_CLKSEL_CON(1), 12, 3, DFLAGS,
|
||||
RK2928_CLKGATE_CON(6), 2, GFLAGS),
|
||||
GATE(0, "pclk_cpu", "pclk_bus_src", 0,
|
||||
GATE(PCLK_CPU, "pclk_cpu", "pclk_bus_src", 0,
|
||||
RK2928_CLKGATE_CON(6), 3, GFLAGS),
|
||||
GATE(0, "pclk_phy_pre", "pclk_bus_src", 0,
|
||||
RK2928_CLKGATE_CON(6), 4, GFLAGS),
|
||||
|
|
@ -268,58 +286,58 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
|||
RK2928_CLKGATE_CON(6), 13, GFLAGS),
|
||||
|
||||
/* PD_VIDEO */
|
||||
COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,
|
||||
COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,
|
||||
RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 11, GFLAGS),
|
||||
FACTOR_GATE(0, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4,
|
||||
FACTOR_GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4,
|
||||
RK2928_CLKGATE_CON(4), 4, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,
|
||||
COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,
|
||||
RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 2, GFLAGS),
|
||||
FACTOR_GATE(0, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4,
|
||||
FACTOR_GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4,
|
||||
RK2928_CLKGATE_CON(4), 5, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0,
|
||||
COMPOSITE(SCLK_VDEC_CABAC, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0,
|
||||
RK2928_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 3, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "sclk_vdec_core", mux_pll_src_4plls_p, 0,
|
||||
COMPOSITE(SCLK_VDEC_CORE, "sclk_vdec_core", mux_pll_src_4plls_p, 0,
|
||||
RK2928_CLKSEL_CON(34), 13, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 4, GFLAGS),
|
||||
|
||||
/* PD_VIO */
|
||||
COMPOSITE(0, "aclk_iep_pre", mux_pll_src_4plls_p, 0,
|
||||
COMPOSITE(ACLK_IEP_PRE, "aclk_iep_pre", mux_pll_src_4plls_p, 0,
|
||||
RK2928_CLKSEL_CON(31), 5, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 0, GFLAGS),
|
||||
DIV(0, "hclk_vio_pre", "aclk_iep_pre", 0,
|
||||
DIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_iep_pre", 0,
|
||||
RK2928_CLKSEL_CON(2), 0, 5, DFLAGS),
|
||||
|
||||
COMPOSITE(0, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0,
|
||||
COMPOSITE(ACLK_HDCP_PRE, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0,
|
||||
RK2928_CLKSEL_CON(31), 13, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 4, GFLAGS),
|
||||
|
||||
MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, 0,
|
||||
RK2928_CLKSEL_CON(33), 13, 2, MFLAGS),
|
||||
COMPOSITE_NOMUX(0, "aclk_rga_pre", "sclk_rga_src", 0,
|
||||
COMPOSITE_NOMUX(ACLK_RGA_PRE, "aclk_rga_pre", "sclk_rga_src", 0,
|
||||
RK2928_CLKSEL_CON(33), 8, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 2, GFLAGS),
|
||||
COMPOSITE(0, "sclk_rga", mux_sclk_rga_p, 0,
|
||||
COMPOSITE(SCLK_RGA, "sclk_rga", mux_sclk_rga_p, 0,
|
||||
RK2928_CLKSEL_CON(22), 5, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 6, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "aclk_vop_pre", mux_pll_src_4plls_p, 0,
|
||||
COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", mux_pll_src_4plls_p, 0,
|
||||
RK2928_CLKSEL_CON(33), 5, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 1, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "sclk_hdcp", mux_pll_src_3plls_p, 0,
|
||||
COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_3plls_p, 0,
|
||||
RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 6, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 5, GFLAGS),
|
||||
|
||||
GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
|
||||
RK2928_CLKGATE_CON(3), 7, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0,
|
||||
COMPOSITE(SCLK_HDMI_CEC, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0,
|
||||
RK2928_CLKSEL_CON(21), 14, 2, MFLAGS, 0, 14, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 8, GFLAGS),
|
||||
|
||||
|
|
@ -354,18 +372,18 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
|||
GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
|
||||
RK2928_CLKGATE_CON(6), 10, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "sclk_crypto", mux_pll_src_2plls_p, 0,
|
||||
COMPOSITE(SCLK_CRYPTO, "sclk_crypto", mux_pll_src_2plls_p, 0,
|
||||
RK2928_CLKSEL_CON(24), 5, 1, MFLAGS, 0, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 7, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "sclk_tsp", mux_pll_src_2plls_p, 0,
|
||||
COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_2plls_p, 0,
|
||||
RK2928_CLKSEL_CON(22), 15, 1, MFLAGS, 8, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 6, GFLAGS),
|
||||
|
||||
GATE(0, "sclk_hsadc", "ext_hsadc", 0,
|
||||
GATE(SCLK_HSADC, "sclk_hsadc", "ext_hsadc", 0,
|
||||
RK2928_CLKGATE_CON(10), 12, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
|
||||
COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
|
||||
RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 15, GFLAGS),
|
||||
|
||||
|
|
@ -445,12 +463,12 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
|||
RK2928_CLKGATE_CON(2), 12, GFLAGS,
|
||||
&rk3228_spdif_fracmux),
|
||||
|
||||
GATE(0, "jtag", "ext_jtag", 0,
|
||||
GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(1), 3, GFLAGS),
|
||||
|
||||
GATE(0, "sclk_otgphy0", "xin24m", 0,
|
||||
GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", 0,
|
||||
RK2928_CLKGATE_CON(1), 5, GFLAGS),
|
||||
GATE(0, "sclk_otgphy1", "xin24m", 0,
|
||||
GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", 0,
|
||||
RK2928_CLKGATE_CON(1), 6, GFLAGS),
|
||||
|
||||
COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,
|
||||
|
|
@ -526,28 +544,28 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
|||
*/
|
||||
|
||||
/* PD_VOP */
|
||||
GATE(0, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS),
|
||||
GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS),
|
||||
GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 11, GFLAGS),
|
||||
GATE(0, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),
|
||||
GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),
|
||||
GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 9, GFLAGS),
|
||||
|
||||
GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),
|
||||
GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 12, GFLAGS),
|
||||
|
||||
GATE(0, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),
|
||||
GATE(ACLK_HDCP, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),
|
||||
GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(13), 10, GFLAGS),
|
||||
|
||||
GATE(0, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),
|
||||
GATE(0, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),
|
||||
GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),
|
||||
GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),
|
||||
GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),
|
||||
GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 7, GFLAGS),
|
||||
GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 8, GFLAGS),
|
||||
GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS),
|
||||
GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS),
|
||||
GATE(0, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS),
|
||||
GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS),
|
||||
GATE(HCLK_HDCP_MMU, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS),
|
||||
GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS),
|
||||
GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS),
|
||||
GATE(0, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS),
|
||||
GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS),
|
||||
GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS),
|
||||
|
||||
/* PD_PERI */
|
||||
GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 0, GFLAGS),
|
||||
|
|
@ -557,12 +575,12 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
|||
GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 1, GFLAGS),
|
||||
GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 2, GFLAGS),
|
||||
GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS),
|
||||
GATE(0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS),
|
||||
GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS),
|
||||
GATE(0, "hclk_host0_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 7, GFLAGS),
|
||||
GATE(0, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS),
|
||||
GATE(HCLK_HOST1, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS),
|
||||
GATE(0, "hclk_host1_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 9, GFLAGS),
|
||||
GATE(0, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS),
|
||||
GATE(0, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS),
|
||||
GATE(HCLK_HOST2, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS),
|
||||
GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS),
|
||||
GATE(0, "hclk_otg_pmu", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 13, GFLAGS),
|
||||
GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS),
|
||||
GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS),
|
||||
|
|
@ -571,7 +589,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
|||
GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 2, GFLAGS),
|
||||
|
||||
/* PD_GPU */
|
||||
GATE(0, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 14, GFLAGS),
|
||||
GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 14, GFLAGS),
|
||||
GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 15, GFLAGS),
|
||||
|
||||
/* PD_BUS */
|
||||
|
|
@ -585,16 +603,16 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
|||
GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
|
||||
GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
|
||||
GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
|
||||
GATE(0, "hclk_tsp", "hclk_cpu", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS),
|
||||
GATE(0, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
|
||||
GATE(0, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
|
||||
GATE(HCLK_TSP, "hclk_tsp", "hclk_cpu", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS),
|
||||
GATE(HCLK_M_CRYPTO, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
|
||||
GATE(HCLK_S_CRYPTO, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
|
||||
|
||||
GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
|
||||
GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
|
||||
GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS),
|
||||
|
||||
GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
|
||||
GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS),
|
||||
GATE(PCLK_EFUSE_1024, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
|
||||
GATE(PCLK_EFUSE_256, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS),
|
||||
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
|
||||
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),
|
||||
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
|
||||
|
|
@ -622,13 +640,13 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
|||
GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
|
||||
GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
|
||||
|
||||
GATE(0, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS),
|
||||
GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS),
|
||||
GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 4, GFLAGS),
|
||||
GATE(0, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS),
|
||||
GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS),
|
||||
GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 6, GFLAGS),
|
||||
GATE(0, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS),
|
||||
GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS),
|
||||
GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 5, GFLAGS),
|
||||
GATE(0, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS),
|
||||
GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS),
|
||||
GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 7, GFLAGS),
|
||||
|
||||
/* PD_MMC */
|
||||
|
|
@ -644,9 +662,37 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
|||
|
||||
static const char *const rk3228_critical_clocks[] __initconst = {
|
||||
"aclk_cpu",
|
||||
"pclk_cpu",
|
||||
"hclk_cpu",
|
||||
"aclk_peri",
|
||||
"hclk_peri",
|
||||
"pclk_peri",
|
||||
"aclk_rga_noc",
|
||||
"aclk_iep_noc",
|
||||
"aclk_vop_noc",
|
||||
"aclk_hdcp_noc",
|
||||
"hclk_vio_ahb_arbi",
|
||||
"hclk_vio_noc",
|
||||
"hclk_vop_noc",
|
||||
"hclk_host0_arb",
|
||||
"hclk_host1_arb",
|
||||
"hclk_host2_arb",
|
||||
"hclk_otg_pmu",
|
||||
"aclk_gpu_noc",
|
||||
"sclk_initmem_mbist",
|
||||
"aclk_initmem",
|
||||
"hclk_rom",
|
||||
"pclk_ddrupctl",
|
||||
"pclk_ddrmon",
|
||||
"pclk_msch_noc",
|
||||
"pclk_stimer",
|
||||
"pclk_ddrphy",
|
||||
"pclk_acodecphy",
|
||||
"pclk_phy_noc",
|
||||
"aclk_vpu_noc",
|
||||
"aclk_rkvdec_noc",
|
||||
"hclk_vpu_noc",
|
||||
"hclk_rkvdec_noc",
|
||||
};
|
||||
|
||||
static void __init rk3228_clk_init(struct device_node *np)
|
||||
|
|
|
|||
|
|
@ -292,13 +292,13 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
|
|||
COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED,
|
||||
RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
|
||||
RK3288_CLKGATE_CON(12), 6, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "atclk", "armclk", 0,
|
||||
COMPOSITE_NOMUX(0, "atclk", "armclk", CLK_IGNORE_UNUSED,
|
||||
RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
|
||||
RK3288_CLKGATE_CON(12), 7, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED,
|
||||
RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
|
||||
RK3288_CLKGATE_CON(12), 8, GFLAGS),
|
||||
GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
|
||||
GATE(0, "pclk_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
|
||||
RK3288_CLKGATE_CON(12), 9, GFLAGS),
|
||||
GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
|
||||
RK3288_CLKGATE_CON(12), 10, GFLAGS),
|
||||
|
|
@ -626,7 +626,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
|
|||
INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
|
||||
RK3288_CLKSEL_CON(22), 7, IFLAGS),
|
||||
|
||||
GATE(0, "jtag", "ext_jtag", 0,
|
||||
GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
|
||||
RK3288_CLKGATE_CON(4), 14, GFLAGS),
|
||||
|
||||
COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0,
|
||||
|
|
@ -635,7 +635,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
|
|||
COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
|
||||
RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
|
||||
RK3288_CLKGATE_CON(3), 6, GFLAGS),
|
||||
GATE(0, "hsicphy12m_xin12m", "xin12m", 0,
|
||||
GATE(0, "hsicphy12m_xin12m", "xin12m", CLK_IGNORE_UNUSED,
|
||||
RK3288_CLKGATE_CON(13), 9, GFLAGS),
|
||||
DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0,
|
||||
RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),
|
||||
|
|
@ -816,6 +816,12 @@ static const char *const rk3288_critical_clocks[] __initconst = {
|
|||
"pclk_alive_niu",
|
||||
"pclk_pd_pmu",
|
||||
"pclk_pmu_niu",
|
||||
"pclk_core_niu",
|
||||
"pclk_ddrupctl0",
|
||||
"pclk_publ0",
|
||||
"pclk_ddrupctl1",
|
||||
"pclk_publ1",
|
||||
"pmu_hclk_otg0",
|
||||
};
|
||||
|
||||
static void __iomem *rk3288_cru_base;
|
||||
|
|
|
|||
|
|
@ -638,7 +638,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
|
|||
GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,
|
||||
RK3368_CLKGATE_CON(7), 5, GFLAGS),
|
||||
|
||||
GATE(0, "jtag", "ext_jtag", 0,
|
||||
GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
|
||||
RK3368_CLKGATE_CON(7), 0, GFLAGS),
|
||||
|
||||
COMPOSITE_NODIV(0, "hsic_usbphy_480m", mux_hsic_usbphy480m_p, 0,
|
||||
|
|
@ -861,6 +861,9 @@ static const char *const rk3368_critical_clocks[] __initconst = {
|
|||
"pclk_pd_alive",
|
||||
"pclk_peri",
|
||||
"hclk_peri",
|
||||
"pclk_ddrphy",
|
||||
"pclk_ddrupctl",
|
||||
"pmu_hclk_otg0",
|
||||
};
|
||||
|
||||
static void __init rk3368_clk_init(struct device_node *np)
|
||||
|
|
|
|||
|
|
@ -1066,13 +1066,13 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
|
|||
/* cif_testout */
|
||||
MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
|
||||
RK3399_CLKSEL_CON(38), 6, 2, MFLAGS),
|
||||
COMPOSITE(0, "clk_testout1", mux_clk_testout1_p, 0,
|
||||
COMPOSITE(SCLK_TESTCLKOUT1, "clk_testout1", mux_clk_testout1_p, 0,
|
||||
RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3399_CLKGATE_CON(13), 14, GFLAGS),
|
||||
|
||||
MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
|
||||
RK3399_CLKSEL_CON(38), 14, 2, MFLAGS),
|
||||
COMPOSITE(0, "clk_testout2", mux_clk_testout2_p, 0,
|
||||
COMPOSITE(SCLK_TESTCLKOUT2, "clk_testout2", mux_clk_testout2_p, 0,
|
||||
RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS,
|
||||
RK3399_CLKGATE_CON(13), 15, GFLAGS),
|
||||
|
||||
|
|
|
|||
282
include/dt-bindings/clock/rk3128-cru.h
Normal file
282
include/dt-bindings/clock/rk3128-cru.h
Normal file
|
|
@ -0,0 +1,282 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Rockchip Electronics Co. Ltd.
|
||||
* Author: Elaine <zhangqing@rock-chips.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
|
||||
|
||||
/* core clocks */
|
||||
#define PLL_APLL 1
|
||||
#define PLL_DPLL 2
|
||||
#define PLL_CPLL 3
|
||||
#define PLL_GPLL 4
|
||||
#define ARMCLK 5
|
||||
#define PLL_GPLL_DIV2 6
|
||||
#define PLL_GPLL_DIV3 7
|
||||
|
||||
/* sclk gates (special clocks) */
|
||||
#define SCLK_SPI0 65
|
||||
#define SCLK_NANDC 67
|
||||
#define SCLK_SDMMC 68
|
||||
#define SCLK_SDIO 69
|
||||
#define SCLK_EMMC 71
|
||||
#define SCLK_UART0 77
|
||||
#define SCLK_UART1 78
|
||||
#define SCLK_UART2 79
|
||||
#define SCLK_I2S0 80
|
||||
#define SCLK_I2S1 81
|
||||
#define SCLK_SPDIF 83
|
||||
#define SCLK_TIMER0 85
|
||||
#define SCLK_TIMER1 86
|
||||
#define SCLK_TIMER2 87
|
||||
#define SCLK_TIMER3 88
|
||||
#define SCLK_TIMER4 89
|
||||
#define SCLK_TIMER5 90
|
||||
#define SCLK_SARADC 91
|
||||
#define SCLK_I2S_OUT 113
|
||||
#define SCLK_SDMMC_DRV 114
|
||||
#define SCLK_SDIO_DRV 115
|
||||
#define SCLK_EMMC_DRV 117
|
||||
#define SCLK_SDMMC_SAMPLE 118
|
||||
#define SCLK_SDIO_SAMPLE 119
|
||||
#define SCLK_EMMC_SAMPLE 121
|
||||
#define SCLK_VOP 122
|
||||
#define SCLK_MAC_SRC 124
|
||||
#define SCLK_MAC 126
|
||||
#define SCLK_MAC_REFOUT 127
|
||||
#define SCLK_MAC_REF 128
|
||||
#define SCLK_MAC_RX 129
|
||||
#define SCLK_MAC_TX 130
|
||||
#define SCLK_HEVC_CORE 134
|
||||
#define SCLK_RGA 135
|
||||
#define SCLK_CRYPTO 138
|
||||
#define SCLK_TSP 139
|
||||
#define SCLK_OTGPHY0 142
|
||||
#define SCLK_OTGPHY1 143
|
||||
#define SCLK_DDRC 144
|
||||
#define SCLK_PVTM_FUNC 145
|
||||
#define SCLK_PVTM_CORE 146
|
||||
#define SCLK_PVTM_GPU 147
|
||||
#define SCLK_MIPI_24M 148
|
||||
#define SCLK_PVTM 149
|
||||
#define SCLK_CIF_SRC 150
|
||||
#define SCLK_CIF_OUT_SRC 151
|
||||
#define SCLK_CIF_OUT 152
|
||||
#define SCLK_SFC 153
|
||||
#define SCLK_USB480M 154
|
||||
|
||||
/* dclk gates */
|
||||
#define DCLK_VOP 190
|
||||
#define DCLK_EBC 191
|
||||
|
||||
/* aclk gates */
|
||||
#define ACLK_VIO0 192
|
||||
#define ACLK_VIO1 193
|
||||
#define ACLK_DMAC 194
|
||||
#define ACLK_CPU 195
|
||||
#define ACLK_VEPU 196
|
||||
#define ACLK_VDPU 197
|
||||
#define ACLK_CIF 198
|
||||
#define ACLK_IEP 199
|
||||
#define ACLK_LCDC0 204
|
||||
#define ACLK_RGA 205
|
||||
#define ACLK_PERI 210
|
||||
#define ACLK_VOP 211
|
||||
#define ACLK_GMAC 212
|
||||
#define ACLK_GPU 213
|
||||
|
||||
/* pclk gates */
|
||||
#define PCLK_SARADC 318
|
||||
#define PCLK_WDT 319
|
||||
#define PCLK_GPIO0 320
|
||||
#define PCLK_GPIO1 321
|
||||
#define PCLK_GPIO2 322
|
||||
#define PCLK_GPIO3 323
|
||||
#define PCLK_VIO_H2P 324
|
||||
#define PCLK_MIPI 325
|
||||
#define PCLK_EFUSE 326
|
||||
#define PCLK_HDMI 327
|
||||
#define PCLK_ACODEC 328
|
||||
#define PCLK_GRF 329
|
||||
#define PCLK_I2C0 332
|
||||
#define PCLK_I2C1 333
|
||||
#define PCLK_I2C2 334
|
||||
#define PCLK_I2C3 335
|
||||
#define PCLK_SPI0 338
|
||||
#define PCLK_UART0 341
|
||||
#define PCLK_UART1 342
|
||||
#define PCLK_UART2 343
|
||||
#define PCLK_TSADC 344
|
||||
#define PCLK_PWM 350
|
||||
#define PCLK_TIMER 353
|
||||
#define PCLK_CPU 354
|
||||
#define PCLK_PERI 363
|
||||
#define PCLK_GMAC 367
|
||||
#define PCLK_PMU_PRE 368
|
||||
#define PCLK_SIM_CARD 369
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_SPDIF 440
|
||||
#define HCLK_GPS 441
|
||||
#define HCLK_USBHOST 442
|
||||
#define HCLK_I2S_8CH 443
|
||||
#define HCLK_I2S_2CH 444
|
||||
#define HCLK_VOP 452
|
||||
#define HCLK_NANDC 453
|
||||
#define HCLK_SDMMC 456
|
||||
#define HCLK_SDIO 457
|
||||
#define HCLK_EMMC 459
|
||||
#define HCLK_CPU 460
|
||||
#define HCLK_VEPU 461
|
||||
#define HCLK_VDPU 462
|
||||
#define HCLK_LCDC0 463
|
||||
#define HCLK_EBC 465
|
||||
#define HCLK_VIO 466
|
||||
#define HCLK_RGA 467
|
||||
#define HCLK_IEP 468
|
||||
#define HCLK_VIO_H2P 469
|
||||
#define HCLK_CIF 470
|
||||
#define HCLK_HOST2 473
|
||||
#define HCLK_OTG 474
|
||||
#define HCLK_TSP 475
|
||||
#define HCLK_CRYPTO 476
|
||||
#define HCLK_PERI 478
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_PERI + 1)
|
||||
|
||||
/* soft-reset indices */
|
||||
#define SRST_CORE0_PO 0
|
||||
#define SRST_CORE1_PO 1
|
||||
#define SRST_CORE2_PO 2
|
||||
#define SRST_CORE3_PO 3
|
||||
#define SRST_CORE0 4
|
||||
#define SRST_CORE1 5
|
||||
#define SRST_CORE2 6
|
||||
#define SRST_CORE3 7
|
||||
#define SRST_CORE0_DBG 8
|
||||
#define SRST_CORE1_DBG 9
|
||||
#define SRST_CORE2_DBG 10
|
||||
#define SRST_CORE3_DBG 11
|
||||
#define SRST_TOPDBG 12
|
||||
#define SRST_ACLK_CORE 13
|
||||
#define SRST_STRC_SYS_A 14
|
||||
#define SRST_L2C 15
|
||||
|
||||
#define SRST_CPUSYS_H 18
|
||||
#define SRST_AHB2APBSYS_H 19
|
||||
#define SRST_SPDIF 20
|
||||
#define SRST_INTMEM 21
|
||||
#define SRST_ROM 22
|
||||
#define SRST_PERI_NIU 23
|
||||
#define SRST_I2S_2CH 24
|
||||
#define SRST_I2S_8CH 25
|
||||
#define SRST_GPU_PVTM 26
|
||||
#define SRST_FUNC_PVTM 27
|
||||
#define SRST_CORE_PVTM 29
|
||||
#define SRST_EFUSE_P 30
|
||||
#define SRST_ACODEC_P 31
|
||||
|
||||
#define SRST_GPIO0 32
|
||||
#define SRST_GPIO1 33
|
||||
#define SRST_GPIO2 34
|
||||
#define SRST_GPIO3 35
|
||||
#define SRST_MIPIPHY_P 36
|
||||
#define SRST_UART0 39
|
||||
#define SRST_UART1 40
|
||||
#define SRST_UART2 41
|
||||
#define SRST_I2C0 43
|
||||
#define SRST_I2C1 44
|
||||
#define SRST_I2C2 45
|
||||
#define SRST_I2C3 46
|
||||
#define SRST_SFC 47
|
||||
|
||||
#define SRST_PWM 48
|
||||
#define SRST_DAP_PO 50
|
||||
#define SRST_DAP 51
|
||||
#define SRST_DAP_SYS 52
|
||||
#define SRST_CRYPTO 53
|
||||
#define SRST_GRF 55
|
||||
#define SRST_GMAC 56
|
||||
#define SRST_PERIPH_SYS_A 57
|
||||
#define SRST_PERIPH_SYS_H 58
|
||||
#define SRST_PERIPH_SYS_P 59
|
||||
#define SRST_SMART_CARD 60
|
||||
#define SRST_CPU_PERI 61
|
||||
#define SRST_EMEM_PERI 62
|
||||
#define SRST_USB_PERI 63
|
||||
|
||||
#define SRST_DMA 64
|
||||
#define SRST_GPS 67
|
||||
#define SRST_NANDC 68
|
||||
#define SRST_USBOTG0 69
|
||||
#define SRST_OTGC0 71
|
||||
#define SRST_USBOTG1 72
|
||||
#define SRST_OTGC1 74
|
||||
#define SRST_DDRMSCH 79
|
||||
|
||||
#define SRST_SDMMC 81
|
||||
#define SRST_SDIO 82
|
||||
#define SRST_EMMC 83
|
||||
#define SRST_SPI 84
|
||||
#define SRST_WDT 86
|
||||
#define SRST_SARADC 87
|
||||
#define SRST_DDRPHY 88
|
||||
#define SRST_DDRPHY_P 89
|
||||
#define SRST_DDRCTRL 90
|
||||
#define SRST_DDRCTRL_P 91
|
||||
#define SRST_TSP 92
|
||||
#define SRST_TSP_CLKIN 93
|
||||
#define SRST_HOST0_ECHI 94
|
||||
|
||||
#define SRST_HDMI_P 96
|
||||
#define SRST_VIO_ARBI_H 97
|
||||
#define SRST_VIO0_A 98
|
||||
#define SRST_VIO_BUS_H 99
|
||||
#define SRST_VOP_A 100
|
||||
#define SRST_VOP_H 101
|
||||
#define SRST_VOP_D 102
|
||||
#define SRST_UTMI0 103
|
||||
#define SRST_UTMI1 104
|
||||
#define SRST_USBPOR 105
|
||||
#define SRST_IEP_A 106
|
||||
#define SRST_IEP_H 107
|
||||
#define SRST_RGA_A 108
|
||||
#define SRST_RGA_H 109
|
||||
#define SRST_CIF0 110
|
||||
#define SRST_PMU 111
|
||||
|
||||
#define SRST_VCODEC_A 112
|
||||
#define SRST_VCODEC_H 113
|
||||
#define SRST_VIO1_A 114
|
||||
#define SRST_HEVC_CORE 115
|
||||
#define SRST_VCODEC_NIU_A 116
|
||||
#define SRST_PMU_NIU_P 117
|
||||
#define SRST_LCDC0_S 119
|
||||
#define SRST_GPU 120
|
||||
#define SRST_GPU_NIU_A 122
|
||||
#define SRST_EBC_A 123
|
||||
#define SRST_EBC_H 124
|
||||
|
||||
#define SRST_CORE_DBG 128
|
||||
#define SRST_DBG_P 129
|
||||
#define SRST_TIMER0 130
|
||||
#define SRST_TIMER1 131
|
||||
#define SRST_TIMER2 132
|
||||
#define SRST_TIMER3 133
|
||||
#define SRST_TIMER4 134
|
||||
#define SRST_TIMER5 135
|
||||
#define SRST_VIO_H2P 136
|
||||
#define SRST_VIO_MIPI_DSI 137
|
||||
|
||||
#endif
|
||||
|
|
@ -61,6 +61,17 @@
|
|||
#define SCLK_MAC_TX 130
|
||||
#define SCLK_MAC_PHY 131
|
||||
#define SCLK_MAC_OUT 132
|
||||
#define SCLK_VDEC_CABAC 133
|
||||
#define SCLK_VDEC_CORE 134
|
||||
#define SCLK_RGA 135
|
||||
#define SCLK_HDCP 136
|
||||
#define SCLK_HDMI_CEC 137
|
||||
#define SCLK_CRYPTO 138
|
||||
#define SCLK_TSP 139
|
||||
#define SCLK_HSADC 140
|
||||
#define SCLK_WIFI 141
|
||||
#define SCLK_OTGPHY0 142
|
||||
#define SCLK_OTGPHY1 143
|
||||
|
||||
/* dclk gates */
|
||||
#define DCLK_VOP 190
|
||||
|
|
@ -68,15 +79,32 @@
|
|||
|
||||
/* aclk gates */
|
||||
#define ACLK_DMAC 194
|
||||
#define ACLK_CPU 195
|
||||
#define ACLK_VPU_PRE 196
|
||||
#define ACLK_RKVDEC_PRE 197
|
||||
#define ACLK_RGA_PRE 198
|
||||
#define ACLK_IEP_PRE 199
|
||||
#define ACLK_HDCP_PRE 200
|
||||
#define ACLK_VOP_PRE 201
|
||||
#define ACLK_VPU 202
|
||||
#define ACLK_RKVDEC 203
|
||||
#define ACLK_IEP 204
|
||||
#define ACLK_RGA 205
|
||||
#define ACLK_HDCP 206
|
||||
#define ACLK_PERI 210
|
||||
#define ACLK_VOP 211
|
||||
#define ACLK_GMAC 212
|
||||
#define ACLK_GPU 213
|
||||
|
||||
/* pclk gates */
|
||||
#define PCLK_GPIO0 320
|
||||
#define PCLK_GPIO1 321
|
||||
#define PCLK_GPIO2 322
|
||||
#define PCLK_GPIO3 323
|
||||
#define PCLK_VIO_H2P 324
|
||||
#define PCLK_HDCP 325
|
||||
#define PCLK_EFUSE_1024 326
|
||||
#define PCLK_EFUSE_256 327
|
||||
#define PCLK_GRF 329
|
||||
#define PCLK_I2C0 332
|
||||
#define PCLK_I2C1 333
|
||||
|
|
@ -89,6 +117,7 @@
|
|||
#define PCLK_TSADC 344
|
||||
#define PCLK_PWM 350
|
||||
#define PCLK_TIMER 353
|
||||
#define PCLK_CPU 354
|
||||
#define PCLK_PERI 363
|
||||
#define PCLK_HDMI_CTRL 364
|
||||
#define PCLK_HDMI_PHY 365
|
||||
|
|
@ -104,6 +133,24 @@
|
|||
#define HCLK_SDMMC 456
|
||||
#define HCLK_SDIO 457
|
||||
#define HCLK_EMMC 459
|
||||
#define HCLK_CPU 460
|
||||
#define HCLK_VPU_PRE 461
|
||||
#define HCLK_RKVDEC_PRE 462
|
||||
#define HCLK_VIO_PRE 463
|
||||
#define HCLK_VPU 464
|
||||
#define HCLK_RKVDEC 465
|
||||
#define HCLK_VIO 466
|
||||
#define HCLK_RGA 467
|
||||
#define HCLK_IEP 468
|
||||
#define HCLK_VIO_H2P 469
|
||||
#define HCLK_HDCP_MMU 470
|
||||
#define HCLK_HOST0 471
|
||||
#define HCLK_HOST1 472
|
||||
#define HCLK_HOST2 473
|
||||
#define HCLK_OTG 474
|
||||
#define HCLK_TSP 475
|
||||
#define HCLK_M_CRYPTO 476
|
||||
#define HCLK_S_CRYPTO 477
|
||||
#define HCLK_PERI 478
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_PERI + 1)
|
||||
|
|
|
|||
|
|
@ -132,6 +132,8 @@
|
|||
#define SCLK_RMII_SRC 166
|
||||
#define SCLK_PCIEPHY_REF100M 167
|
||||
#define SCLK_DDRC 168
|
||||
#define SCLK_TESTCLKOUT1 169
|
||||
#define SCLK_TESTCLKOUT2 170
|
||||
|
||||
#define DCLK_VOP0 180
|
||||
#define DCLK_VOP1 181
|
||||
|
|
|
|||
Loading…
Reference in a new issue