redonkable
/
remarkable-linux
1
0
Fork 0
Code Releases Activity

MLK-16601: ARM64: dts: imx8mq: support spdif on mscale evk 

Enable the spdif1 on mscale evk, the tx is tested with fly wire to
MX51EXP (sch-26109) board, rx is not tested(waiting the audio board).

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
pull/10/head
Shengjiu Wang 2017-10-16 16:12:39 +08:00 committed by Jason Liu
parent 6fdfc7e5da
commit c9beee1f4a
3 changed files with 62 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/sound/fsl,spdif.txt
View File

@ -8,7 +8,7 @@ Required properties:
- compatible : Compatible list, must contain "fsl,imx35-spdif",
"fsl,vf610-spdif", "fsl,imx8qm-spdif",
"fsl,imx8qxp-v1-spdif"
"fsl,imx8qxp-v1-spdif", "fsl,imx8mq-spdif"
- reg : Offset and length of the register set for the device.

25
arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts
View File

@ -76,6 +76,14 @@
protocol = <0>;
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
spdif-controller = <&spdif1>;
spdif-out;
spdif-in;
};
pwmleds {
compatible = "pwm-leds";
@ -287,6 +295,13 @@
>;
};
pinctrl_spdif1: spdif1grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
@ -601,6 +616,16 @@
status = "okay";
};
&spdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif1>;
assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1_SRC>,
<&clk IMX8MQ_CLK_SPDIF1_DIV>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <0>, <24576000>;
status = "okay";
};
&gpu_pd {
power-supply = <&sw1a_reg>;
};

38
arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
View File

@ -560,9 +560,26 @@
};
spdif1: spdif@30810000 {
compatible = "fsl,imx8mq-spdif";
compatible = "fsl,imx8mq-spdif", "fsl,imx35-spdif";
reg = <0x0 0x30810000 0x0 0x10000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
<&clk IMX8MQ_CLK_25M>, /* rxtx0 */
<&clk IMX8MQ_CLK_SPDIF1_DIV>, /* rxtx1 */
<&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
<&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
<&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
<&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */
<&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */
<&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */
<&clk IMX8MQ_CLK_DUMMY>; /* spba */
clock-names = "core", "rxtx0",
"rxtx1", "rxtx2",
"rxtx3", "rxtx4",
"rxtx5", "rxtx6",
"rxtx7", "spba";
dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -605,9 +622,26 @@
};
spdif2: spdif@308a0000 {
compatible = "fsl,imx8mq-spdif";
compatible = "fsl,imx8mq-spdif", "fsl,imx35-spdif";
reg = <0x0 0x308a0000 0x0 0x10000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
<&clk IMX8MQ_CLK_25M>, /* rxtx0 */
<&clk IMX8MQ_CLK_SPDIF2_DIV>, /* rxtx1 */
<&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
<&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
<&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
<&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */
<&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */
<&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */
<&clk IMX8MQ_CLK_DUMMY>; /* spba */
clock-names = "core", "rxtx0",
"rxtx1", "rxtx2",
"rxtx3", "rxtx4",
"rxtx5", "rxtx6",
"rxtx7", "spba";
dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>;
dma-names = "rx", "tx";
status = "disabled";
};