Merge branch 'x86/mpx' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 cpufeature and mpx updates from Peter Anvin: "This includes the basic infrastructure for MPX (Memory Protection Extensions) support, but does not include MPX support itself. It is, however, a prerequisite for KVM support for MPX, which I believe will be pushed later this merge window by the KVM team. This includes moving the functionality in futex_atomic_cmpxchg_inatomic() into a new function in uaccess.h so it can be reused - this will be used by the final MPX patches. The actual MPX functionality (map management and so on) will be pushed in a future merge window, when ready" * 'x86/mpx' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/intel/mpx: Remove unused LWP structure x86, mpx: Add MPX related opcodes to the x86 opcode map x86: replace futex_atomic_cmpxchg_inatomic() with user_atomic_cmpxchg_inatomic x86: add user_atomic_cmpxchg_inatomic at uaccess.h x86, xsave: Support eager-only xsave features, add MPX support x86, cpufeature: Define the Intel MPX feature flag
This commit is contained in:
commit
c9cdd9a6ae
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@ -216,6 +216,7 @@
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#define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */
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#define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */
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#define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */
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#define X86_FEATURE_MPX (9*32+14) /* Memory Protection Extension */
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#define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */
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#define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */
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#define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */
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@ -110,26 +110,7 @@ static inline int futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
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static inline int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
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u32 oldval, u32 newval)
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{
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int ret = 0;
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if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
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return -EFAULT;
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asm volatile("\t" ASM_STAC "\n"
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"1:\t" LOCK_PREFIX "cmpxchgl %4, %2\n"
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"2:\t" ASM_CLAC "\n"
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"\t.section .fixup, \"ax\"\n"
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"3:\tmov %3, %0\n"
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"\tjmp 2b\n"
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"\t.previous\n"
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_ASM_EXTABLE(1b, 3b)
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: "+r" (ret), "=a" (oldval), "+m" (*uaddr)
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: "i" (-EFAULT), "r" (newval), "1" (oldval)
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: "memory"
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);
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*uval = oldval;
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return ret;
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return user_atomic_cmpxchg_inatomic(uval, uaddr, oldval, newval);
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}
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#endif
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@ -370,6 +370,20 @@ struct ymmh_struct {
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u32 ymmh_space[64];
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};
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/* We don't support LWP yet: */
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struct lwp_struct {
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u8 reserved[128];
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};
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struct bndregs_struct {
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u64 bndregs[8];
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} __packed;
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struct bndcsr_struct {
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u64 cfg_reg_u;
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u64 status_reg;
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} __packed;
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struct xsave_hdr_struct {
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u64 xstate_bv;
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u64 reserved1[2];
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@ -380,6 +394,9 @@ struct xsave_struct {
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struct i387_fxsave_struct i387;
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struct xsave_hdr_struct xsave_hdr;
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struct ymmh_struct ymmh;
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struct lwp_struct lwp;
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struct bndregs_struct bndregs;
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struct bndcsr_struct bndcsr;
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/* new processor state extensions will go here */
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} __attribute__ ((packed, aligned (64)));
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@ -533,6 +533,98 @@ extern __must_check long strnlen_user(const char __user *str, long n);
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unsigned long __must_check clear_user(void __user *mem, unsigned long len);
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unsigned long __must_check __clear_user(void __user *mem, unsigned long len);
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extern void __cmpxchg_wrong_size(void)
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__compiletime_error("Bad argument size for cmpxchg");
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#define __user_atomic_cmpxchg_inatomic(uval, ptr, old, new, size) \
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({ \
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int __ret = 0; \
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__typeof__(ptr) __uval = (uval); \
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__typeof__(*(ptr)) __old = (old); \
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__typeof__(*(ptr)) __new = (new); \
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switch (size) { \
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case 1: \
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{ \
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asm volatile("\t" ASM_STAC "\n" \
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"1:\t" LOCK_PREFIX "cmpxchgb %4, %2\n" \
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"2:\t" ASM_CLAC "\n" \
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"\t.section .fixup, \"ax\"\n" \
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"3:\tmov %3, %0\n" \
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"\tjmp 2b\n" \
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"\t.previous\n" \
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_ASM_EXTABLE(1b, 3b) \
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: "+r" (__ret), "=a" (__old), "+m" (*(ptr)) \
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: "i" (-EFAULT), "q" (__new), "1" (__old) \
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: "memory" \
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); \
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break; \
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} \
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case 2: \
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{ \
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asm volatile("\t" ASM_STAC "\n" \
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"1:\t" LOCK_PREFIX "cmpxchgw %4, %2\n" \
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"2:\t" ASM_CLAC "\n" \
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"\t.section .fixup, \"ax\"\n" \
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"3:\tmov %3, %0\n" \
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"\tjmp 2b\n" \
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"\t.previous\n" \
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_ASM_EXTABLE(1b, 3b) \
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: "+r" (__ret), "=a" (__old), "+m" (*(ptr)) \
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: "i" (-EFAULT), "r" (__new), "1" (__old) \
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: "memory" \
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); \
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break; \
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} \
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case 4: \
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{ \
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asm volatile("\t" ASM_STAC "\n" \
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"1:\t" LOCK_PREFIX "cmpxchgl %4, %2\n" \
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"2:\t" ASM_CLAC "\n" \
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"\t.section .fixup, \"ax\"\n" \
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"3:\tmov %3, %0\n" \
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"\tjmp 2b\n" \
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"\t.previous\n" \
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_ASM_EXTABLE(1b, 3b) \
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: "+r" (__ret), "=a" (__old), "+m" (*(ptr)) \
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: "i" (-EFAULT), "r" (__new), "1" (__old) \
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: "memory" \
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); \
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break; \
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} \
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case 8: \
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{ \
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if (!IS_ENABLED(CONFIG_X86_64)) \
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__cmpxchg_wrong_size(); \
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\
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asm volatile("\t" ASM_STAC "\n" \
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"1:\t" LOCK_PREFIX "cmpxchgq %4, %2\n" \
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"2:\t" ASM_CLAC "\n" \
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"\t.section .fixup, \"ax\"\n" \
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"3:\tmov %3, %0\n" \
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"\tjmp 2b\n" \
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"\t.previous\n" \
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_ASM_EXTABLE(1b, 3b) \
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: "+r" (__ret), "=a" (__old), "+m" (*(ptr)) \
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: "i" (-EFAULT), "r" (__new), "1" (__old) \
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: "memory" \
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); \
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break; \
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} \
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default: \
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__cmpxchg_wrong_size(); \
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} \
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*__uval = __old; \
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__ret; \
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})
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#define user_atomic_cmpxchg_inatomic(uval, ptr, old, new) \
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({ \
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access_ok(VERIFY_WRITE, (ptr), sizeof(*(ptr))) ? \
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__user_atomic_cmpxchg_inatomic((uval), (ptr), \
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(old), (new), sizeof(*(ptr))) : \
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-EFAULT; \
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})
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/*
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* movsl can be slow when source and dest are not both 8-byte aligned
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*/
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@ -9,6 +9,8 @@
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#define XSTATE_FP 0x1
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#define XSTATE_SSE 0x2
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#define XSTATE_YMM 0x4
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#define XSTATE_BNDREGS 0x8
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#define XSTATE_BNDCSR 0x10
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#define XSTATE_FPSSE (XSTATE_FP | XSTATE_SSE)
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@ -20,10 +22,14 @@
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#define XSAVE_YMM_SIZE 256
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#define XSAVE_YMM_OFFSET (XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET)
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/*
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* These are the features that the OS can handle currently.
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*/
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#define XCNTXT_MASK (XSTATE_FP | XSTATE_SSE | XSTATE_YMM)
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/* Supported features which support lazy state saving */
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#define XSTATE_LAZY (XSTATE_FP | XSTATE_SSE | XSTATE_YMM)
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/* Supported features which require eager state saving */
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#define XSTATE_EAGER (XSTATE_BNDREGS | XSTATE_BNDCSR)
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/* All currently supported features */
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#define XCNTXT_MASK (XSTATE_LAZY | XSTATE_EAGER)
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#ifdef CONFIG_X86_64
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#define REX_PREFIX "0x48, "
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@ -562,6 +562,16 @@ static void __init xstate_enable_boot_cpu(void)
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if (cpu_has_xsaveopt && eagerfpu != DISABLE)
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eagerfpu = ENABLE;
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if (pcntxt_mask & XSTATE_EAGER) {
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if (eagerfpu == DISABLE) {
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pr_err("eagerfpu not present, disabling some xstate features: 0x%llx\n",
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pcntxt_mask & XSTATE_EAGER);
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pcntxt_mask &= ~XSTATE_EAGER;
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} else {
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eagerfpu = ENABLE;
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}
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}
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pr_info("enabled xstate_bv 0x%llx, cntxt size 0x%x\n",
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pcntxt_mask, xstate_size);
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}
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@ -346,8 +346,8 @@ AVXcode: 1
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17: vmovhps Mq,Vq (v1) | vmovhpd Mq,Vq (66),(v1)
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18: Grp16 (1A)
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19:
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1a:
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1b:
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1a: BNDCL Ev,Gv | BNDCU Ev,Gv | BNDMOV Gv,Ev | BNDLDX Gv,Ev,Gv
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1b: BNDCN Ev,Gv | BNDMOV Ev,Gv | BNDMK Gv,Ev | BNDSTX Ev,GV,Gv
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1c:
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1d:
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1e:
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