clk/exynos5420: add sclk_hdmiphy to the list of special clocks
Add sclk_hdmiphy to the list of exposed clocks. This is required by hdmi driver to change the parent of hdmi clock. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -59,6 +59,7 @@ clock which they consume.
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sclk_pwm 155
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sclk_gscl_wa 156
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sclk_gscl_wb 157
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sclk_hdmiphy 158
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[Peripheral Clock Gates]
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@ -120,7 +120,7 @@ enum exynos5420_clks {
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sclk_i2s2, sclk_pcm1, sclk_pcm2, sclk_spdif, sclk_hdmi, sclk_pixel,
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sclk_dp1, sclk_mipi1, sclk_fimd1, sclk_maudio0, sclk_maupcm0,
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sclk_usbd300, sclk_usbd301, sclk_usbphy300, sclk_usbphy301, sclk_unipro,
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sclk_pwm, sclk_gscl_wa, sclk_gscl_wb,
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sclk_pwm, sclk_gscl_wa, sclk_gscl_wb, sclk_hdmiphy,
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/* gate clocks */
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aclk66_peric = 256, uart0, uart1, uart2, uart3, i2c0, i2c1, i2c2, i2c3,
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@ -297,7 +297,7 @@ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initda
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/* fixed rate clocks generated inside the soc */
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static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = {
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FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
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FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
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FRATE(none, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
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FRATE(none, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
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FRATE(none, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000),
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