arm64/kernel: enable A53 erratum #8434319 handling at runtime
Omit patching of ADRP instruction at module load time if the current CPUs are not susceptible to the erratum. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> [will: Drop duplicate initialisation of .def_scope field] Signed-off-by: Will Deacon <will.deacon@arm.com>
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@ -45,7 +45,8 @@
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#define ARM64_HARDEN_BRANCH_PREDICTOR 24
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#define ARM64_HARDEN_BP_POST_GUEST_EXIT 25
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#define ARM64_HAS_RAS_EXTN 26
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#define ARM64_WORKAROUND_843419 27
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#define ARM64_NCAPS 27
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#define ARM64_NCAPS 28
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#endif /* __ASM_CPUCAPS_H */
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@ -298,6 +298,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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MIDR_CPU_VAR_REV(1, 2)),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_843419
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{
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/* Cortex-A53 r0p[01234] */
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.desc = "ARM erratum 843419",
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.capability = ARM64_WORKAROUND_843419,
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MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
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MIDR_FIXED(0x4, BIT(8)),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_845719
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{
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/* Cortex-A53 r0p[01234] */
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@ -158,7 +158,8 @@ static unsigned int count_plts(Elf64_Sym *syms, Elf64_Rela *rela, int num,
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break;
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case R_AARCH64_ADR_PREL_PG_HI21_NC:
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case R_AARCH64_ADR_PREL_PG_HI21:
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if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_843419))
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if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_843419) ||
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!cpus_have_const_cap(ARM64_WORKAROUND_843419))
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break;
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/*
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@ -203,6 +203,7 @@ static int reloc_insn_adrp(struct module *mod, __le32 *place, u64 val)
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u32 insn;
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if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_843419) ||
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!cpus_have_const_cap(ARM64_WORKAROUND_843419) ||
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((u64)place & 0xfff) < 0xff8)
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return reloc_insn_imm(RELOC_OP_PAGE, place, val, 12, 21,
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AARCH64_INSN_IMM_ADR);
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