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[ACPI] acpi_register_gsi() fix needed for ACPICA 20051021

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Use the #define for ACPI_LEVEL_SENSITIVE instead of assuming
non-zero, because ACPICA 20051021 changes its value to zero.

Also, use uniform variable names:
edge_level -> triggering
active_high_low -> polarity

Signed-off-by: Len Brown <len.brown@intel.com>
This commit is contained in:
Len Brown 2005-12-28 02:43:51 -05:00
parent 28f55ebce5
commit cb654695f6
4 changed files with 11 additions and 11 deletions
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6
arch/i386/kernel/acpi/boot.c
View file

@ -464,7 +464,7 @@ int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
* success: return IRQ number (>=0) * success: return IRQ number (>=0)
* failure: return < 0 * failure: return < 0
*/ */
int acpi_register_gsi(u32 gsi, int edge_level, int active_high_low) int acpi_register_gsi(u32 gsi, int triggering, int polarity)
{ {
unsigned int irq; unsigned int irq;
unsigned int plat_gsi = gsi; unsigned int plat_gsi = gsi;
@ -476,14 +476,14 @@ int acpi_register_gsi(u32 gsi, int edge_level, int active_high_low)
if (acpi_irq_model == ACPI_IRQ_MODEL_PIC) { if (acpi_irq_model == ACPI_IRQ_MODEL_PIC) {
extern void eisa_set_level_irq(unsigned int irq); extern void eisa_set_level_irq(unsigned int irq);
if (edge_level == ACPI_LEVEL_SENSITIVE) if (triggering == ACPI_LEVEL_SENSITIVE)
eisa_set_level_irq(gsi); eisa_set_level_irq(gsi);
} }
#endif #endif
#ifdef CONFIG_X86_IO_APIC #ifdef CONFIG_X86_IO_APIC
if (acpi_irq_model == ACPI_IRQ_MODEL_IOAPIC) { if (acpi_irq_model == ACPI_IRQ_MODEL_IOAPIC) {
plat_gsi = mp_register_gsi(gsi, edge_level, active_high_low); plat_gsi = mp_register_gsi(gsi, triggering, polarity);
} }
#endif #endif
acpi_gsi_to_irq(plat_gsi, &irq); acpi_gsi_to_irq(plat_gsi, &irq);

8
arch/i386/kernel/mpparse.c
View file

@ -1070,7 +1070,7 @@ void __init mp_config_acpi_legacy_irqs (void)
#define MAX_GSI_NUM 4096 #define MAX_GSI_NUM 4096
int mp_register_gsi (u32 gsi, int edge_level, int active_high_low) int mp_register_gsi (u32 gsi, int triggering, int polarity)
{ {
int ioapic = -1; int ioapic = -1;
int ioapic_pin = 0; int ioapic_pin = 0;
@ -1119,7 +1119,7 @@ int mp_register_gsi (u32 gsi, int edge_level, int active_high_low)
mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit); mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
if (edge_level) { if (triggering == ACPI_LEVEL_SENSITIVE) {
/* /*
* For PCI devices assign IRQs in order, avoiding gaps * For PCI devices assign IRQs in order, avoiding gaps
* due to unused I/O APIC pins. * due to unused I/O APIC pins.
@ -1141,8 +1141,8 @@ int mp_register_gsi (u32 gsi, int edge_level, int active_high_low)
} }
io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
edge_level == ACPI_EDGE_SENSITIVE ? 0 : 1, triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
active_high_low == ACPI_ACTIVE_HIGH ? 0 : 1); polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
return gsi; return gsi;
} }

6
arch/ia64/kernel/acpi.c
View file

@ -567,16 +567,16 @@ void __init acpi_numa_arch_fixup(void)
* success: return IRQ number (>=0) * success: return IRQ number (>=0)
* failure: return < 0 * failure: return < 0
*/ */
int acpi_register_gsi(u32 gsi, int edge_level, int active_high_low) int acpi_register_gsi(u32 gsi, int triggering, int polarity)
{ {
if (has_8259 && gsi < 16) if (has_8259 && gsi < 16)
return isa_irq_to_vector(gsi); return isa_irq_to_vector(gsi);
return iosapic_register_intr(gsi, return iosapic_register_intr(gsi,
(active_high_low == (polarity ==
ACPI_ACTIVE_HIGH) ? IOSAPIC_POL_HIGH : ACPI_ACTIVE_HIGH) ? IOSAPIC_POL_HIGH :
IOSAPIC_POL_LOW, IOSAPIC_POL_LOW,
(edge_level == (triggering ==
ACPI_EDGE_SENSITIVE) ? IOSAPIC_EDGE : ACPI_EDGE_SENSITIVE) ? IOSAPIC_EDGE :
IOSAPIC_LEVEL); IOSAPIC_LEVEL);
} }

2
arch/x86_64/kernel/mpparse.c
View file

@ -964,7 +964,7 @@ int mp_register_gsi(u32 gsi, int triggering, int polarity)
mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit); mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
if (triggering) { if (triggering == ACPI_LEVEL_SENSITIVE) {
/* /*
* For PCI devices assign IRQs in order, avoiding gaps * For PCI devices assign IRQs in order, avoiding gaps
* due to unused I/O APIC pins. * due to unused I/O APIC pins.