MLK-18138-2: soc: imx: gpc: Convert imx6sx to new bindings
This fixes graphics on imx6sx by aligning closer to upstream instead of adding new features to old bindings. Upstream adds a 4th power domain for PCI but this is is wrong: the PCI block is in the DISPMIX domain and only PCIE_PHY is in the PCIE_PHY power domain. Manual is not very clear on this but in section 10.4.1.4.1 there is this statement: "The DISPLAY domain contains GIS, CSI, PXP, LCDIF, PCIe, DCIC, and LDB. It is supplied by internal regulator." Placing pcie in a 4th power domain makes lspci hang when display is turned off. In upstream the dispmix domain is not actually touched on 6sx so it's always on, this is why pci seems to work. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Acked-by: Richard Zhu <hongxing.zhu@nxp.com>pull/10/head
parent
c053493276
commit
cbe8752661
|
@ -290,7 +290,7 @@
|
|||
"gpu3d_shader_clk";
|
||||
resets = <&src 0>;
|
||||
reset-names = "gpu3d";
|
||||
power-domains = <&gpc 1>;
|
||||
power-domains = <&pd_pu>;
|
||||
};
|
||||
|
||||
gpmi: gpmi-nand@01806000{
|
||||
|
@ -892,15 +892,38 @@
|
|||
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
fsl,mf-mix-wakeup-irq = <0x7c00000 0x3d00 0x0 0x400240>;
|
||||
clocks = <&clks IMX6SX_CLK_GPU>, <&clks IMX6SX_CLK_IPG>,
|
||||
<&clks IMX6SX_CLK_PXP_AXI>, <&clks IMX6SX_CLK_DISPLAY_AXI>,
|
||||
<&clks IMX6SX_CLK_LCDIF1_PIX>, <&clks IMX6SX_CLK_LCDIF_APB>,
|
||||
<&clks IMX6SX_CLK_LCDIF2_PIX>, <&clks IMX6SX_CLK_CSI>,
|
||||
<&clks IMX6SX_CLK_VADC>;
|
||||
clock-names = "gpu3d_core", "ipg", "pxp_axi", "disp_axi", "lcdif1_pix",
|
||||
"lcdif_axi", "lcdif2_pix", "csi_mclk";
|
||||
clocks = <&clks IMX6SX_CLK_IPG>;
|
||||
clock-names = "ipg";
|
||||
pcie-phy-supply = <®_pcie_phy>;
|
||||
#power-domain-cells = <1>;
|
||||
|
||||
pgc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
power-domain@0 {
|
||||
reg = <0>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_pu: power-domain@1 {
|
||||
reg = <1>;
|
||||
#power-domain-cells = <0>;
|
||||
power-supply = <®_soc>;
|
||||
clocks = <&clks IMX6SX_CLK_GPU>;
|
||||
};
|
||||
|
||||
pd_disp: power-domain@2 {
|
||||
reg = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
clocks = <&clks IMX6SX_CLK_PXP_AXI>,
|
||||
<&clks IMX6SX_CLK_DISPLAY_AXI>,
|
||||
<&clks IMX6SX_CLK_LCDIF1_PIX>,
|
||||
<&clks IMX6SX_CLK_LCDIF_APB>,
|
||||
<&clks IMX6SX_CLK_LCDIF2_PIX>,
|
||||
<&clks IMX6SX_CLK_CSI>,
|
||||
<&clks IMX6SX_CLK_VADC>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
iomuxc: iomuxc@020e0000 {
|
||||
|
@ -1386,7 +1409,7 @@
|
|||
clocks = <&clks IMX6SX_CLK_PXP_AXI>,
|
||||
<&clks IMX6SX_CLK_DISPLAY_AXI>;
|
||||
clock-names = "pxp-axi", "disp-axi";
|
||||
power-domains = <&gpc 2>;
|
||||
power-domains = <&pd_disp>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -1409,7 +1432,7 @@
|
|||
<&clks IMX6SX_CLK_LCDIF_APB>,
|
||||
<&clks IMX6SX_CLK_DISPLAY_AXI>;
|
||||
clock-names = "pix", "axi", "disp_axi";
|
||||
power-domains = <&gpc 2>;
|
||||
power-domains = <&pd_disp>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -1421,7 +1444,7 @@
|
|||
<&clks IMX6SX_CLK_LCDIF_APB>,
|
||||
<&clks IMX6SX_CLK_DISPLAY_AXI>;
|
||||
clock-names = "pix", "axi", "disp_axi";
|
||||
power-domains = <&gpc 2>;
|
||||
power-domains = <&pd_disp>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -1432,7 +1455,7 @@
|
|||
clocks = <&clks IMX6SX_CLK_VADC>,
|
||||
<&clks IMX6SX_CLK_CSI>;
|
||||
clock-names = "vadc", "csi";
|
||||
power-domains = <&gpc 2>;
|
||||
power-domains = <&pd_disp>;
|
||||
gpr = <&gpr>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -1583,7 +1606,7 @@
|
|||
<&clks IMX6SX_CLK_DISPLAY_AXI>;
|
||||
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
|
||||
pcie-phy-supply = <®_pcie_phy>;
|
||||
power-domains = <&gpc 2>;
|
||||
power-domains = <&pd_disp>;
|
||||
fsl,max-link-speed = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
@ -414,10 +414,16 @@ static const struct imx_gpc_dt_data imx6sl_dt_data = {
|
|||
.err009619_present = false,
|
||||
};
|
||||
|
||||
static const struct imx_gpc_dt_data imx6sx_dt_data = {
|
||||
.num_domains = 3,
|
||||
.err009619_present = false,
|
||||
};
|
||||
|
||||
static const struct of_device_id imx_gpc_dt_ids[] = {
|
||||
{ .compatible = "fsl,imx6q-gpc", .data = &imx6q_dt_data },
|
||||
{ .compatible = "fsl,imx6qp-gpc", .data = &imx6qp_dt_data },
|
||||
{ .compatible = "fsl,imx6sl-gpc", .data = &imx6sl_dt_data },
|
||||
{ .compatible = "fsl,imx6sx-gpc", .data = &imx6sx_dt_data },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
Loading…
Reference in New Issue