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Merge 3.15-rc6 into driver-core-next 

We want the kernfs fixes in this branch as well for testing.

Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
wifi-calibration
Greg Kroah-Hartman 2014-05-23 10:13:53 +09:00
parent d35cc56ddf 4b660a7f5c
commit cbfef53360
724 changed files with 8057 additions and 4802 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/ABI/testing/sysfs-bus-pci
View File

@ -117,7 +117,7 @@ Description:
What: /sys/bus/pci/devices/.../vpd What: /sys/bus/pci/devices/.../vpd
Date: February 2008 Date: February 2008
Contact: Ben Hutchings <bhutchings@solarflare.com> Contact: Ben Hutchings <bwh@kernel.org>
Description: Description:
A file named vpd in a device directory will be a A file named vpd in a device directory will be a
binary file containing the Vital Product Data for the binary file containing the Vital Product Data for the

3
Documentation/devicetree/bindings/arm/arch_timer.txt
View File

@ -19,6 +19,9 @@ to deliver its interrupts via SPIs.
- clock-frequency : The frequency of the main counter, in Hz. Optional. - clock-frequency : The frequency of the main counter, in Hz. Optional.
- always-on : a boolean property. If present, the timer is powered through an
always-on power domain, therefore it never loses context.
Example: Example:
timer { timer {

3
Documentation/devicetree/bindings/ata/apm-xgene.txt
View File

@ -24,6 +24,7 @@ Required properties:
* "sata-phy" for the SATA 6.0Gbps PHY * "sata-phy" for the SATA 6.0Gbps PHY
Optional properties: Optional properties:
- dma-coherent : Present if dma operations are coherent
- status : Shall be "ok" if enabled or "disabled" if disabled. - status : Shall be "ok" if enabled or "disabled" if disabled.
Default is "ok". Default is "ok".
@ -55,6 +56,7 @@ Example:
<0x0 0x1f22e000 0x0 0x1000>, <0x0 0x1f22e000 0x0 0x1000>,
<0x0 0x1f227000 0x0 0x1000>; <0x0 0x1f227000 0x0 0x1000>;
interrupts = <0x0 0x87 0x4>; interrupts = <0x0 0x87 0x4>;
dma-coherent;
status = "ok"; status = "ok";
clocks = <&sataclk 0>; clocks = <&sataclk 0>;
phys = <&phy2 0>; phys = <&phy2 0>;
@ -69,6 +71,7 @@ Example:
<0x0 0x1f23e000 0x0 0x1000>, <0x0 0x1f23e000 0x0 0x1000>,
<0x0 0x1f237000 0x0 0x1000>; <0x0 0x1f237000 0x0 0x1000>;
interrupts = <0x0 0x88 0x4>; interrupts = <0x0 0x88 0x4>;
dma-coherent;
status = "ok"; status = "ok";
clocks = <&sataclk 0>; clocks = <&sataclk 0>;
phys = <&phy3 0>; phys = <&phy3 0>;

2
Documentation/devicetree/bindings/clock/at91-clock.txt
View File

@ -62,7 +62,7 @@ Required properties for PMC node:
- interrupt-controller : tell that the PMC is an interrupt controller. - interrupt-controller : tell that the PMC is an interrupt controller.
- #interrupt-cells : must be set to 1. The first cell encodes the interrupt id, - #interrupt-cells : must be set to 1. The first cell encodes the interrupt id,
and reflect the bit position in the PMC_ER/DR/SR registers. and reflect the bit position in the PMC_ER/DR/SR registers.
You can use the dt macros defined in dt-bindings/clk/at91.h. You can use the dt macros defined in dt-bindings/clock/at91.h.
0 (AT91_PMC_MOSCS) -> main oscillator ready 0 (AT91_PMC_MOSCS) -> main oscillator ready
1 (AT91_PMC_LOCKA) -> PLL A ready 1 (AT91_PMC_LOCKA) -> PLL A ready
2 (AT91_PMC_LOCKB) -> PLL B ready 2 (AT91_PMC_LOCKB) -> PLL B ready

2
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
View File

@ -43,7 +43,7 @@ Example
clock-output-names = clock-output-names =
"tpu0", "mmcif1", "sdhi3", "sdhi2", "tpu0", "mmcif1", "sdhi3", "sdhi2",
"sdhi1", "sdhi0", "mmcif0"; "sdhi1", "sdhi0", "mmcif0";
renesas,clock-indices = < clock-indices = <
R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
R8A7790_CLK_MMCIF0 R8A7790_CLK_MMCIF0

4
Documentation/devicetree/bindings/dma/ti-edma.txt
View File

@ -29,6 +29,6 @@ edma: edma@49000000 {
dma-channels = <64>; dma-channels = <64>;
ti,edma-regions = <4>; ti,edma-regions = <4>;
ti,edma-slots = <256>; ti,edma-slots = <256>;
ti,edma-xbar-event-map = <1 12 ti,edma-xbar-event-map = /bits/ 16 <1 12
2 13>; 2 13>;
}; };

12
Documentation/devicetree/bindings/net/arc_emac.txt
View File

@ -4,11 +4,15 @@ Required properties:
- compatible: Should be "snps,arc-emac" - compatible: Should be "snps,arc-emac"
- reg: Address and length of the register set for the device - reg: Address and length of the register set for the device
- interrupts: Should contain the EMAC interrupts - interrupts: Should contain the EMAC interrupts
- clock-frequency: CPU frequency. It is needed to calculate and set polling
period of EMAC.
- max-speed: see ethernet.txt file in the same directory. - max-speed: see ethernet.txt file in the same directory.
- phy: see ethernet.txt file in the same directory. - phy: see ethernet.txt file in the same directory.
Clock handling:
The clock frequency is needed to calculate and set polling period of EMAC.
It must be provided by one of:
- clock-frequency: CPU frequency.
- clocks: reference to the clock supplying the EMAC.
Child nodes of the driver are the individual PHY devices connected to the Child nodes of the driver are the individual PHY devices connected to the
MDIO bus. They must have a "reg" property given the PHY address on the MDIO bus. MDIO bus. They must have a "reg" property given the PHY address on the MDIO bus.
@ -19,7 +23,11 @@ Examples:
reg = <0xc0fc2000 0x3c>; reg = <0xc0fc2000 0x3c>;
interrupts = <6>; interrupts = <6>;
mac-address = [ 00 11 22 33 44 55 ]; mac-address = [ 00 11 22 33 44 55 ];
clock-frequency = <80000000>; clock-frequency = <80000000>;
/* or */
clocks = <&emac_clock>;
max-speed = <100>; max-speed = <100>;
phy = <&phy0>; phy = <&phy0>;

2
Documentation/devicetree/bindings/net/socfpga-dwmac.txt
View File

@ -23,5 +23,5 @@ gmac0: ethernet@ff700000 {
interrupt-names = "macirq"; interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
clocks = <&emac_0_clk>; clocks = <&emac_0_clk>;
clocks-names = "stmmaceth"; clock-names = "stmmaceth";
}; };

2
Documentation/devicetree/bindings/net/stmmac.txt
View File

@ -33,7 +33,7 @@ Optional properties:
- max-frame-size: See ethernet.txt file in the same directory - max-frame-size: See ethernet.txt file in the same directory
- clocks: If present, the first clock should be the GMAC main clock, - clocks: If present, the first clock should be the GMAC main clock,
further clocks may be specified in derived bindings. further clocks may be specified in derived bindings.
- clocks-names: One name for each entry in the clocks property, the - clock-names: One name for each entry in the clocks property, the
first one should be "stmmaceth". first one should be "stmmaceth".
Examples: Examples:

4
Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
View File

@ -83,7 +83,7 @@ Example:
reg = <0xfe61f080 0x4>; reg = <0xfe61f080 0x4>;
reg-names = "irqmux"; reg-names = "irqmux";
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
interrupts-names = "irqmux"; interrupt-names = "irqmux";
ranges = <0 0xfe610000 0x5000>; ranges = <0 0xfe610000 0x5000>;
PIO0: gpio@fe610000 { PIO0: gpio@fe610000 {
@ -165,7 +165,7 @@ sdhci0:sdhci@fe810000{
interrupt-parent = <&PIO3>; interrupt-parent = <&PIO3>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; /* Interrupt line via PIO3-3 */ interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; /* Interrupt line via PIO3-3 */
interrupts-names = "card-detect"; interrupt-names = "card-detect";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc>; pinctrl-0 = <&pinctrl_mmc>;
}; };

2
Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
View File

@ -47,7 +47,7 @@ mcasp0: mcasp0@1d00000 {
reg = <0x100000 0x3000>; reg = <0x100000 0x3000>;
reg-names "mpu"; reg-names "mpu";
interrupts = <82>, <83>; interrupts = <82>, <83>;
interrupts-names = "tx", "rx"; interrupt-names = "tx", "rx";
op-mode = <0>; /* MCASP_IIS_MODE */ op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>; tdm-slots = <2>;
serial-dir = < serial-dir = <

6
Documentation/devicetree/bindings/sound/tlv320aic31xx.txt
View File

@ -13,6 +13,9 @@ Required properties:
"ti,tlv320aic3111" - TLV320AIC3111 (stereo speaker amp, MiniDSP) "ti,tlv320aic3111" - TLV320AIC3111 (stereo speaker amp, MiniDSP)
- reg - <int> - I2C slave address - reg - <int> - I2C slave address
- HPVDD-supply, SPRVDD-supply, SPLVDD-supply, AVDD-supply, IOVDD-supply,
DVDD-supply : power supplies for the device as covered in
Documentation/devicetree/bindings/regulator/regulator.txt
Optional properties: Optional properties:
@ -24,9 +27,6 @@ Optional properties:
3 or MICBIAS_AVDD - MICBIAS output is connected to AVDD 3 or MICBIAS_AVDD - MICBIAS output is connected to AVDD
If this node is not mentioned or if the value is unknown, then If this node is not mentioned or if the value is unknown, then
micbias is set to 2.0V. micbias is set to 2.0V.
- HPVDD-supply, SPRVDD-supply, SPLVDD-supply, AVDD-supply, IOVDD-supply,
DVDD-supply : power supplies for the device as covered in
Documentation/devicetree/bindings/regulator/regulator.txt
CODEC output pins: CODEC output pins:
* HPL * HPL

5
Documentation/input/elantech.txt
View File

@ -504,9 +504,12 @@ byte 5:
* reg_10 * reg_10
bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 A 0 0 0 0 R F T A
A: 1 = enable absolute tracking A: 1 = enable absolute tracking
T: 1 = enable two finger mode auto correct
F: 1 = disable ABS Position Filter
R: 1 = enable real hardware resolution
6.2 Native absolute mode 6 byte packet format 6.2 Native absolute mode 6 byte packet format
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

8
Documentation/kernel-parameters.txt
View File

@ -2218,10 +2218,10 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
noreplace-smp [X86-32,SMP] Don't replace SMP instructions noreplace-smp [X86-32,SMP] Don't replace SMP instructions
with UP alternatives with UP alternatives
nordrand [X86] Disable the direct use of the RDRAND nordrand [X86] Disable kernel use of the RDRAND and
instruction even if it is supported by the RDSEED instructions even if they are supported
processor. RDRAND is still available to user by the processor. RDRAND and RDSEED are still
space applications. available to user space applications.
noresume [SWSUSP] Disables resume and restores original swap noresume [SWSUSP] Disables resume and restores original swap
space. space.

2
Documentation/networking/scaling.txt
View File

@ -429,7 +429,7 @@ RPS and RFS were introduced in kernel 2.6.35. XPS was incorporated into
(therbert@google.com) (therbert@google.com)
Accelerated RFS was introduced in 2.6.35. Original patches were Accelerated RFS was introduced in 2.6.35. Original patches were
submitted by Ben Hutchings (bhutchings@solarflare.com) submitted by Ben Hutchings (bwh@kernel.org)
Authors: Authors:
Tom Herbert (therbert@google.com) Tom Herbert (therbert@google.com)

51
MAINTAINERS
View File

@ -1893,14 +1893,15 @@ L: netdev@vger.kernel.org
S: Supported S: Supported
F: drivers/net/ethernet/broadcom/bnx2x/ F: drivers/net/ethernet/broadcom/bnx2x/
BROADCOM BCM281XX/BCM11XXX ARM ARCHITECTURE BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITECTURE
M: Christian Daudt <bcm@fixthebug.org> M: Christian Daudt <bcm@fixthebug.org>
M: Matt Porter <mporter@linaro.org> M: Matt Porter <mporter@linaro.org>
L: bcm-kernel-feedback-list@broadcom.com L: bcm-kernel-feedback-list@broadcom.com
T: git git://git.github.com/broadcom/bcm11351 T: git git://github.com/broadcom/mach-bcm
S: Maintained S: Maintained
F: arch/arm/mach-bcm/ F: arch/arm/mach-bcm/
F: arch/arm/boot/dts/bcm113* F: arch/arm/boot/dts/bcm113*
F: arch/arm/boot/dts/bcm216*
F: arch/arm/boot/dts/bcm281* F: arch/arm/boot/dts/bcm281*
F: arch/arm/configs/bcm_defconfig F: arch/arm/configs/bcm_defconfig
F: drivers/mmc/host/sdhci_bcm_kona.c F: drivers/mmc/host/sdhci_bcm_kona.c
@ -2245,12 +2246,6 @@ L: linux-usb@vger.kernel.org
S: Maintained S: Maintained
F: drivers/usb/host/ohci-ep93xx.c F: drivers/usb/host/ohci-ep93xx.c
CIRRUS LOGIC CS4270 SOUND DRIVER
M: Timur Tabi <timur@tabi.org>
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
S: Odd Fixes
F: sound/soc/codecs/cs4270*
CIRRUS LOGIC AUDIO CODEC DRIVERS CIRRUS LOGIC AUDIO CODEC DRIVERS
M: Brian Austin <brian.austin@cirrus.com> M: Brian Austin <brian.austin@cirrus.com>
M: Paul Handrigan <Paul.Handrigan@cirrus.com> M: Paul Handrigan <Paul.Handrigan@cirrus.com>
@ -3485,6 +3480,12 @@ S: Maintained
F: drivers/extcon/ F: drivers/extcon/
F: Documentation/extcon/ F: Documentation/extcon/
EXYNOS DP DRIVER
M: Jingoo Han <jg1.han@samsung.com>
L: dri-devel@lists.freedesktop.org
S: Maintained
F: drivers/gpu/drm/exynos/exynos_dp*
EXYNOS MIPI DISPLAY DRIVERS EXYNOS MIPI DISPLAY DRIVERS
M: Inki Dae <inki.dae@samsung.com> M: Inki Dae <inki.dae@samsung.com>
M: Donghwa Lee <dh09.lee@samsung.com> M: Donghwa Lee <dh09.lee@samsung.com>
@ -3550,7 +3551,7 @@ F: include/scsi/libfcoe.h
F: include/uapi/scsi/fc/ F: include/uapi/scsi/fc/
FILE LOCKING (flock() and fcntl()/lockf()) FILE LOCKING (flock() and fcntl()/lockf())
M: Jeff Layton <jlayton@redhat.com> M: Jeff Layton <jlayton@poochiereds.net>
M: J. Bruce Fields <bfields@fieldses.org> M: J. Bruce Fields <bfields@fieldses.org>
L: linux-fsdevel@vger.kernel.org L: linux-fsdevel@vger.kernel.org
S: Maintained S: Maintained
@ -4812,6 +4813,14 @@ L: linux-kernel@vger.kernel.org
S: Maintained S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
F: kernel/irq/ F: kernel/irq/
IRQCHIP DRIVERS
M: Thomas Gleixner <tglx@linutronix.de>
M: Jason Cooper <jason@lakedaemon.net>
L: linux-kernel@vger.kernel.org
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
T: git git://git.infradead.org/users/jcooper/linux.git irqchip/core
F: drivers/irqchip/ F: drivers/irqchip/
IRQ DOMAINS (IRQ NUMBER MAPPING LIBRARY) IRQ DOMAINS (IRQ NUMBER MAPPING LIBRARY)
@ -5108,14 +5117,19 @@ F: drivers/s390/kvm/
KERNEL VIRTUAL MACHINE (KVM) FOR ARM KERNEL VIRTUAL MACHINE (KVM) FOR ARM
M: Christoffer Dall <christoffer.dall@linaro.org> M: Christoffer Dall <christoffer.dall@linaro.org>
M: Marc Zyngier <marc.zyngier@arm.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: kvmarm@lists.cs.columbia.edu L: kvmarm@lists.cs.columbia.edu
W: http://systems.cs.columbia.edu/projects/kvm-arm W: http://systems.cs.columbia.edu/projects/kvm-arm
S: Supported S: Supported
F: arch/arm/include/uapi/asm/kvm* F: arch/arm/include/uapi/asm/kvm*
F: arch/arm/include/asm/kvm* F: arch/arm/include/asm/kvm*
F: arch/arm/kvm/ F: arch/arm/kvm/
F: virt/kvm/arm/
F: include/kvm/arm_*
KERNEL VIRTUAL MACHINE FOR ARM64 (KVM/arm64) KERNEL VIRTUAL MACHINE FOR ARM64 (KVM/arm64)
M: Christoffer Dall <christoffer.dall@linaro.org>
M: Marc Zyngier <marc.zyngier@arm.com> M: Marc Zyngier <marc.zyngier@arm.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: kvmarm@lists.cs.columbia.edu L: kvmarm@lists.cs.columbia.edu
@ -5479,15 +5493,15 @@ F: Documentation/hwmon/ltc4261
F: drivers/hwmon/ltc4261.c F: drivers/hwmon/ltc4261.c
LTP (Linux Test Project) LTP (Linux Test Project)
M: Shubham Goyal <shubham@linux.vnet.ibm.com>
M: Mike Frysinger <vapier@gentoo.org> M: Mike Frysinger <vapier@gentoo.org>
M: Cyril Hrubis <chrubis@suse.cz> M: Cyril Hrubis <chrubis@suse.cz>
M: Caspar Zhang <caspar@casparzhang.com>
M: Wanlong Gao <gaowanlong@cn.fujitsu.com> M: Wanlong Gao <gaowanlong@cn.fujitsu.com>
M: Jan Stancek <jstancek@redhat.com>
M: Stanislav Kholmanskikh <stanislav.kholmanskikh@oracle.com>
M: Alexey Kodanev <alexey.kodanev@oracle.com>
L: ltp-list@lists.sourceforge.net (subscribers-only) L: ltp-list@lists.sourceforge.net (subscribers-only)
W: http://ltp.sourceforge.net/ W: http://linux-test-project.github.io/
T: git git://github.com/linux-test-project/ltp.git T: git git://github.com/linux-test-project/ltp.git
T: git git://ltp.git.sourceforge.net/gitroot/ltp/ltp-dev
S: Maintained S: Maintained
M32R ARCHITECTURE M32R ARCHITECTURE
@ -7277,7 +7291,6 @@ F: drivers/video/aty/aty128fb.c
RALINK RT2X00 WIRELESS LAN DRIVER RALINK RT2X00 WIRELESS LAN DRIVER
P: rt2x00 project P: rt2x00 project
M: Ivo van Doorn <IvDoorn@gmail.com> M: Ivo van Doorn <IvDoorn@gmail.com>
M: Gertjan van Wingerde <gwingerde@gmail.com>
M: Helmut Schaa <helmut.schaa@googlemail.com> M: Helmut Schaa <helmut.schaa@googlemail.com>
L: linux-wireless@vger.kernel.org L: linux-wireless@vger.kernel.org
L: users@rt2x00.serialmonkey.com (moderated for non-subscribers) L: users@rt2x00.serialmonkey.com (moderated for non-subscribers)
@ -7293,7 +7306,7 @@ F: Documentation/blockdev/ramdisk.txt
F: drivers/block/brd.c F: drivers/block/brd.c
RANDOM NUMBER DRIVER RANDOM NUMBER DRIVER
M: Theodore Ts'o" <tytso@mit.edu> M: "Theodore Ts'o" <tytso@mit.edu>
S: Maintained S: Maintained
F: drivers/char/random.c F: drivers/char/random.c
@ -7674,7 +7687,6 @@ F: drivers/clk/samsung/
SAMSUNG SXGBE DRIVERS SAMSUNG SXGBE DRIVERS
M: Byungho An <bh74.an@samsung.com> M: Byungho An <bh74.an@samsung.com>
M: Girish K S <ks.giri@samsung.com> M: Girish K S <ks.giri@samsung.com>
M: Siva Reddy Kallam <siva.kallam@samsung.com>
M: Vipul Pandya <vipul.pandya@samsung.com> M: Vipul Pandya <vipul.pandya@samsung.com>
S: Supported S: Supported
L: netdev@vger.kernel.org L: netdev@vger.kernel.org
@ -9098,6 +9110,9 @@ F: arch/um/os-Linux/drivers/
TURBOCHANNEL SUBSYSTEM TURBOCHANNEL SUBSYSTEM
M: "Maciej W. Rozycki" <macro@linux-mips.org> M: "Maciej W. Rozycki" <macro@linux-mips.org>
M: Ralf Baechle <ralf@linux-mips.org>
L: linux-mips@linux-mips.org
Q: http://patchwork.linux-mips.org/project/linux-mips/list/
S: Maintained S: Maintained
F: drivers/tc/ F: drivers/tc/
F: include/linux/tc.h F: include/linux/tc.h
@ -9951,7 +9966,7 @@ F: drivers/net/hamradio/*scc.c
F: drivers/net/hamradio/z8530.h F: drivers/net/hamradio/z8530.h
ZBUD COMPRESSED PAGE ALLOCATOR ZBUD COMPRESSED PAGE ALLOCATOR
M: Seth Jennings <sjenning@linux.vnet.ibm.com> M: Seth Jennings <sjennings@variantweb.net>
L: linux-mm@kvack.org L: linux-mm@kvack.org
S: Maintained S: Maintained
F: mm/zbud.c F: mm/zbud.c
@ -9996,7 +10011,7 @@ F: mm/zsmalloc.c
F: include/linux/zsmalloc.h F: include/linux/zsmalloc.h
ZSWAP COMPRESSED SWAP CACHING ZSWAP COMPRESSED SWAP CACHING
M: Seth Jennings <sjenning@linux.vnet.ibm.com> M: Seth Jennings <sjennings@variantweb.net>
L: linux-mm@kvack.org L: linux-mm@kvack.org
S: Maintained S: Maintained
F: mm/zswap.c F: mm/zswap.c

2
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 3 VERSION = 3
PATCHLEVEL = 15 PATCHLEVEL = 15
SUBLEVEL = 0 SUBLEVEL = 0
EXTRAVERSION = -rc3 EXTRAVERSION = -rc6
NAME = Shuffling Zombie Juror NAME = Shuffling Zombie Juror
# *DOCUMENTATION* # *DOCUMENTATION*

8
arch/arc/kernel/entry.S
View File

@ -614,11 +614,13 @@ resume_user_mode_begin:
resume_kernel_mode: resume_kernel_mode:
#ifdef CONFIG_PREEMPT ; Disable Interrupts from this point on
; CONFIG_PREEMPT: This is a must for preempt_schedule_irq()
; This is a must for preempt_schedule_irq() ; !CONFIG_PREEMPT: To ensure restore_regs is intr safe
IRQ_DISABLE r9 IRQ_DISABLE r9
#ifdef CONFIG_PREEMPT
; Can't preempt if preemption disabled ; Can't preempt if preemption disabled
GET_CURR_THR_INFO_FROM_SP r10 GET_CURR_THR_INFO_FROM_SP r10
ld r8, [r10, THREAD_INFO_PREEMPT_COUNT] ld r8, [r10, THREAD_INFO_PREEMPT_COUNT]

6
arch/arm/boot/dts/am33xx.dtsi
View File

@ -144,7 +144,7 @@
compatible = "ti,edma3"; compatible = "ti,edma3";
ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
reg = <0x49000000 0x10000>, reg = <0x49000000 0x10000>,
<0x44e10f90 0x10>; <0x44e10f90 0x40>;
interrupts = <12 13 14>; interrupts = <12 13 14>;
#dma-cells = <1>; #dma-cells = <1>;
dma-channels = <64>; dma-channels = <64>;
@ -802,7 +802,7 @@
<0x46000000 0x400000>; <0x46000000 0x400000>;
reg-names = "mpu", "dat"; reg-names = "mpu", "dat";
interrupts = <80>, <81>; interrupts = <80>, <81>;
interrupts-names = "tx", "rx"; interrupt-names = "tx", "rx";
status = "disabled"; status = "disabled";
dmas = <&edma 8>, dmas = <&edma 8>,
<&edma 9>; <&edma 9>;
@ -816,7 +816,7 @@
<0x46400000 0x400000>; <0x46400000 0x400000>;
reg-names = "mpu", "dat"; reg-names = "mpu", "dat";
interrupts = <82>, <83>; interrupts = <82>, <83>;
interrupts-names = "tx", "rx"; interrupt-names = "tx", "rx";
status = "disabled"; status = "disabled";
dmas = <&edma 10>, dmas = <&edma 10>,
<&edma 11>; <&edma 11>;

16
arch/arm/boot/dts/am3517.dtsi
View File

@ -62,5 +62,21 @@
}; };
}; };
&iva {
status = "disabled";
};
&mailbox {
status = "disabled";
};
&mmu_isp {
status = "disabled";
};
&smartreflex_mpu_iva {
status = "disabled";
};
/include/ "am35xx-clocks.dtsi" /include/ "am35xx-clocks.dtsi"
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"

4
arch/arm/boot/dts/am4372.dtsi
View File

@ -691,7 +691,7 @@
<0x46000000 0x400000>; <0x46000000 0x400000>;
reg-names = "mpu", "dat"; reg-names = "mpu", "dat";
interrupts = <80>, <81>; interrupts = <80>, <81>;
interrupts-names = "tx", "rx"; interrupt-names = "tx", "rx";
status = "disabled"; status = "disabled";
dmas = <&edma 8>, dmas = <&edma 8>,
<&edma 9>; <&edma 9>;
@ -705,7 +705,7 @@
<0x46400000 0x400000>; <0x46400000 0x400000>;
reg-names = "mpu", "dat"; reg-names = "mpu", "dat";
interrupts = <82>, <83>; interrupts = <82>, <83>;
interrupts-names = "tx", "rx"; interrupt-names = "tx", "rx";
status = "disabled"; status = "disabled";
dmas = <&edma 10>, dmas = <&edma 10>,
<&edma 11>; <&edma 11>;

5
arch/arm/boot/dts/am437x-gp-evm.dts
View File

@ -117,6 +117,11 @@
status = "okay"; status = "okay";
}; };
&gpio5 {
status = "okay";
ti,no-reset-on-init;
};
&mmc1 { &mmc1 {
status = "okay"; status = "okay";
vmmc-supply = <&vmmcsd_fixed>; vmmc-supply = <&vmmcsd_fixed>;

1
arch/arm/boot/dts/armada-370-db.dts
View File

@ -67,6 +67,7 @@
i2c@11000 { i2c@11000 {
pinctrl-0 = <&i2c0_pins>; pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
clock-frequency = <100000>;
status = "okay"; status = "okay";
audio_codec: audio-codec@4a { audio_codec: audio-codec@4a {
compatible = "cirrus,cs42l51"; compatible = "cirrus,cs42l51";

5
arch/arm/boot/dts/armada-375-db.dts
View File

@ -79,6 +79,11 @@
}; };
}; };
sata@a0000 {
status = "okay";
nr-ports = <2>;
};
nand: nand@d0000 { nand: nand@d0000 {
pinctrl-0 = <&nand_pins>; pinctrl-0 = <&nand_pins>;
pinctrl-names = "default"; pinctrl-names = "default";

2
arch/arm/boot/dts/armada-xp-db.dts
View File

@ -49,7 +49,7 @@
/* Device Bus parameters are required */ /* Device Bus parameters are required */
/* Read parameters */ /* Read parameters */
devbus,bus-width = <8>; devbus,bus-width = <16>;
devbus,turn-off-ps = <60000>; devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>; devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>; devbus,acc-first-ps = <124000>;

10
arch/arm/boot/dts/armada-xp-gp.dts
View File

@ -59,7 +59,7 @@
/* Device Bus parameters are required */ /* Device Bus parameters are required */
/* Read parameters */ /* Read parameters */
devbus,bus-width = <8>; devbus,bus-width = <16>;
devbus,turn-off-ps = <60000>; devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>; devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>; devbus,acc-first-ps = <124000>;
@ -146,22 +146,22 @@
ethernet@70000 { ethernet@70000 {
status = "okay"; status = "okay";
phy = <&phy0>; phy = <&phy0>;
phy-mode = "rgmii-id"; phy-mode = "qsgmii";
}; };
ethernet@74000 { ethernet@74000 {
status = "okay"; status = "okay";
phy = <&phy1>; phy = <&phy1>;
phy-mode = "rgmii-id"; phy-mode = "qsgmii";
}; };
ethernet@30000 { ethernet@30000 {
status = "okay"; status = "okay";
phy = <&phy2>; phy = <&phy2>;
phy-mode = "rgmii-id"; phy-mode = "qsgmii";
}; };
ethernet@34000 { ethernet@34000 {
status = "okay"; status = "okay";
phy = <&phy3>; phy = <&phy3>;
phy-mode = "rgmii-id"; phy-mode = "qsgmii";
}; };
/* Front-side USB slot */ /* Front-side USB slot */

2
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
View File

@ -39,7 +39,7 @@
/* Device Bus parameters are required */ /* Device Bus parameters are required */
/* Read parameters */ /* Read parameters */
devbus,bus-width = <8>; devbus,bus-width = <16>;
devbus,turn-off-ps = <60000>; devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>; devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>; devbus,acc-first-ps = <124000>;

4
arch/arm/boot/dts/at91-sama5d3_xplained.dts
View File

@ -34,7 +34,7 @@
}; };
spi0: spi@f0004000 { spi0: spi@f0004000 {
cs-gpios = <&pioD 13 0>; cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>;
status = "okay"; status = "okay";
}; };
@ -79,7 +79,7 @@
}; };
spi1: spi@f8008000 { spi1: spi@f8008000 {
cs-gpios = <&pioC 25 0>, <0>, <0>, <&pioD 16 0>; cs-gpios = <&pioC 25 0>;
status = "okay"; status = "okay";
}; };

2
arch/arm/boot/dts/at91sam9261.dtsi
View File

@ -10,7 +10,7 @@
#include <dt-bindings/pinctrl/at91.h> #include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/at91.h> #include <dt-bindings/clock/at91.h>
/ { / {
model = "Atmel AT91SAM9261 family SoC"; model = "Atmel AT91SAM9261 family SoC";

2
arch/arm/boot/dts/at91sam9rl.dtsi
View File

@ -8,7 +8,7 @@
#include "skeleton.dtsi" #include "skeleton.dtsi"
#include <dt-bindings/pinctrl/at91.h> #include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/clk/at91.h> #include <dt-bindings/clock/at91.h>
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>

2
arch/arm/boot/dts/imx53-mba53.dts
View File

@ -244,7 +244,7 @@
&tve { &tve {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_vga_sync_1>; pinctrl-0 = <&pinctrl_vga_sync_1>;
i2c-ddc-bus = <&i2c3>; ddc-i2c-bus = <&i2c3>;
fsl,tve-mode = "vga"; fsl,tve-mode = "vga";
fsl,hsync-pin = <4>; fsl,hsync-pin = <4>;
fsl,vsync-pin = <6>; fsl,vsync-pin = <6>;

2
arch/arm/boot/dts/imx53.dtsi
View File

@ -115,7 +115,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,imx53-ipu"; compatible = "fsl,imx53-ipu";
reg = <0x18000000 0x080000000>; reg = <0x18000000 0x08000000>;
interrupts = <11 10>; interrupts = <11 10>;
clocks = <&clks IMX5_CLK_IPU_GATE>, clocks = <&clks IMX5_CLK_IPU_GATE>,
<&clks IMX5_CLK_IPU_DI0_GATE>, <&clks IMX5_CLK_IPU_DI0_GATE>,

18
arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
View File

@ -30,6 +30,16 @@
bootargs = "console=ttyS0,115200n8 earlyprintk"; bootargs = "console=ttyS0,115200n8 earlyprintk";
}; };
mbus {
pcie-controller {
status = "okay";
pcie@1,0 {
status = "okay";
};
};
};
ocp@f1000000 { ocp@f1000000 {
pinctrl@10000 { pinctrl@10000 {
pmx_usb_led: pmx-usb-led { pmx_usb_led: pmx-usb-led {
@ -73,14 +83,6 @@
ehci@50000 { ehci@50000 {
status = "okay"; status = "okay";
}; };
pcie-controller {
status = "okay";
pcie@1,0 {
status = "okay";
};
};
}; };
gpio-leds { gpio-leds {

18
arch/arm/boot/dts/kirkwood-nsa310-common.dtsi
View File

@ -4,6 +4,16 @@
/ { / {
model = "ZyXEL NSA310"; model = "ZyXEL NSA310";
mbus {
pcie-controller {
status = "okay";
pcie@1,0 {
status = "okay";
};
};
};
ocp@f1000000 { ocp@f1000000 {
pinctrl: pinctrl@10000 { pinctrl: pinctrl@10000 {
@ -26,14 +36,6 @@
status = "okay"; status = "okay";
nr-ports = <2>; nr-ports = <2>;
}; };
pcie-controller {
status = "okay";
pcie@1,0 {
status = "okay";
};
};
}; };
gpio_poweroff { gpio_poweroff {

5
arch/arm/boot/dts/kirkwood-t5325.dts
View File

@ -127,11 +127,6 @@
i2c@11000 { i2c@11000 {
status = "okay"; status = "okay";
alc5621: alc5621@1a {
compatible = "realtek,alc5621";
reg = <0x1a>;
};
}; };
serial@12000 { serial@12000 {

19
arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
View File

@ -24,11 +24,10 @@
compatible = "smsc,lan9221", "smsc,lan9115"; compatible = "smsc,lan9221", "smsc,lan9115";
bank-width = <2>; bank-width = <2>;
gpmc,mux-add-data; gpmc,mux-add-data;
gpmc,cs-on-ns = <0>; gpmc,cs-on-ns = <1>;
gpmc,cs-rd-off-ns = <186>; gpmc,cs-rd-off-ns = <180>;
gpmc,cs-wr-off-ns = <186>; gpmc,cs-wr-off-ns = <180>;
gpmc,adv-on-ns = <12>; gpmc,adv-rd-off-ns = <18>;
gpmc,adv-rd-off-ns = <48>;
gpmc,adv-wr-off-ns = <48>; gpmc,adv-wr-off-ns = <48>;
gpmc,oe-on-ns = <54>; gpmc,oe-on-ns = <54>;
gpmc,oe-off-ns = <168>; gpmc,oe-off-ns = <168>;
@ -36,12 +35,10 @@
gpmc,we-off-ns = <168>; gpmc,we-off-ns = <168>;
gpmc,rd-cycle-ns = <186>; gpmc,rd-cycle-ns = <186>;
gpmc,wr-cycle-ns = <186>; gpmc,wr-cycle-ns = <186>;
gpmc,access-ns = <114>; gpmc,access-ns = <144>;
gpmc,page-burst-access-ns = <6>; gpmc,page-burst-access-ns = <24>;
gpmc,bus-turnaround-ns = <12>; gpmc,bus-turnaround-ns = <90>;
gpmc,cycle2cycle-delay-ns = <18>; gpmc,cycle2cycle-delay-ns = <90>;
gpmc,wr-data-mux-bus-ns = <90>;
gpmc,wr-access-ns = <186>;
gpmc,cycle2cycle-samecsen; gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen; gpmc,cycle2cycle-diffcsen;
vddvario-supply = <&vddvario>; vddvario-supply = <&vddvario>;

7
arch/arm/boot/dts/omap2.dtsi
View File

@ -71,13 +71,6 @@
interrupts = <58>; interrupts = <58>;
}; };
mailbox: mailbox@48094000 {
compatible = "ti,omap2-mailbox";
ti,hwmods = "mailbox";
reg = <0x48094000 0x200>;
interrupts = <26>;
};
intc: interrupt-controller@1 { intc: interrupt-controller@1 {
compatible = "ti,omap2-intc"; compatible = "ti,omap2-intc";
interrupt-controller; interrupt-controller;

8
arch/arm/boot/dts/omap2420.dtsi
View File

@ -125,6 +125,14 @@
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
mailbox: mailbox@48094000 {
compatible = "ti,omap2-mailbox";
reg = <0x48094000 0x200>;
interrupts = <26>, <34>;
interrupt-names = "dsp", "iva";
ti,hwmods = "mailbox";
};
timer1: timer@48028000 { timer1: timer@48028000 {
compatible = "ti,omap2420-timer"; compatible = "ti,omap2420-timer";
reg = <0x48028000 0x400>; reg = <0x48028000 0x400>;

7
arch/arm/boot/dts/omap2430.dtsi
View File

@ -216,6 +216,13 @@
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
mailbox: mailbox@48094000 {
compatible = "ti,omap2-mailbox";
reg = <0x48094000 0x200>;
interrupts = <26>;
ti,hwmods = "mailbox";
};
timer1: timer@49018000 { timer1: timer@49018000 {
compatible = "ti,omap2420-timer"; compatible = "ti,omap2420-timer";
reg = <0x49018000 0x400>; reg = <0x49018000 0x400>;

66
arch/arm/boot/dts/omap3-cm-t3x30.dtsi
View File

@ -10,18 +10,6 @@
cpu0-supply = <&vcc>; cpu0-supply = <&vcc>;
}; };
}; };
vddvario: regulator-vddvario {
compatible = "regulator-fixed";
regulator-name = "vddvario";
regulator-always-on;
};
vdd33a: regulator-vdd33a {
compatible = "regulator-fixed";
regulator-name = "vdd33a";
regulator-always-on;
};
}; };
&omap3_pmx_core { &omap3_pmx_core {
@ -35,58 +23,34 @@
hsusb0_pins: pinmux_hsusb0_pins { hsusb0_pins: pinmux_hsusb0_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */
OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */
OMAP3_CORE1_IOPAD(0x21a4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */
OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */
OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data0.hsusb2_data0 */ OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data0.hsusb2_data0 */
OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */
OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */
OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data3 */ OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data3 */
OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data4 */ OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data4 */
OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data5 */ OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data5 */
OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data6 */ OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data6 */
OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */
>; >;
}; };
}; };
#include "omap-gpmc-smsc911x.dtsi"
&gpmc { &gpmc {
ranges = <5 0 0x2c000000 0x01000000>; ranges = <5 0 0x2c000000 0x01000000>;
smsc1: ethernet@5,0 { smsc1: ethernet@gpmc {
compatible = "smsc,lan9221", "smsc,lan9115"; compatible = "smsc,lan9221", "smsc,lan9115";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&smsc1_pins>; pinctrl-0 = <&smsc1_pins>;
interrupt-parent = <&gpio6>; interrupt-parent = <&gpio6>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
reg = <5 0 0xff>; reg = <5 0 0xff>;
bank-width = <2>;
gpmc,mux-add-data;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <186>;
gpmc,cs-wr-off-ns = <186>;
gpmc,adv-on-ns = <12>;
gpmc,adv-rd-off-ns = <48>;
gpmc,adv-wr-off-ns = <48>;
gpmc,oe-on-ns = <54>;
gpmc,oe-off-ns = <168>;
gpmc,we-on-ns = <54>;
gpmc,we-off-ns = <168>;
gpmc,rd-cycle-ns = <186>;
gpmc,wr-cycle-ns = <186>;
gpmc,access-ns = <114>;
gpmc,page-burst-access-ns = <6>;
gpmc,bus-turnaround-ns = <12>;
gpmc,cycle2cycle-delay-ns = <18>;
gpmc,wr-data-mux-bus-ns = <90>;
gpmc,wr-access-ns = <186>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen;
vddvario-supply = <&vddvario>;
vdd33a-supply = <&vdd33a>;
reg-io-width = <4>;
smsc,save-mac-address;
}; };
}; };

2
arch/arm/boot/dts/omap3-igep.dtsi
View File

@ -107,7 +107,7 @@
>; >;
}; };
smsc911x_pins: pinmux_smsc911x_pins { smsc9221_pins: pinmux_smsc9221_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x1a2 (PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ 0x1a2 (PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
>; >;

4
arch/arm/boot/dts/omap3-igep0020.dts
View File

@ -10,7 +10,7 @@
*/ */
#include "omap3-igep.dtsi" #include "omap3-igep.dtsi"
#include "omap-gpmc-smsc911x.dtsi" #include "omap-gpmc-smsc9221.dtsi"
/ { / {
model = "IGEPv2 (TI OMAP AM/DM37x)"; model = "IGEPv2 (TI OMAP AM/DM37x)";
@ -248,7 +248,7 @@
ethernet@gpmc { ethernet@gpmc {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&smsc911x_pins>; pinctrl-0 = <&smsc9221_pins>;
reg = <5 0 0xff>; reg = <5 0 0xff>;
interrupt-parent = <&gpio6>; interrupt-parent = <&gpio6>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>; interrupts = <16 IRQ_TYPE_LEVEL_LOW>;

37
arch/arm/boot/dts/omap3-sb-t35.dtsi
View File

@ -2,20 +2,6 @@
* Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730 * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730
*/ */
/ {
vddvario_sb_t35: regulator-vddvario-sb-t35 {
compatible = "regulator-fixed";
regulator-name = "vddvario";
regulator-always-on;
};
vdd33a_sb_t35: regulator-vdd33a-sb-t35 {
compatible = "regulator-fixed";
regulator-name = "vdd33a";
regulator-always-on;
};
};
&omap3_pmx_core { &omap3_pmx_core {
smsc2_pins: pinmux_smsc2_pins { smsc2_pins: pinmux_smsc2_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
@ -37,11 +23,10 @@
reg = <4 0 0xff>; reg = <4 0 0xff>;
bank-width = <2>; bank-width = <2>;
gpmc,mux-add-data; gpmc,mux-add-data;
gpmc,cs-on-ns = <0>; gpmc,cs-on-ns = <1>;
gpmc,cs-rd-off-ns = <186>; gpmc,cs-rd-off-ns = <180>;
gpmc,cs-wr-off-ns = <186>; gpmc,cs-wr-off-ns = <180>;
gpmc,adv-on-ns = <12>; gpmc,adv-rd-off-ns = <18>;
gpmc,adv-rd-off-ns = <48>;
gpmc,adv-wr-off-ns = <48>; gpmc,adv-wr-off-ns = <48>;
gpmc,oe-on-ns = <54>; gpmc,oe-on-ns = <54>;
gpmc,oe-off-ns = <168>; gpmc,oe-off-ns = <168>;
@ -49,16 +34,14 @@
gpmc,we-off-ns = <168>; gpmc,we-off-ns = <168>;
gpmc,rd-cycle-ns = <186>; gpmc,rd-cycle-ns = <186>;
gpmc,wr-cycle-ns = <186>; gpmc,wr-cycle-ns = <186>;
gpmc,access-ns = <114>; gpmc,access-ns = <144>;
gpmc,page-burst-access-ns = <6>; gpmc,page-burst-access-ns = <24>;
gpmc,bus-turnaround-ns = <12>; gpmc,bus-turnaround-ns = <90>;
gpmc,cycle2cycle-delay-ns = <18>; gpmc,cycle2cycle-delay-ns = <90>;
gpmc,wr-data-mux-bus-ns = <90>;
gpmc,wr-access-ns = <186>;
gpmc,cycle2cycle-samecsen; gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen; gpmc,cycle2cycle-diffcsen;
vddvario-supply = <&vddvario_sb_t35>; vddvario-supply = <&vddvario>;
vdd33a-supply = <&vdd33a_sb_t35>; vdd33a-supply = <&vdd33a>;
reg-io-width = <4>; reg-io-width = <4>;
smsc,save-mac-address; smsc,save-mac-address;
}; };

13
arch/arm/boot/dts/omap3-sbc-t3517.dts
View File

@ -8,6 +8,19 @@
/ { / {
model = "CompuLab SBC-T3517 with CM-T3517"; model = "CompuLab SBC-T3517 with CM-T3517";
compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3";
/* Only one GPMC smsc9220 on SBC-T3517, CM-T3517 uses am35x Ethernet */
vddvario: regulator-vddvario-sb-t35 {
compatible = "regulator-fixed";
regulator-name = "vddvario";
regulator-always-on;
};
vdd33a: regulator-vdd33a-sb-t35 {
compatible = "regulator-fixed";
regulator-name = "vdd33a";
regulator-always-on;
};
}; };
&omap3_pmx_core { &omap3_pmx_core {

2
arch/arm/boot/dts/omap3.dtsi
View File

@ -61,7 +61,7 @@
ti,hwmods = "mpu"; ti,hwmods = "mpu";
}; };
iva { iva: iva {
compatible = "ti,iva2.2"; compatible = "ti,iva2.2";
ti,hwmods = "iva"; ti,hwmods = "iva";

7
arch/arm/boot/dts/omap5.dtsi
View File

@ -630,6 +630,13 @@
status = "disabled"; status = "disabled";
}; };
mailbox: mailbox@4a0f4000 {
compatible = "ti,omap4-mailbox";
reg = <0x4a0f4000 0x200>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox";
};
timer1: timer@4ae18000 { timer1: timer@4ae18000 {
compatible = "ti,omap5430-timer"; compatible = "ti,omap5430-timer";
reg = <0x4ae18000 0x80>; reg = <0x4ae18000 0x80>;

2
arch/arm/boot/dts/sama5d3.dtsi
View File

@ -13,7 +13,7 @@
#include <dt-bindings/pinctrl/at91.h> #include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/at91.h> #include <dt-bindings/clock/at91.h>
/ { / {
model = "Atmel SAMA5D3 family SoC"; model = "Atmel SAMA5D3 family SoC";

2
arch/arm/boot/dts/sama5d3_mci2.dtsi
View File

@ -9,7 +9,7 @@
#include <dt-bindings/pinctrl/at91.h> #include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clk/at91.h> #include <dt-bindings/clock/at91.h>
/ { / {
ahb { ahb {

2
arch/arm/boot/dts/sama5d3_tcb1.dtsi
View File

@ -9,7 +9,7 @@
#include <dt-bindings/pinctrl/at91.h> #include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clk/at91.h> #include <dt-bindings/clock/at91.h>
/ { / {
aliases { aliases {

2
arch/arm/boot/dts/sama5d3_uart.dtsi
View File

@ -9,7 +9,7 @@
#include <dt-bindings/pinctrl/at91.h> #include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clk/at91.h> #include <dt-bindings/clock/at91.h>
/ { / {
aliases { aliases {

1
arch/arm/boot/dts/ste-ccu8540.dts
View File

@ -18,6 +18,7 @@
compatible = "st-ericsson,ccu8540", "st-ericsson,u8540"; compatible = "st-ericsson,ccu8540", "st-ericsson,u8540";
memory@0 { memory@0 {
device_type = "memory";
reg = <0x20000000 0x1f000000>, <0xc0000000 0x3f000000>; reg = <0x20000000 0x1f000000>, <0xc0000000 0x3f000000>;
}; };

10
arch/arm/boot/dts/stih415-pinctrl.dtsi
View File

@ -49,7 +49,7 @@
reg = <0xfe61f080 0x4>; reg = <0xfe61f080 0x4>;
reg-names = "irqmux"; reg-names = "irqmux";
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
interrupts-names = "irqmux"; interrupt-names = "irqmux";
ranges = <0 0xfe610000 0x5000>; ranges = <0 0xfe610000 0x5000>;
PIO0: gpio@fe610000 { PIO0: gpio@fe610000 {
@ -187,7 +187,7 @@
reg = <0xfee0f080 0x4>; reg = <0xfee0f080 0x4>;
reg-names = "irqmux"; reg-names = "irqmux";
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
interrupts-names = "irqmux"; interrupt-names = "irqmux";
ranges = <0 0xfee00000 0x8000>; ranges = <0 0xfee00000 0x8000>;
PIO5: gpio@fee00000 { PIO5: gpio@fee00000 {
@ -282,7 +282,7 @@
reg = <0xfe82f080 0x4>; reg = <0xfe82f080 0x4>;
reg-names = "irqmux"; reg-names = "irqmux";
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
interrupts-names = "irqmux"; interrupt-names = "irqmux";
ranges = <0 0xfe820000 0x8000>; ranges = <0 0xfe820000 0x8000>;
PIO13: gpio@fe820000 { PIO13: gpio@fe820000 {
@ -423,7 +423,7 @@
reg = <0xfd6bf080 0x4>; reg = <0xfd6bf080 0x4>;
reg-names = "irqmux"; reg-names = "irqmux";
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
interrupts-names = "irqmux"; interrupt-names = "irqmux";
ranges = <0 0xfd6b0000 0x3000>; ranges = <0 0xfd6b0000 0x3000>;
PIO100: gpio@fd6b0000 { PIO100: gpio@fd6b0000 {
@ -460,7 +460,7 @@
reg = <0xfd33f080 0x4>; reg = <0xfd33f080 0x4>;
reg-names = "irqmux"; reg-names = "irqmux";
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
interrupts-names = "irqmux"; interrupt-names = "irqmux";
ranges = <0 0xfd330000 0x5000>; ranges = <0 0xfd330000 0x5000>;
PIO103: gpio@fd330000 { PIO103: gpio@fd330000 {

10
arch/arm/boot/dts/stih416-pinctrl.dtsi
View File

@ -53,7 +53,7 @@
reg = <0xfe61f080 0x4>; reg = <0xfe61f080 0x4>;
reg-names = "irqmux"; reg-names = "irqmux";
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
interrupts-names = "irqmux"; interrupt-names = "irqmux";
ranges = <0 0xfe610000 0x6000>; ranges = <0 0xfe610000 0x6000>;
PIO0: gpio@fe610000 { PIO0: gpio@fe610000 {
@ -201,7 +201,7 @@
reg = <0xfee0f080 0x4>; reg = <0xfee0f080 0x4>;
reg-names = "irqmux"; reg-names = "irqmux";
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
interrupts-names = "irqmux"; interrupt-names = "irqmux";
ranges = <0 0xfee00000 0x10000>; ranges = <0 0xfee00000 0x10000>;
PIO5: gpio@fee00000 { PIO5: gpio@fee00000 {
@ -333,7 +333,7 @@
reg = <0xfe82f080 0x4>; reg = <0xfe82f080 0x4>;
reg-names = "irqmux"; reg-names = "irqmux";
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
interrupts-names = "irqmux"; interrupt-names = "irqmux";
ranges = <0 0xfe820000 0x6000>; ranges = <0 0xfe820000 0x6000>;
PIO13: gpio@fe820000 { PIO13: gpio@fe820000 {
@ -461,7 +461,7 @@
reg = <0xfd6bf080 0x4>; reg = <0xfd6bf080 0x4>;
reg-names = "irqmux"; reg-names = "irqmux";
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
interrupts-names = "irqmux"; interrupt-names = "irqmux";
ranges = <0 0xfd6b0000 0x3000>; ranges = <0 0xfd6b0000 0x3000>;
PIO100: gpio@fd6b0000 { PIO100: gpio@fd6b0000 {
@ -498,7 +498,7 @@
reg = <0xfd33f080 0x4>; reg = <0xfd33f080 0x4>;
reg-names = "irqmux"; reg-names = "irqmux";
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
interrupts-names = "irqmux"; interrupt-names = "irqmux";
ranges = <0 0xfd330000 0x5000>; ranges = <0 0xfd330000 0x5000>;
PIO103: gpio@fd330000 { PIO103: gpio@fd330000 {

14
arch/arm/boot/dts/sun7i-a20.dtsi
View File

@ -87,7 +87,7 @@
pll4: clk@01c20018 { pll4: clk@01c20018 {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "allwinner,sun4i-a10-pll1-clk"; compatible = "allwinner,sun7i-a20-pll4-clk";
reg = <0x01c20018 0x4>; reg = <0x01c20018 0x4>;
clocks = <&osc24M>; clocks = <&osc24M>;
clock-output-names = "pll4"; clock-output-names = "pll4";
@ -109,6 +109,14 @@
clock-output-names = "pll6_sata", "pll6_other", "pll6"; clock-output-names = "pll6_sata", "pll6_other", "pll6";
}; };
pll8: clk@01c20040 {
#clock-cells = <0>;
compatible = "allwinner,sun7i-a20-pll4-clk";
reg = <0x01c20040 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll8";
};
cpu: cpu@01c20054 { cpu: cpu@01c20054 {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "allwinner,sun4i-a10-cpu-clk"; compatible = "allwinner,sun4i-a10-cpu-clk";
@ -805,9 +813,9 @@
status = "disabled"; status = "disabled";
}; };
i2c4: i2c@01c2bc00 { i2c4: i2c@01c2c000 {
compatible = "allwinner,sun4i-i2c"; compatible = "allwinner,sun4i-i2c";
reg = <0x01c2bc00 0x400>; reg = <0x01c2c000 0x400>;
interrupts = <0 89 4>; interrupts = <0 89 4>;
clocks = <&apb1_gates 15>; clocks = <&apb1_gates 15>;
clock-frequency = <100000>; clock-frequency = <100000>;

48
arch/arm/common/edma.c
View File

@ -1423,55 +1423,38 @@ EXPORT_SYMBOL(edma_clear_event);
#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES) #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)
static int edma_of_read_u32_to_s16_array(const struct device_node *np, static int edma_xbar_event_map(struct device *dev, struct device_node *node,
const char *propname, s16 *out_values, struct edma_soc_info *pdata, size_t sz)
size_t sz)
{ {
int ret; const char pname[] = "ti,edma-xbar-event-map";
ret = of_property_read_u16_array(np, propname, out_values, sz);
if (ret)
return ret;
/* Terminate it */
*out_values++ = -1;
*out_values++ = -1;
return 0;
}
static int edma_xbar_event_map(struct device *dev,
struct device_node *node,
struct edma_soc_info *pdata, int len)
{
int ret, i;
struct resource res; struct resource res;
void __iomem *xbar; void __iomem *xbar;
const s16 (*xbar_chans)[2]; s16 (*xbar_chans)[2];
size_t nelm = sz / sizeof(s16);
u32 shift, offset, mux; u32 shift, offset, mux;
int ret, i;
xbar_chans = devm_kzalloc(dev, xbar_chans = devm_kzalloc(dev, (nelm + 2) * sizeof(s16), GFP_KERNEL);
len/sizeof(s16) + 2*sizeof(s16),
GFP_KERNEL);
if (!xbar_chans) if (!xbar_chans)
return -ENOMEM; return -ENOMEM;
ret = of_address_to_resource(node, 1, &res); ret = of_address_to_resource(node, 1, &res);
if (ret) if (ret)
return -EIO; return -ENOMEM;
xbar = devm_ioremap(dev, res.start, resource_size(&res)); xbar = devm_ioremap(dev, res.start, resource_size(&res));
if (!xbar) if (!xbar)
return -ENOMEM; return -ENOMEM;
ret = edma_of_read_u32_to_s16_array(node, ret = of_property_read_u16_array(node, pname, (u16 *)xbar_chans, nelm);
"ti,edma-xbar-event-map",
(s16 *)xbar_chans,
len/sizeof(u32));
if (ret) if (ret)
return -EIO; return -EIO;
for (i = 0; xbar_chans[i][0] != -1; i++) { /* Invalidate last entry for the other user of this mess */
nelm >>= 1;
xbar_chans[nelm][0] = xbar_chans[nelm][1] = -1;
for (i = 0; i < nelm; i++) {
shift = (xbar_chans[i][1] & 0x03) << 3; shift = (xbar_chans[i][1] & 0x03) << 3;
offset = xbar_chans[i][1] & 0xfffffffc; offset = xbar_chans[i][1] & 0xfffffffc;
mux = readl(xbar + offset); mux = readl(xbar + offset);
@ -1480,8 +1463,7 @@ static int edma_xbar_event_map(struct device *dev,
writel(mux, (xbar + offset)); writel(mux, (xbar + offset));
} }
pdata->xbar_chans = xbar_chans; pdata->xbar_chans = (const s16 (*)[2]) xbar_chans;
return 0; return 0;
} }

2
arch/arm/configs/sunxi_defconfig
View File

@ -37,7 +37,7 @@ CONFIG_SUN4I_EMAC=y
# CONFIG_NET_VENDOR_NATSEMI is not set # CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set # CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SMSC is not set # CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_STMICRO is not set CONFIG_STMMAC_ETH=y
# CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_WLAN is not set # CONFIG_WLAN is not set
CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250=y

1
arch/arm/include/asm/xen/page.h
View File

@ -77,7 +77,6 @@ static inline xpaddr_t machine_to_phys(xmaddr_t machine)
} }
/* VIRT <-> MACHINE conversion */ /* VIRT <-> MACHINE conversion */
#define virt_to_machine(v) (phys_to_machine(XPADDR(__pa(v)))) #define virt_to_machine(v) (phys_to_machine(XPADDR(__pa(v))))
#define virt_to_pfn(v) (PFN_DOWN(__pa(v)))
#define virt_to_mfn(v) (pfn_to_mfn(virt_to_pfn(v))) #define virt_to_mfn(v) (pfn_to_mfn(virt_to_pfn(v)))
#define mfn_to_virt(m) (__va(mfn_to_pfn(m) << PAGE_SHIFT)) #define mfn_to_virt(m) (__va(mfn_to_pfn(m) << PAGE_SHIFT))

2
arch/arm/kvm/Kconfig
View File

@ -23,7 +23,7 @@ config KVM
select HAVE_KVM_CPU_RELAX_INTERCEPT select HAVE_KVM_CPU_RELAX_INTERCEPT
select KVM_MMIO select KVM_MMIO
select KVM_ARM_HOST select KVM_ARM_HOST
depends on ARM_VIRT_EXT && ARM_LPAE depends on ARM_VIRT_EXT && ARM_LPAE && !CPU_BIG_ENDIAN
---help--- ---help---
Support hosting virtualized guest machines. You will also Support hosting virtualized guest machines. You will also
need to select one or more of the processor modules below. need to select one or more of the processor modules below.

15
arch/arm/kvm/mmu.c
View File

@ -42,6 +42,8 @@ static unsigned long hyp_idmap_start;
static unsigned long hyp_idmap_end; static unsigned long hyp_idmap_end;
static phys_addr_t hyp_idmap_vector; static phys_addr_t hyp_idmap_vector;
#define pgd_order get_order(PTRS_PER_PGD * sizeof(pgd_t))
#define kvm_pmd_huge(_x) (pmd_huge(_x) || pmd_trans_huge(_x)) #define kvm_pmd_huge(_x) (pmd_huge(_x) || pmd_trans_huge(_x))
static void kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa) static void kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
@ -293,14 +295,14 @@ void free_boot_hyp_pgd(void)
if (boot_hyp_pgd) { if (boot_hyp_pgd) {
unmap_range(NULL, boot_hyp_pgd, hyp_idmap_start, PAGE_SIZE); unmap_range(NULL, boot_hyp_pgd, hyp_idmap_start, PAGE_SIZE);
unmap_range(NULL, boot_hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE); unmap_range(NULL, boot_hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE);
kfree(boot_hyp_pgd); free_pages((unsigned long)boot_hyp_pgd, pgd_order);
boot_hyp_pgd = NULL; boot_hyp_pgd = NULL;
} }
if (hyp_pgd) if (hyp_pgd)
unmap_range(NULL, hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE); unmap_range(NULL, hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE);
kfree(init_bounce_page); free_page((unsigned long)init_bounce_page);
init_bounce_page = NULL; init_bounce_page = NULL;
mutex_unlock(&kvm_hyp_pgd_mutex); mutex_unlock(&kvm_hyp_pgd_mutex);
@ -330,7 +332,7 @@ void free_hyp_pgds(void)
for (addr = VMALLOC_START; is_vmalloc_addr((void*)addr); addr += PGDIR_SIZE) for (addr = VMALLOC_START; is_vmalloc_addr((void*)addr); addr += PGDIR_SIZE)
unmap_range(NULL, hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE); unmap_range(NULL, hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE);
kfree(hyp_pgd); free_pages((unsigned long)hyp_pgd, pgd_order);
hyp_pgd = NULL; hyp_pgd = NULL;
} }
@ -1024,7 +1026,7 @@ int kvm_mmu_init(void)
size_t len = __hyp_idmap_text_end - __hyp_idmap_text_start; size_t len = __hyp_idmap_text_end - __hyp_idmap_text_start;
phys_addr_t phys_base; phys_addr_t phys_base;
init_bounce_page = kmalloc(PAGE_SIZE, GFP_KERNEL); init_bounce_page = (void *)__get_free_page(GFP_KERNEL);
if (!init_bounce_page) { if (!init_bounce_page) {
kvm_err("Couldn't allocate HYP init bounce page\n"); kvm_err("Couldn't allocate HYP init bounce page\n");
err = -ENOMEM; err = -ENOMEM;
@ -1050,8 +1052,9 @@ int kvm_mmu_init(void)
(unsigned long)phys_base); (unsigned long)phys_base);
} }
hyp_pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL); hyp_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, pgd_order);
boot_hyp_pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL); boot_hyp_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, pgd_order);
if (!hyp_pgd || !boot_hyp_pgd) { if (!hyp_pgd || !boot_hyp_pgd) {
kvm_err("Hyp mode PGD not allocated\n"); kvm_err("Hyp mode PGD not allocated\n");
err = -ENOMEM; err = -ENOMEM;

8
arch/arm/mach-omap2/omap-headsmp.S
View File

@ -1,7 +1,7 @@
/* /*
* Secondary CPU startup routine source file. * Secondary CPU startup routine source file.
* *
* Copyright (C) 2009 Texas Instruments, Inc. * Copyright (C) 2009-2014 Texas Instruments, Inc.
* *
* Author: * Author:
* Santosh Shilimkar <santosh.shilimkar@ti.com> * Santosh Shilimkar <santosh.shilimkar@ti.com>
@ -28,9 +28,13 @@
* code. This routine also provides a holding flag into which * code. This routine also provides a holding flag into which
* secondary core is held until we're ready for it to initialise. * secondary core is held until we're ready for it to initialise.
* The primary core will update this flag using a hardware * The primary core will update this flag using a hardware
+ * register AuxCoreBoot0. * register AuxCoreBoot0.
*/ */
ENTRY(omap5_secondary_startup) ENTRY(omap5_secondary_startup)
.arm
THUMB( adr r9, BSYM(wait) ) @ CPU may be entered in ARM mode.
THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
THUMB( .thumb ) @ switch to Thumb now.
wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
ldr r0, [r2] ldr r0, [r2]
mov r0, r0, lsr #5 mov r0, r0, lsr #5

2
arch/arm/mach-orion5x/common.h
View File

@ -21,7 +21,7 @@ struct mv_sata_platform_data;
#define ORION_MBUS_DEVBUS_BOOT_ATTR 0x0f #define ORION_MBUS_DEVBUS_BOOT_ATTR 0x0f
#define ORION_MBUS_DEVBUS_TARGET(cs) 0x01 #define ORION_MBUS_DEVBUS_TARGET(cs) 0x01
#define ORION_MBUS_DEVBUS_ATTR(cs) (~(1 << cs)) #define ORION_MBUS_DEVBUS_ATTR(cs) (~(1 << cs))
#define ORION_MBUS_SRAM_TARGET 0x00 #define ORION_MBUS_SRAM_TARGET 0x09
#define ORION_MBUS_SRAM_ATTR 0x00 #define ORION_MBUS_SRAM_ATTR 0x00
/* /*

3
arch/arm64/boot/dts/apm-storm.dtsi
View File

@ -307,6 +307,7 @@
<0x0 0x1f21e000 0x0 0x1000>, <0x0 0x1f21e000 0x0 0x1000>,
<0x0 0x1f217000 0x0 0x1000>; <0x0 0x1f217000 0x0 0x1000>;
interrupts = <0x0 0x86 0x4>; interrupts = <0x0 0x86 0x4>;
dma-coherent;
status = "disabled"; status = "disabled";
clocks = <&sata01clk 0>; clocks = <&sata01clk 0>;
phys = <&phy1 0>; phys = <&phy1 0>;
@ -321,6 +322,7 @@
<0x0 0x1f22e000 0x0 0x1000>, <0x0 0x1f22e000 0x0 0x1000>,
<0x0 0x1f227000 0x0 0x1000>; <0x0 0x1f227000 0x0 0x1000>;
interrupts = <0x0 0x87 0x4>; interrupts = <0x0 0x87 0x4>;
dma-coherent;
status = "ok"; status = "ok";
clocks = <&sata23clk 0>; clocks = <&sata23clk 0>;
phys = <&phy2 0>; phys = <&phy2 0>;
@ -334,6 +336,7 @@
<0x0 0x1f23d000 0x0 0x1000>, <0x0 0x1f23d000 0x0 0x1000>,
<0x0 0x1f23e000 0x0 0x1000>; <0x0 0x1f23e000 0x0 0x1000>;
interrupts = <0x0 0x88 0x4>; interrupts = <0x0 0x88 0x4>;
dma-coherent;
status = "ok"; status = "ok";
clocks = <&sata45clk 0>; clocks = <&sata45clk 0>;
phys = <&phy3 0>; phys = <&phy3 0>;

1
arch/arm64/include/asm/memory.h
View File

@ -138,6 +138,7 @@ static inline void *phys_to_virt(phys_addr_t x)
#define __pa(x) __virt_to_phys((unsigned long)(x)) #define __pa(x) __virt_to_phys((unsigned long)(x))
#define __va(x) ((void *)__phys_to_virt((phys_addr_t)(x))) #define __va(x) ((void *)__phys_to_virt((phys_addr_t)(x)))
#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) #define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
#define virt_to_pfn(x) __phys_to_pfn(__virt_to_phys(x))
/* /*
* virt_to_page(k) convert a _valid_ virtual address to struct page * * virt_to_page(k) convert a _valid_ virtual address to struct page *

6
arch/arm64/kernel/early_printk.c
View File

@ -143,10 +143,8 @@ static int __init setup_early_printk(char *buf)
} }
/* no options parsing yet */ /* no options parsing yet */
if (paddr) { if (paddr)
set_fixmap_io(FIX_EARLYCON_MEM_BASE, paddr); early_base = (void __iomem *)set_fixmap_offset_io(FIX_EARLYCON_MEM_BASE, paddr);
early_base = (void __iomem *)fix_to_virt(FIX_EARLYCON_MEM_BASE);
}
printch = match->printch; printch = match->printch;
early_console = &early_console_dev; early_console = &early_console_dev;

10
arch/arm64/kernel/irq.c
View File

@ -97,11 +97,15 @@ static bool migrate_one_irq(struct irq_desc *desc)
if (irqd_is_per_cpu(d) || !cpumask_test_cpu(smp_processor_id(), affinity)) if (irqd_is_per_cpu(d) || !cpumask_test_cpu(smp_processor_id(), affinity))
return false; return false;
if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) { if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids)
affinity = cpu_online_mask;
ret = true; ret = true;
}
/*
* when using forced irq_set_affinity we must ensure that the cpu
* being offlined is not present in the affinity mask, it may be
* selected as the target CPU otherwise
*/
affinity = cpu_online_mask;
c = irq_data_get_irq_chip(d); c = irq_data_get_irq_chip(d);
if (!c->irq_set_affinity) if (!c->irq_set_affinity)
pr_debug("IRQ%u: unable to set affinity\n", d->irq); pr_debug("IRQ%u: unable to set affinity\n", d->irq);

2
arch/arm64/kernel/setup.c
View File

@ -396,7 +396,7 @@ static int __init arm64_device_init(void)
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
return 0; return 0;
} }
arch_initcall(arm64_device_init); arch_initcall_sync(arm64_device_init);
static DEFINE_PER_CPU(struct cpu, cpu_data); static DEFINE_PER_CPU(struct cpu, cpu_data);

35
arch/arm64/mm/dma-mapping.c
View File

@ -22,8 +22,11 @@
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/dma-mapping.h> #include <linux/dma-mapping.h>
#include <linux/dma-contiguous.h> #include <linux/dma-contiguous.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/vmalloc.h> #include <linux/vmalloc.h>
#include <linux/swiotlb.h> #include <linux/swiotlb.h>
#include <linux/amba/bus.h>
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
@ -305,17 +308,45 @@ struct dma_map_ops coherent_swiotlb_dma_ops = {
}; };
EXPORT_SYMBOL(coherent_swiotlb_dma_ops); EXPORT_SYMBOL(coherent_swiotlb_dma_ops);
static int dma_bus_notifier(struct notifier_block *nb,
unsigned long event, void *_dev)
{
struct device *dev = _dev;
if (event != BUS_NOTIFY_ADD_DEVICE)
return NOTIFY_DONE;
if (of_property_read_bool(dev->of_node, "dma-coherent"))
set_dma_ops(dev, &coherent_swiotlb_dma_ops);
return NOTIFY_OK;
}
static struct notifier_block platform_bus_nb = {
.notifier_call = dma_bus_notifier,
};
static struct notifier_block amba_bus_nb = {
.notifier_call = dma_bus_notifier,
};
extern int swiotlb_late_init_with_default_size(size_t default_size); extern int swiotlb_late_init_with_default_size(size_t default_size);
static int __init swiotlb_late_init(void) static int __init swiotlb_late_init(void)
{ {
size_t swiotlb_size = min(SZ_64M, MAX_ORDER_NR_PAGES << PAGE_SHIFT); size_t swiotlb_size = min(SZ_64M, MAX_ORDER_NR_PAGES << PAGE_SHIFT);
dma_ops = &coherent_swiotlb_dma_ops; /*
* These must be registered before of_platform_populate().
*/
bus_register_notifier(&platform_bus_type, &platform_bus_nb);
bus_register_notifier(&amba_bustype, &amba_bus_nb);
dma_ops = &noncoherent_swiotlb_dma_ops;
return swiotlb_late_init_with_default_size(swiotlb_size); return swiotlb_late_init_with_default_size(swiotlb_size);
} }
subsys_initcall(swiotlb_late_init); arch_initcall(swiotlb_late_init);
#define PREALLOC_DMA_DEBUG_ENTRIES 4096 #define PREALLOC_DMA_DEBUG_ENTRIES 4096

4
arch/arm64/mm/hugetlbpage.c
View File

@ -51,7 +51,11 @@ int pmd_huge(pmd_t pmd)
int pud_huge(pud_t pud) int pud_huge(pud_t pud)
{ {
#ifndef __PAGETABLE_PMD_FOLDED
return !(pud_val(pud) & PUD_TABLE_BIT); return !(pud_val(pud) & PUD_TABLE_BIT);
#else
return 0;
#endif
} }
int pmd_huge_support(void) int pmd_huge_support(void)

3
arch/arm64/mm/mmu.c
View File

@ -374,6 +374,9 @@ int kern_addr_valid(unsigned long addr)
if (pmd_none(*pmd)) if (pmd_none(*pmd))
return 0; return 0;
if (pmd_sect(*pmd))
return pfn_valid(pmd_pfn(*pmd));
pte = pte_offset_kernel(pmd, addr); pte = pte_offset_kernel(pmd, addr);
if (pte_none(*pte)) if (pte_none(*pte))
return 0; return 0;

37
arch/hexagon/include/asm/barrier.h
View File

@ -1,37 +0,0 @@
/*
* Memory barrier definitions for the Hexagon architecture
*
* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#ifndef _ASM_BARRIER_H
#define _ASM_BARRIER_H
#define rmb() barrier()
#define read_barrier_depends() barrier()
#define wmb() barrier()
#define mb() barrier()
#define smp_rmb() barrier()
#define smp_read_barrier_depends() barrier()
#define smp_wmb() barrier()
#define smp_mb() barrier()
/* Set a value and use a memory barrier. Used by the scheduler somewhere. */
#define set_mb(var, value) \
do { var = value; mb(); } while (0)
#endif /* _ASM_BARRIER_H */

2
arch/ia64/include/asm/unistd.h
View File

@ -11,7 +11,7 @@
#define NR_syscalls 314 /* length of syscall table */ #define NR_syscalls 315 /* length of syscall table */
/* /*
* The following defines stop scripts/checksyscalls.sh from complaining about * The following defines stop scripts/checksyscalls.sh from complaining about

1
arch/ia64/include/uapi/asm/unistd.h
View File

@ -327,5 +327,6 @@
#define __NR_finit_module 1335 #define __NR_finit_module 1335
#define __NR_sched_setattr 1336 #define __NR_sched_setattr 1336
#define __NR_sched_getattr 1337 #define __NR_sched_getattr 1337
#define __NR_renameat2 1338
#endif /* _UAPI_ASM_IA64_UNISTD_H */ #endif /* _UAPI_ASM_IA64_UNISTD_H */

1
arch/ia64/kernel/entry.S
View File

@ -1775,6 +1775,7 @@ sys_call_table:
data8 sys_finit_module // 1335 data8 sys_finit_module // 1335
data8 sys_sched_setattr data8 sys_sched_setattr
data8 sys_sched_getattr data8 sys_sched_getattr
data8 sys_renameat2
.org sys_call_table + 8*NR_syscalls // guard against failures to increase NR_syscalls .org sys_call_table + 8*NR_syscalls // guard against failures to increase NR_syscalls
#endif /* __IA64_ASM_PARAVIRTUALIZED_NATIVE */ #endif /* __IA64_ASM_PARAVIRTUALIZED_NATIVE */

2
arch/m68k/include/asm/unistd.h
View File

@ -4,7 +4,7 @@
#include <uapi/asm/unistd.h> #include <uapi/asm/unistd.h>
#define NR_syscalls 351 #define NR_syscalls 352
#define __ARCH_WANT_OLD_READDIR #define __ARCH_WANT_OLD_READDIR
#define __ARCH_WANT_OLD_STAT #define __ARCH_WANT_OLD_STAT

1
arch/m68k/include/uapi/asm/unistd.h
View File

@ -356,5 +356,6 @@
#define __NR_finit_module 348 #define __NR_finit_module 348
#define __NR_sched_setattr 349 #define __NR_sched_setattr 349
#define __NR_sched_getattr 350 #define __NR_sched_getattr 350
#define __NR_renameat2 351
#endif /* _UAPI_ASM_M68K_UNISTD_H_ */ #endif /* _UAPI_ASM_M68K_UNISTD_H_ */

1
arch/m68k/kernel/syscalltable.S
View File

@ -371,4 +371,5 @@ ENTRY(sys_call_table)
.long sys_finit_module .long sys_finit_module
.long sys_sched_setattr .long sys_sched_setattr
.long sys_sched_getattr /* 350 */ .long sys_sched_getattr /* 350 */
.long sys_renameat2

3
arch/metag/include/asm/barrier.h
View File

@ -15,6 +15,7 @@ static inline void wr_fence(void)
volatile int *flushptr = (volatile int *) LINSYSEVENT_WR_FENCE; volatile int *flushptr = (volatile int *) LINSYSEVENT_WR_FENCE;
barrier(); barrier();
*flushptr = 0; *flushptr = 0;
barrier();
} }
#else /* CONFIG_METAG_META21 */ #else /* CONFIG_METAG_META21 */
@ -35,6 +36,7 @@ static inline void wr_fence(void)
*flushptr = 0; *flushptr = 0;
*flushptr = 0; *flushptr = 0;
*flushptr = 0; *flushptr = 0;
barrier();
} }
#endif /* !CONFIG_METAG_META21 */ #endif /* !CONFIG_METAG_META21 */
@ -68,6 +70,7 @@ static inline void fence(void)
volatile int *flushptr = (volatile int *) LINSYSEVENT_WR_ATOMIC_UNLOCK; volatile int *flushptr = (volatile int *) LINSYSEVENT_WR_ATOMIC_UNLOCK;
barrier(); barrier();
*flushptr = 0; *flushptr = 0;
barrier();
} }
#define smp_mb() fence() #define smp_mb() fence()
#define smp_rmb() fence() #define smp_rmb() fence()

2
arch/metag/include/asm/processor.h
View File

@ -22,6 +22,8 @@
/* Add an extra page of padding at the top of the stack for the guard page. */ /* Add an extra page of padding at the top of the stack for the guard page. */
#define STACK_TOP (TASK_SIZE - PAGE_SIZE) #define STACK_TOP (TASK_SIZE - PAGE_SIZE)
#define STACK_TOP_MAX STACK_TOP #define STACK_TOP_MAX STACK_TOP
/* Maximum virtual space for stack */
#define STACK_SIZE_MAX (CONFIG_MAX_STACK_SIZE_MB*1024*1024)
/* This decides where the kernel will search for a free chunk of vm /* This decides where the kernel will search for a free chunk of vm
* space during mmap's. * space during mmap's.

2
arch/metag/include/uapi/asm/Kbuild
View File

@ -4,11 +4,11 @@ include include/uapi/asm-generic/Kbuild.asm
header-y += byteorder.h header-y += byteorder.h
header-y += ech.h header-y += ech.h
header-y += ptrace.h header-y += ptrace.h
header-y += resource.h
header-y += sigcontext.h header-y += sigcontext.h
header-y += siginfo.h header-y += siginfo.h
header-y += swab.h header-y += swab.h
header-y += unistd.h header-y += unistd.h
generic-y += mman.h generic-y += mman.h
generic-y += resource.h
generic-y += setup.h generic-y += setup.h

7
arch/metag/include/uapi/asm/resource.h
View File

@ -1,7 +0,0 @@
#ifndef _UAPI_METAG_RESOURCE_H
#define _UAPI_METAG_RESOURCE_H
#define _STK_LIM_MAX (1 << 28)
#include <asm-generic/resource.h>
#endif /* _UAPI_METAG_RESOURCE_H */

1
arch/mips/dec/ecc-berr.c
View File

@ -21,6 +21,7 @@
#include <asm/addrspace.h> #include <asm/addrspace.h>
#include <asm/bootinfo.h> #include <asm/bootinfo.h>
#include <asm/cpu.h> #include <asm/cpu.h>
#include <asm/cpu-type.h>
#include <asm/irq_regs.h> #include <asm/irq_regs.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/ptrace.h> #include <asm/ptrace.h>

1
arch/mips/dec/kn02xa-berr.c
View File

@ -19,6 +19,7 @@
#include <linux/types.h> #include <linux/types.h>
#include <asm/addrspace.h> #include <asm/addrspace.h>
#include <asm/cpu-type.h>
#include <asm/irq_regs.h> #include <asm/irq_regs.h>
#include <asm/ptrace.h> #include <asm/ptrace.h>
#include <asm/traps.h> #include <asm/traps.h>

1
arch/mips/dec/prom/Makefile
View File

@ -6,4 +6,3 @@
lib-y += init.o memory.o cmdline.o identify.o console.o lib-y += init.o memory.o cmdline.o identify.o console.o
lib-$(CONFIG_32BIT) += locore.o lib-$(CONFIG_32BIT) += locore.o
lib-$(CONFIG_64BIT) += call_o32.o

89
arch/mips/dec/prom/call_o32.S
View File

@ -1,89 +0,0 @@
/*
* O32 interface for the 64 (or N32) ABI.
*
* Copyright (C) 2002 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <asm/asm.h>
#include <asm/regdef.h>
/* Maximum number of arguments supported. Must be even! */
#define O32_ARGC 32
/* Number of static registers we save. */
#define O32_STATC 11
/* Frame size for both of the above. */
#define O32_FRAMESZ (4 * O32_ARGC + SZREG * O32_STATC)
.text
/*
* O32 function call dispatcher, for interfacing 32-bit ROM routines.
*
* The standard 64 (N32) calling sequence is supported, with a0
* holding a function pointer, a1-a7 -- its first seven arguments
* and the stack -- remaining ones (up to O32_ARGC, including a1-a7).
* Static registers, gp and fp are preserved, v0 holds a result.
* This code relies on the called o32 function for sp and ra
* restoration and thus both this dispatcher and the current stack
* have to be placed in a KSEGx (or KUSEG) address space. Any
* pointers passed have to point to addresses within one of these
* spaces as well.
*/
NESTED(call_o32, O32_FRAMESZ, ra)
REG_SUBU sp,O32_FRAMESZ
REG_S ra,O32_FRAMESZ-1*SZREG(sp)
REG_S fp,O32_FRAMESZ-2*SZREG(sp)
REG_S gp,O32_FRAMESZ-3*SZREG(sp)
REG_S s7,O32_FRAMESZ-4*SZREG(sp)
REG_S s6,O32_FRAMESZ-5*SZREG(sp)
REG_S s5,O32_FRAMESZ-6*SZREG(sp)
REG_S s4,O32_FRAMESZ-7*SZREG(sp)
REG_S s3,O32_FRAMESZ-8*SZREG(sp)
REG_S s2,O32_FRAMESZ-9*SZREG(sp)
REG_S s1,O32_FRAMESZ-10*SZREG(sp)
REG_S s0,O32_FRAMESZ-11*SZREG(sp)
move jp,a0
sll a0,a1,zero
sll a1,a2,zero
sll a2,a3,zero
sll a3,a4,zero
sw a5,0x10(sp)
sw a6,0x14(sp)
sw a7,0x18(sp)
PTR_LA t0,O32_FRAMESZ(sp)
PTR_LA t1,0x1c(sp)
li t2,O32_ARGC-7
1:
lw t3,(t0)
REG_ADDU t0,SZREG
sw t3,(t1)
REG_SUBU t2,1
REG_ADDU t1,4
bnez t2,1b
jalr jp
REG_L s0,O32_FRAMESZ-11*SZREG(sp)
REG_L s1,O32_FRAMESZ-10*SZREG(sp)
REG_L s2,O32_FRAMESZ-9*SZREG(sp)
REG_L s3,O32_FRAMESZ-8*SZREG(sp)
REG_L s4,O32_FRAMESZ-7*SZREG(sp)
REG_L s5,O32_FRAMESZ-6*SZREG(sp)
REG_L s6,O32_FRAMESZ-5*SZREG(sp)
REG_L s7,O32_FRAMESZ-4*SZREG(sp)
REG_L gp,O32_FRAMESZ-3*SZREG(sp)
REG_L fp,O32_FRAMESZ-2*SZREG(sp)
REG_L ra,O32_FRAMESZ-1*SZREG(sp)
REG_ADDU sp,O32_FRAMESZ
jr ra
END(call_o32)

57
arch/mips/fw/lib/call_o32.S
View File

@ -1,7 +1,7 @@
/* /*
* O32 interface for the 64 (or N32) ABI. * O32 interface for the 64 (or N32) ABI.
* *
* Copyright (C) 2002 Maciej W. Rozycki * Copyright (C) 2002, 2014 Maciej W. Rozycki
* *
* This program is free software; you can redistribute it and/or * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License * modify it under the terms of the GNU General Public License
@ -12,28 +12,37 @@
#include <asm/asm.h> #include <asm/asm.h>
#include <asm/regdef.h> #include <asm/regdef.h>
/* O32 register size. */
#define O32_SZREG 4
/* Maximum number of arguments supported. Must be even! */ /* Maximum number of arguments supported. Must be even! */
#define O32_ARGC 32 #define O32_ARGC 32
/* Number of static registers we save. */ /* Number of static registers we save. */
#define O32_STATC 11 #define O32_STATC 11
/* Frame size for static register */ /* Argument area frame size. */
#define O32_FRAMESZ (SZREG * O32_STATC) #define O32_ARGSZ (O32_SZREG * O32_ARGC)
/* Frame size on new stack */ /* Static register save area frame size. */
#define O32_FRAMESZ_NEW (SZREG + 4 * O32_ARGC) #define O32_STATSZ (SZREG * O32_STATC)
/* Stack pointer register save area frame size. */
#define O32_SPSZ SZREG
/* Combined area frame size. */
#define O32_FRAMESZ (O32_ARGSZ + O32_SPSZ + O32_STATSZ)
/* Switched stack frame size. */
#define O32_NFRAMESZ (O32_ARGSZ + O32_SPSZ)
.text .text
/* /*
* O32 function call dispatcher, for interfacing 32-bit ROM routines. * O32 function call dispatcher, for interfacing 32-bit ROM routines.
* *
* The standard 64 (N32) calling sequence is supported, with a0 * The standard 64 (N32) calling sequence is supported, with a0 holding
* holding a function pointer, a1 a new stack pointer, a2-a7 -- its * a function pointer, a1 a pointer to the new stack to call the
* first six arguments and the stack -- remaining ones (up to O32_ARGC, * function with or 0 if no stack switching is requested, a2-a7 -- the
* including a2-a7). Static registers, gp and fp are preserved, v0 holds * function call's first six arguments, and the stack -- the remaining
* a result. This code relies on the called o32 function for sp and ra * arguments (up to O32_ARGC, including a2-a7). Static registers, gp
* restoration and this dispatcher has to be placed in a KSEGx (or KUSEG) * and fp are preserved, v0 holds the result. This code relies on the
* address space. Any pointers passed have to point to addresses within * called o32 function for sp and ra restoration and this dispatcher has
* one of these spaces as well. * to be placed in a KSEGx (or KUSEG) address space. Any pointers
* passed have to point to addresses within one of these spaces as well.
*/ */
NESTED(call_o32, O32_FRAMESZ, ra) NESTED(call_o32, O32_FRAMESZ, ra)
REG_SUBU sp,O32_FRAMESZ REG_SUBU sp,O32_FRAMESZ
@ -51,32 +60,36 @@ NESTED(call_o32, O32_FRAMESZ, ra)
REG_S s0,O32_FRAMESZ-11*SZREG(sp) REG_S s0,O32_FRAMESZ-11*SZREG(sp)
move jp,a0 move jp,a0
REG_SUBU s0,a1,O32_FRAMESZ_NEW
REG_S sp,O32_FRAMESZ_NEW-1*SZREG(s0) move fp,sp
beqz a1,0f
REG_SUBU fp,a1,O32_NFRAMESZ
0:
REG_S sp,O32_NFRAMESZ-1*SZREG(fp)
sll a0,a2,zero sll a0,a2,zero
sll a1,a3,zero sll a1,a3,zero
sll a2,a4,zero sll a2,a4,zero
sll a3,a5,zero sll a3,a5,zero
sw a6,0x10(s0) sw a6,4*O32_SZREG(fp)
sw a7,0x14(s0) sw a7,5*O32_SZREG(fp)
PTR_LA t0,O32_FRAMESZ(sp) PTR_LA t0,O32_FRAMESZ(sp)
PTR_LA t1,0x18(s0) PTR_LA t1,6*O32_SZREG(fp)
li t2,O32_ARGC-6 li t2,O32_ARGC-6
1: 1:
lw t3,(t0) lw t3,(t0)
REG_ADDU t0,SZREG REG_ADDU t0,SZREG
sw t3,(t1) sw t3,(t1)
REG_SUBU t2,1 REG_SUBU t2,1
REG_ADDU t1,4 REG_ADDU t1,O32_SZREG
bnez t2,1b bnez t2,1b
move sp,s0 move sp,fp
jalr jp jalr jp
REG_L sp,O32_FRAMESZ_NEW-1*SZREG(sp) REG_L sp,O32_NFRAMESZ-1*SZREG(sp)
REG_L s0,O32_FRAMESZ-11*SZREG(sp) REG_L s0,O32_FRAMESZ-11*SZREG(sp)
REG_L s1,O32_FRAMESZ-10*SZREG(sp) REG_L s1,O32_FRAMESZ-10*SZREG(sp)

3
arch/mips/fw/sni/sniprom.c
View File

@ -40,7 +40,8 @@
#ifdef CONFIG_64BIT #ifdef CONFIG_64BIT
static u8 o32_stk[16384]; /* O32 stack has to be 8-byte aligned. */
static u64 o32_stk[4096];
#define O32_STK &o32_stk[sizeof(o32_stk)] #define O32_STK &o32_stk[sizeof(o32_stk)]
#define __PROM_O32(fun, arg) fun arg __asm__(#fun); \ #define __PROM_O32(fun, arg) fun arg __asm__(#fun); \

40
arch/mips/include/asm/dec/prom.h
View File

@ -113,31 +113,31 @@ extern int (*__pmax_close)(int);
#define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \ #define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \
__asm__(#fun " = call_o32") __asm__(#fun " = call_o32")
int __DEC_PROM_O32(_rex_bootinit, (int (*)(void))); int __DEC_PROM_O32(_rex_bootinit, (int (*)(void), void *));
int __DEC_PROM_O32(_rex_bootread, (int (*)(void))); int __DEC_PROM_O32(_rex_bootread, (int (*)(void), void *));
int __DEC_PROM_O32(_rex_getbitmap, (int (*)(memmap *), memmap *)); int __DEC_PROM_O32(_rex_getbitmap, (int (*)(memmap *), void *, memmap *));
unsigned long *__DEC_PROM_O32(_rex_slot_address, unsigned long *__DEC_PROM_O32(_rex_slot_address,
(unsigned long *(*)(int), int)); (unsigned long *(*)(int), void *, int));
void *__DEC_PROM_O32(_rex_gettcinfo, (void *(*)(void))); void *__DEC_PROM_O32(_rex_gettcinfo, (void *(*)(void), void *));
int __DEC_PROM_O32(_rex_getsysid, (int (*)(void))); int __DEC_PROM_O32(_rex_getsysid, (int (*)(void), void *));
void __DEC_PROM_O32(_rex_clear_cache, (void (*)(void))); void __DEC_PROM_O32(_rex_clear_cache, (void (*)(void), void *));
int __DEC_PROM_O32(_prom_getchar, (int (*)(void))); int __DEC_PROM_O32(_prom_getchar, (int (*)(void), void *));
char *__DEC_PROM_O32(_prom_getenv, (char *(*)(char *), char *)); char *__DEC_PROM_O32(_prom_getenv, (char *(*)(char *), void *, char *));
int __DEC_PROM_O32(_prom_printf, (int (*)(char *, ...), char *, ...)); int __DEC_PROM_O32(_prom_printf, (int (*)(char *, ...), void *, char *, ...));
#define rex_bootinit() _rex_bootinit(__rex_bootinit) #define rex_bootinit() _rex_bootinit(__rex_bootinit, NULL)
#define rex_bootread() _rex_bootread(__rex_bootread) #define rex_bootread() _rex_bootread(__rex_bootread, NULL)
#define rex_getbitmap(x) _rex_getbitmap(__rex_getbitmap, x) #define rex_getbitmap(x) _rex_getbitmap(__rex_getbitmap, NULL, x)
#define rex_slot_address(x) _rex_slot_address(__rex_slot_address, x) #define rex_slot_address(x) _rex_slot_address(__rex_slot_address, NULL, x)
#define rex_gettcinfo() _rex_gettcinfo(__rex_gettcinfo) #define rex_gettcinfo() _rex_gettcinfo(__rex_gettcinfo, NULL)
#define rex_getsysid() _rex_getsysid(__rex_getsysid) #define rex_getsysid() _rex_getsysid(__rex_getsysid, NULL)
#define rex_clear_cache() _rex_clear_cache(__rex_clear_cache) #define rex_clear_cache() _rex_clear_cache(__rex_clear_cache, NULL)
#define prom_getchar() _prom_getchar(__prom_getchar) #define prom_getchar() _prom_getchar(__prom_getchar, NULL)
#define prom_getenv(x) _prom_getenv(__prom_getenv, x) #define prom_getenv(x) _prom_getenv(__prom_getenv, NULL, x)
#define prom_printf(x...) _prom_printf(__prom_printf, x) #define prom_printf(x...) _prom_printf(__prom_printf, NULL, x)
#else /* !CONFIG_64BIT */ #else /* !CONFIG_64BIT */

56
arch/mips/include/asm/rm9k-ocd.h
View File

@ -1,56 +0,0 @@
/*
* Copyright (C) 2004 by Basler Vision Technologies AG
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#if !defined(_ASM_RM9K_OCD_H)
#define _ASM_RM9K_OCD_H
#include <linux/types.h>
#include <linux/spinlock.h>
#include <asm/io.h>
extern volatile void __iomem * const ocd_base;
extern volatile void __iomem * const titan_base;
#define ocd_addr(__x__) (ocd_base + (__x__))
#define titan_addr(__x__) (titan_base + (__x__))
#define scram_addr(__x__) (scram_base + (__x__))
/* OCD register access */
#define ocd_readl(__offs__) __raw_readl(ocd_addr(__offs__))
#define ocd_readw(__offs__) __raw_readw(ocd_addr(__offs__))
#define ocd_readb(__offs__) __raw_readb(ocd_addr(__offs__))
#define ocd_writel(__val__, __offs__) \
__raw_writel((__val__), ocd_addr(__offs__))
#define ocd_writew(__val__, __offs__) \
__raw_writew((__val__), ocd_addr(__offs__))
#define ocd_writeb(__val__, __offs__) \
__raw_writeb((__val__), ocd_addr(__offs__))
/* TITAN register access - 32 bit-wide only */
#define titan_readl(__offs__) __raw_readl(titan_addr(__offs__))
#define titan_writel(__val__, __offs__) \
__raw_writel((__val__), titan_addr(__offs__))
/* Protect access to shared TITAN registers */
extern spinlock_t titan_lock;
extern int titan_irqflags;
#define lock_titan_regs() spin_lock_irqsave(&titan_lock, titan_irqflags)
#define unlock_titan_regs() spin_unlock_irqrestore(&titan_lock, titan_irqflags)
#endif /* !defined(_ASM_RM9K_OCD_H) */

2
arch/mips/include/asm/syscall.h
View File

@ -133,6 +133,8 @@ static inline int syscall_get_arch(void)
#ifdef CONFIG_64BIT #ifdef CONFIG_64BIT
if (!test_thread_flag(TIF_32BIT_REGS)) if (!test_thread_flag(TIF_32BIT_REGS))
arch |= __AUDIT_ARCH_64BIT; arch |= __AUDIT_ARCH_64BIT;
if (test_thread_flag(TIF_32BIT_ADDR))
arch |= __AUDIT_ARCH_CONVENTION_MIPS64_N32;
#endif #endif
#if defined(__LITTLE_ENDIAN) #if defined(__LITTLE_ENDIAN)
arch |= __AUDIT_ARCH_LE; arch |= __AUDIT_ARCH_LE;

398
arch/mips/include/uapi/asm/inst.h
View File

@ -484,13 +484,13 @@ enum MIPS6e_i8_func {
* Damn ... bitfields depend from byteorder :-( * Damn ... bitfields depend from byteorder :-(
*/ */
#ifdef __MIPSEB__ #ifdef __MIPSEB__
#define BITFIELD_FIELD(field, more) \ #define __BITFIELD_FIELD(field, more) \
field; \ field; \
more more
#elif defined(__MIPSEL__) #elif defined(__MIPSEL__)
#define BITFIELD_FIELD(field, more) \ #define __BITFIELD_FIELD(field, more) \
more \ more \
field; field;
@ -499,112 +499,112 @@ enum MIPS6e_i8_func {
#endif #endif
struct j_format { struct j_format {
BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */ __BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
BITFIELD_FIELD(unsigned int target : 26, __BITFIELD_FIELD(unsigned int target : 26,
;)) ;))
}; };
struct i_format { /* signed immediate format */ struct i_format { /* signed immediate format */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rs : 5, __BITFIELD_FIELD(unsigned int rs : 5,
BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int rt : 5,
BITFIELD_FIELD(signed int simmediate : 16, __BITFIELD_FIELD(signed int simmediate : 16,
;)))) ;))))
}; };
struct u_format { /* unsigned immediate format */ struct u_format { /* unsigned immediate format */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rs : 5, __BITFIELD_FIELD(unsigned int rs : 5,
BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int rt : 5,
BITFIELD_FIELD(unsigned int uimmediate : 16, __BITFIELD_FIELD(unsigned int uimmediate : 16,
;)))) ;))))
}; };
struct c_format { /* Cache (>= R6000) format */ struct c_format { /* Cache (>= R6000) format */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rs : 5, __BITFIELD_FIELD(unsigned int rs : 5,
BITFIELD_FIELD(unsigned int c_op : 3, __BITFIELD_FIELD(unsigned int c_op : 3,
BITFIELD_FIELD(unsigned int cache : 2, __BITFIELD_FIELD(unsigned int cache : 2,
BITFIELD_FIELD(unsigned int simmediate : 16, __BITFIELD_FIELD(unsigned int simmediate : 16,
;))))) ;)))))
}; };
struct r_format { /* Register format */ struct r_format { /* Register format */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rs : 5, __BITFIELD_FIELD(unsigned int rs : 5,
BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int rt : 5,
BITFIELD_FIELD(unsigned int rd : 5, __BITFIELD_FIELD(unsigned int rd : 5,
BITFIELD_FIELD(unsigned int re : 5, __BITFIELD_FIELD(unsigned int re : 5,
BITFIELD_FIELD(unsigned int func : 6, __BITFIELD_FIELD(unsigned int func : 6,
;)))))) ;))))))
}; };
struct p_format { /* Performance counter format (R10000) */ struct p_format { /* Performance counter format (R10000) */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rs : 5, __BITFIELD_FIELD(unsigned int rs : 5,
BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int rt : 5,
BITFIELD_FIELD(unsigned int rd : 5, __BITFIELD_FIELD(unsigned int rd : 5,
BITFIELD_FIELD(unsigned int re : 5, __BITFIELD_FIELD(unsigned int re : 5,
BITFIELD_FIELD(unsigned int func : 6, __BITFIELD_FIELD(unsigned int func : 6,
;)))))) ;))))))
}; };
struct f_format { /* FPU register format */ struct f_format { /* FPU register format */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int : 1, __BITFIELD_FIELD(unsigned int : 1,
BITFIELD_FIELD(unsigned int fmt : 4, __BITFIELD_FIELD(unsigned int fmt : 4,
BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int rt : 5,
BITFIELD_FIELD(unsigned int rd : 5, __BITFIELD_FIELD(unsigned int rd : 5,
BITFIELD_FIELD(unsigned int re : 5, __BITFIELD_FIELD(unsigned int re : 5,
BITFIELD_FIELD(unsigned int func : 6, __BITFIELD_FIELD(unsigned int func : 6,
;))))))) ;)))))))
}; };
struct ma_format { /* FPU multiply and add format (MIPS IV) */ struct ma_format { /* FPU multiply and add format (MIPS IV) */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int fr : 5, __BITFIELD_FIELD(unsigned int fr : 5,
BITFIELD_FIELD(unsigned int ft : 5, __BITFIELD_FIELD(unsigned int ft : 5,
BITFIELD_FIELD(unsigned int fs : 5, __BITFIELD_FIELD(unsigned int fs : 5,
BITFIELD_FIELD(unsigned int fd : 5, __BITFIELD_FIELD(unsigned int fd : 5,
BITFIELD_FIELD(unsigned int func : 4, __BITFIELD_FIELD(unsigned int func : 4,
BITFIELD_FIELD(unsigned int fmt : 2, __BITFIELD_FIELD(unsigned int fmt : 2,
;))))))) ;)))))))
}; };
struct b_format { /* BREAK and SYSCALL */ struct b_format { /* BREAK and SYSCALL */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int code : 20, __BITFIELD_FIELD(unsigned int code : 20,
BITFIELD_FIELD(unsigned int func : 6, __BITFIELD_FIELD(unsigned int func : 6,
;))) ;)))
}; };
struct ps_format { /* MIPS-3D / paired single format */ struct ps_format { /* MIPS-3D / paired single format */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rs : 5, __BITFIELD_FIELD(unsigned int rs : 5,
BITFIELD_FIELD(unsigned int ft : 5, __BITFIELD_FIELD(unsigned int ft : 5,
BITFIELD_FIELD(unsigned int fs : 5, __BITFIELD_FIELD(unsigned int fs : 5,
BITFIELD_FIELD(unsigned int fd : 5, __BITFIELD_FIELD(unsigned int fd : 5,
BITFIELD_FIELD(unsigned int func : 6, __BITFIELD_FIELD(unsigned int func : 6,
;)))))) ;))))))
}; };
struct v_format { /* MDMX vector format */ struct v_format { /* MDMX vector format */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int sel : 4, __BITFIELD_FIELD(unsigned int sel : 4,
BITFIELD_FIELD(unsigned int fmt : 1, __BITFIELD_FIELD(unsigned int fmt : 1,
BITFIELD_FIELD(unsigned int vt : 5, __BITFIELD_FIELD(unsigned int vt : 5,
BITFIELD_FIELD(unsigned int vs : 5, __BITFIELD_FIELD(unsigned int vs : 5,
BITFIELD_FIELD(unsigned int vd : 5, __BITFIELD_FIELD(unsigned int vd : 5,
BITFIELD_FIELD(unsigned int func : 6, __BITFIELD_FIELD(unsigned int func : 6,
;))))))) ;)))))))
}; };
struct spec3_format { /* SPEC3 */ struct spec3_format { /* SPEC3 */
BITFIELD_FIELD(unsigned int opcode:6, __BITFIELD_FIELD(unsigned int opcode:6,
BITFIELD_FIELD(unsigned int rs:5, __BITFIELD_FIELD(unsigned int rs:5,
BITFIELD_FIELD(unsigned int rt:5, __BITFIELD_FIELD(unsigned int rt:5,
BITFIELD_FIELD(signed int simmediate:9, __BITFIELD_FIELD(signed int simmediate:9,
BITFIELD_FIELD(unsigned int func:7, __BITFIELD_FIELD(unsigned int func:7,
;))))) ;)))))
}; };
@ -616,141 +616,141 @@ struct spec3_format { /* SPEC3 */
* if it is MIPS32 instruction re-encoded for use in the microMIPS ASE. * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
*/ */
struct fb_format { /* FPU branch format (MIPS32) */ struct fb_format { /* FPU branch format (MIPS32) */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int bc : 5, __BITFIELD_FIELD(unsigned int bc : 5,
BITFIELD_FIELD(unsigned int cc : 3, __BITFIELD_FIELD(unsigned int cc : 3,
BITFIELD_FIELD(unsigned int flag : 2, __BITFIELD_FIELD(unsigned int flag : 2,
BITFIELD_FIELD(signed int simmediate : 16, __BITFIELD_FIELD(signed int simmediate : 16,
;))))) ;)))))
}; };
struct fp0_format { /* FPU multiply and add format (MIPS32) */ struct fp0_format { /* FPU multiply and add format (MIPS32) */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int fmt : 5, __BITFIELD_FIELD(unsigned int fmt : 5,
BITFIELD_FIELD(unsigned int ft : 5, __BITFIELD_FIELD(unsigned int ft : 5,
BITFIELD_FIELD(unsigned int fs : 5, __BITFIELD_FIELD(unsigned int fs : 5,
BITFIELD_FIELD(unsigned int fd : 5, __BITFIELD_FIELD(unsigned int fd : 5,
BITFIELD_FIELD(unsigned int func : 6, __BITFIELD_FIELD(unsigned int func : 6,
;)))))) ;))))))
}; };
struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int ft : 5, __BITFIELD_FIELD(unsigned int ft : 5,
BITFIELD_FIELD(unsigned int fs : 5, __BITFIELD_FIELD(unsigned int fs : 5,
BITFIELD_FIELD(unsigned int fd : 5, __BITFIELD_FIELD(unsigned int fd : 5,
BITFIELD_FIELD(unsigned int fmt : 3, __BITFIELD_FIELD(unsigned int fmt : 3,
BITFIELD_FIELD(unsigned int op : 2, __BITFIELD_FIELD(unsigned int op : 2,
BITFIELD_FIELD(unsigned int func : 6, __BITFIELD_FIELD(unsigned int func : 6,
;))))))) ;)))))))
}; };
struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int op : 5, __BITFIELD_FIELD(unsigned int op : 5,
BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int rt : 5,
BITFIELD_FIELD(unsigned int fs : 5, __BITFIELD_FIELD(unsigned int fs : 5,
BITFIELD_FIELD(unsigned int fd : 5, __BITFIELD_FIELD(unsigned int fd : 5,
BITFIELD_FIELD(unsigned int func : 6, __BITFIELD_FIELD(unsigned int func : 6,
;)))))) ;))))))
}; };
struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int rt : 5,
BITFIELD_FIELD(unsigned int fs : 5, __BITFIELD_FIELD(unsigned int fs : 5,
BITFIELD_FIELD(unsigned int fmt : 2, __BITFIELD_FIELD(unsigned int fmt : 2,
BITFIELD_FIELD(unsigned int op : 8, __BITFIELD_FIELD(unsigned int op : 8,
BITFIELD_FIELD(unsigned int func : 6, __BITFIELD_FIELD(unsigned int func : 6,
;)))))) ;))))))
}; };
struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int fd : 5, __BITFIELD_FIELD(unsigned int fd : 5,
BITFIELD_FIELD(unsigned int fs : 5, __BITFIELD_FIELD(unsigned int fs : 5,
BITFIELD_FIELD(unsigned int cc : 3, __BITFIELD_FIELD(unsigned int cc : 3,
BITFIELD_FIELD(unsigned int zero : 2, __BITFIELD_FIELD(unsigned int zero : 2,
BITFIELD_FIELD(unsigned int fmt : 2, __BITFIELD_FIELD(unsigned int fmt : 2,
BITFIELD_FIELD(unsigned int op : 3, __BITFIELD_FIELD(unsigned int op : 3,
BITFIELD_FIELD(unsigned int func : 6, __BITFIELD_FIELD(unsigned int func : 6,
;)))))))) ;))))))))
}; };
struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int rt : 5,
BITFIELD_FIELD(unsigned int fs : 5, __BITFIELD_FIELD(unsigned int fs : 5,
BITFIELD_FIELD(unsigned int fmt : 3, __BITFIELD_FIELD(unsigned int fmt : 3,
BITFIELD_FIELD(unsigned int op : 7, __BITFIELD_FIELD(unsigned int op : 7,
BITFIELD_FIELD(unsigned int func : 6, __BITFIELD_FIELD(unsigned int func : 6,
;)))))) ;))))))
}; };
struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ struct mm_fp4_format { /* FPU c.cond format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int rt : 5,
BITFIELD_FIELD(unsigned int fs : 5, __BITFIELD_FIELD(unsigned int fs : 5,
BITFIELD_FIELD(unsigned int cc : 3, __BITFIELD_FIELD(unsigned int cc : 3,
BITFIELD_FIELD(unsigned int fmt : 3, __BITFIELD_FIELD(unsigned int fmt : 3,
BITFIELD_FIELD(unsigned int cond : 4, __BITFIELD_FIELD(unsigned int cond : 4,
BITFIELD_FIELD(unsigned int func : 6, __BITFIELD_FIELD(unsigned int func : 6,
;))))))) ;)))))))
}; };
struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int index : 5, __BITFIELD_FIELD(unsigned int index : 5,
BITFIELD_FIELD(unsigned int base : 5, __BITFIELD_FIELD(unsigned int base : 5,
BITFIELD_FIELD(unsigned int fd : 5, __BITFIELD_FIELD(unsigned int fd : 5,
BITFIELD_FIELD(unsigned int op : 5, __BITFIELD_FIELD(unsigned int op : 5,
BITFIELD_FIELD(unsigned int func : 6, __BITFIELD_FIELD(unsigned int func : 6,
;)))))) ;))))))
}; };
struct fp6_format { /* FPU madd and msub format (MIPS IV) */ struct fp6_format { /* FPU madd and msub format (MIPS IV) */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int fr : 5, __BITFIELD_FIELD(unsigned int fr : 5,
BITFIELD_FIELD(unsigned int ft : 5, __BITFIELD_FIELD(unsigned int ft : 5,
BITFIELD_FIELD(unsigned int fs : 5, __BITFIELD_FIELD(unsigned int fs : 5,
BITFIELD_FIELD(unsigned int fd : 5, __BITFIELD_FIELD(unsigned int fd : 5,
BITFIELD_FIELD(unsigned int func : 6, __BITFIELD_FIELD(unsigned int func : 6,
;)))))) ;))))))
}; };
struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int ft : 5, __BITFIELD_FIELD(unsigned int ft : 5,
BITFIELD_FIELD(unsigned int fs : 5, __BITFIELD_FIELD(unsigned int fs : 5,
BITFIELD_FIELD(unsigned int fd : 5, __BITFIELD_FIELD(unsigned int fd : 5,
BITFIELD_FIELD(unsigned int fr : 5, __BITFIELD_FIELD(unsigned int fr : 5,
BITFIELD_FIELD(unsigned int func : 6, __BITFIELD_FIELD(unsigned int func : 6,
;)))))) ;))))))
}; };
struct mm_i_format { /* Immediate format (microMIPS) */ struct mm_i_format { /* Immediate format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int rt : 5,
BITFIELD_FIELD(unsigned int rs : 5, __BITFIELD_FIELD(unsigned int rs : 5,
BITFIELD_FIELD(signed int simmediate : 16, __BITFIELD_FIELD(signed int simmediate : 16,
;)))) ;))))
}; };
struct mm_m_format { /* Multi-word load/store format (microMIPS) */ struct mm_m_format { /* Multi-word load/store format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rd : 5, __BITFIELD_FIELD(unsigned int rd : 5,
BITFIELD_FIELD(unsigned int base : 5, __BITFIELD_FIELD(unsigned int base : 5,
BITFIELD_FIELD(unsigned int func : 4, __BITFIELD_FIELD(unsigned int func : 4,
BITFIELD_FIELD(signed int simmediate : 12, __BITFIELD_FIELD(signed int simmediate : 12,
;))))) ;)))))
}; };
struct mm_x_format { /* Scaled indexed load format (microMIPS) */ struct mm_x_format { /* Scaled indexed load format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int index : 5, __BITFIELD_FIELD(unsigned int index : 5,
BITFIELD_FIELD(unsigned int base : 5, __BITFIELD_FIELD(unsigned int base : 5,
BITFIELD_FIELD(unsigned int rd : 5, __BITFIELD_FIELD(unsigned int rd : 5,
BITFIELD_FIELD(unsigned int func : 11, __BITFIELD_FIELD(unsigned int func : 11,
;))))) ;)))))
}; };
@ -758,51 +758,51 @@ struct mm_x_format { /* Scaled indexed load format (microMIPS) */
* microMIPS instruction formats (16-bit length) * microMIPS instruction formats (16-bit length)
*/ */
struct mm_b0_format { /* Unconditional branch format (microMIPS) */ struct mm_b0_format { /* Unconditional branch format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(signed int simmediate : 10, __BITFIELD_FIELD(signed int simmediate : 10,
BITFIELD_FIELD(unsigned int : 16, /* Ignored */ __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
;))) ;)))
}; };
struct mm_b1_format { /* Conditional branch format (microMIPS) */ struct mm_b1_format { /* Conditional branch format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rs : 3, __BITFIELD_FIELD(unsigned int rs : 3,
BITFIELD_FIELD(signed int simmediate : 7, __BITFIELD_FIELD(signed int simmediate : 7,
BITFIELD_FIELD(unsigned int : 16, /* Ignored */ __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
;)))) ;))))
}; };
struct mm16_m_format { /* Multi-word load/store format */ struct mm16_m_format { /* Multi-word load/store format */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int func : 4, __BITFIELD_FIELD(unsigned int func : 4,
BITFIELD_FIELD(unsigned int rlist : 2, __BITFIELD_FIELD(unsigned int rlist : 2,
BITFIELD_FIELD(unsigned int imm : 4, __BITFIELD_FIELD(unsigned int imm : 4,
BITFIELD_FIELD(unsigned int : 16, /* Ignored */ __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
;))))) ;)))))
}; };
struct mm16_rb_format { /* Signed immediate format */ struct mm16_rb_format { /* Signed immediate format */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rt : 3, __BITFIELD_FIELD(unsigned int rt : 3,
BITFIELD_FIELD(unsigned int base : 3, __BITFIELD_FIELD(unsigned int base : 3,
BITFIELD_FIELD(signed int simmediate : 4, __BITFIELD_FIELD(signed int simmediate : 4,
BITFIELD_FIELD(unsigned int : 16, /* Ignored */ __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
;))))) ;)))))
}; };
struct mm16_r3_format { /* Load from global pointer format */ struct mm16_r3_format { /* Load from global pointer format */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rt : 3, __BITFIELD_FIELD(unsigned int rt : 3,
BITFIELD_FIELD(signed int simmediate : 7, __BITFIELD_FIELD(signed int simmediate : 7,
BITFIELD_FIELD(unsigned int : 16, /* Ignored */ __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
;)))) ;))))
}; };
struct mm16_r5_format { /* Load/store from stack pointer format */ struct mm16_r5_format { /* Load/store from stack pointer format */
BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int rt : 5,
BITFIELD_FIELD(signed int simmediate : 5, __BITFIELD_FIELD(signed int simmediate : 5,
BITFIELD_FIELD(unsigned int : 16, /* Ignored */ __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
;)))) ;))))
}; };
@ -810,57 +810,57 @@ struct mm16_r5_format { /* Load/store from stack pointer format */
* MIPS16e instruction formats (16-bit length) * MIPS16e instruction formats (16-bit length)
*/ */
struct m16e_rr { struct m16e_rr {
BITFIELD_FIELD(unsigned int opcode : 5, __BITFIELD_FIELD(unsigned int opcode : 5,
BITFIELD_FIELD(unsigned int rx : 3, __BITFIELD_FIELD(unsigned int rx : 3,
BITFIELD_FIELD(unsigned int nd : 1, __BITFIELD_FIELD(unsigned int nd : 1,
BITFIELD_FIELD(unsigned int l : 1, __BITFIELD_FIELD(unsigned int l : 1,
BITFIELD_FIELD(unsigned int ra : 1, __BITFIELD_FIELD(unsigned int ra : 1,
BITFIELD_FIELD(unsigned int func : 5, __BITFIELD_FIELD(unsigned int func : 5,
;)))))) ;))))))
}; };
struct m16e_jal { struct m16e_jal {
BITFIELD_FIELD(unsigned int opcode : 5, __BITFIELD_FIELD(unsigned int opcode : 5,
BITFIELD_FIELD(unsigned int x : 1, __BITFIELD_FIELD(unsigned int x : 1,
BITFIELD_FIELD(unsigned int imm20_16 : 5, __BITFIELD_FIELD(unsigned int imm20_16 : 5,
BITFIELD_FIELD(signed int imm25_21 : 5, __BITFIELD_FIELD(signed int imm25_21 : 5,
;)))) ;))))
}; };
struct m16e_i64 { struct m16e_i64 {
BITFIELD_FIELD(unsigned int opcode : 5, __BITFIELD_FIELD(unsigned int opcode : 5,
BITFIELD_FIELD(unsigned int func : 3, __BITFIELD_FIELD(unsigned int func : 3,
BITFIELD_FIELD(unsigned int imm : 8, __BITFIELD_FIELD(unsigned int imm : 8,
;))) ;)))
}; };
struct m16e_ri64 { struct m16e_ri64 {
BITFIELD_FIELD(unsigned int opcode : 5, __BITFIELD_FIELD(unsigned int opcode : 5,
BITFIELD_FIELD(unsigned int func : 3, __BITFIELD_FIELD(unsigned int func : 3,
BITFIELD_FIELD(unsigned int ry : 3, __BITFIELD_FIELD(unsigned int ry : 3,
BITFIELD_FIELD(unsigned int imm : 5, __BITFIELD_FIELD(unsigned int imm : 5,
;)))) ;))))
}; };
struct m16e_ri { struct m16e_ri {
BITFIELD_FIELD(unsigned int opcode : 5, __BITFIELD_FIELD(unsigned int opcode : 5,
BITFIELD_FIELD(unsigned int rx : 3, __BITFIELD_FIELD(unsigned int rx : 3,
BITFIELD_FIELD(unsigned int imm : 8, __BITFIELD_FIELD(unsigned int imm : 8,
;))) ;)))
}; };
struct m16e_rri { struct m16e_rri {
BITFIELD_FIELD(unsigned int opcode : 5, __BITFIELD_FIELD(unsigned int opcode : 5,
BITFIELD_FIELD(unsigned int rx : 3, __BITFIELD_FIELD(unsigned int rx : 3,
BITFIELD_FIELD(unsigned int ry : 3, __BITFIELD_FIELD(unsigned int ry : 3,
BITFIELD_FIELD(unsigned int imm : 5, __BITFIELD_FIELD(unsigned int imm : 5,
;)))) ;))))
}; };
struct m16e_i8 { struct m16e_i8 {
BITFIELD_FIELD(unsigned int opcode : 5, __BITFIELD_FIELD(unsigned int opcode : 5,
BITFIELD_FIELD(unsigned int func : 3, __BITFIELD_FIELD(unsigned int func : 3,
BITFIELD_FIELD(unsigned int imm : 8, __BITFIELD_FIELD(unsigned int imm : 8,
;))) ;)))
}; };

9
arch/mips/include/uapi/asm/unistd.h
View File

@ -371,11 +371,12 @@
#define __NR_finit_module (__NR_Linux + 348) #define __NR_finit_module (__NR_Linux + 348)
#define __NR_sched_setattr (__NR_Linux + 349) #define __NR_sched_setattr (__NR_Linux + 349)
#define __NR_sched_getattr (__NR_Linux + 350) #define __NR_sched_getattr (__NR_Linux + 350)
#define __NR_renameat2 (__NR_Linux + 351)
/* /*
* Offset of the last Linux o32 flavoured syscall * Offset of the last Linux o32 flavoured syscall
*/ */
#define __NR_Linux_syscalls 350 #define __NR_Linux_syscalls 351
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
@ -699,11 +700,12 @@
#define __NR_getdents64 (__NR_Linux + 308) #define __NR_getdents64 (__NR_Linux + 308)
#define __NR_sched_setattr (__NR_Linux + 309) #define __NR_sched_setattr (__NR_Linux + 309)
#define __NR_sched_getattr (__NR_Linux + 310) #define __NR_sched_getattr (__NR_Linux + 310)
#define __NR_renameat2 (__NR_Linux + 311)
/* /*
* Offset of the last Linux 64-bit flavoured syscall * Offset of the last Linux 64-bit flavoured syscall
*/ */
#define __NR_Linux_syscalls 310 #define __NR_Linux_syscalls 311
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
@ -1031,11 +1033,12 @@
#define __NR_finit_module (__NR_Linux + 312) #define __NR_finit_module (__NR_Linux + 312)
#define __NR_sched_setattr (__NR_Linux + 313) #define __NR_sched_setattr (__NR_Linux + 313)
#define __NR_sched_getattr (__NR_Linux + 314) #define __NR_sched_getattr (__NR_Linux + 314)
#define __NR_renameat2 (__NR_Linux + 315)
/* /*
* Offset of the last N32 flavoured syscall * Offset of the last N32 flavoured syscall
*/ */
#define __NR_Linux_syscalls 314 #define __NR_Linux_syscalls 315
#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */

9
arch/mips/kernel/proc.c
View File

@ -124,14 +124,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, "kscratch registers\t: %d\n", seq_printf(m, "kscratch registers\t: %d\n",
hweight8(cpu_data[n].kscratch_mask)); hweight8(cpu_data[n].kscratch_mask));
seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core); seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
if (cpu_has_mipsmt) {
seq_printf(m, "VPE\t\t\t: %d\n", cpu_data[n].vpe_id);
#if defined(CONFIG_MIPS_MT_SMTC)
seq_printf(m, "TC\t\t\t: %d\n", cpu_data[n].tc_id);
#endif
}
#endif
sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
cpu_has_vce ? "%u" : "not available"); cpu_has_vce ? "%u" : "not available");
seq_printf(m, fmt, 'D', vced_count); seq_printf(m, fmt, 'D', vced_count);

1
arch/mips/kernel/scall32-o32.S
View File

@ -577,3 +577,4 @@ EXPORT(sys_call_table)
PTR sys_finit_module PTR sys_finit_module
PTR sys_sched_setattr PTR sys_sched_setattr
PTR sys_sched_getattr /* 4350 */ PTR sys_sched_getattr /* 4350 */
PTR sys_renameat2

1
arch/mips/kernel/scall64-64.S
View File

@ -430,4 +430,5 @@ EXPORT(sys_call_table)
PTR sys_getdents64 PTR sys_getdents64
PTR sys_sched_setattr PTR sys_sched_setattr
PTR sys_sched_getattr /* 5310 */ PTR sys_sched_getattr /* 5310 */
PTR sys_renameat2
.size sys_call_table,.-sys_call_table .size sys_call_table,.-sys_call_table

1
arch/mips/kernel/scall64-n32.S
View File

@ -423,4 +423,5 @@ EXPORT(sysn32_call_table)
PTR sys_finit_module PTR sys_finit_module
PTR sys_sched_setattr PTR sys_sched_setattr
PTR sys_sched_getattr PTR sys_sched_getattr
PTR sys_renameat2 /* 6315 */
.size sysn32_call_table,.-sysn32_call_table .size sysn32_call_table,.-sysn32_call_table

1
arch/mips/kernel/scall64-o32.S
View File

@ -556,4 +556,5 @@ EXPORT(sys32_call_table)
PTR sys_finit_module PTR sys_finit_module
PTR sys_sched_setattr PTR sys_sched_setattr
PTR sys_sched_getattr /* 4350 */ PTR sys_sched_getattr /* 4350 */
PTR sys_renameat2
.size sys32_call_table,.-sys32_call_table .size sys32_call_table,.-sys32_call_table

1
arch/mips/lantiq/dts/easy50712.dts
View File

@ -8,6 +8,7 @@
}; };
memory@0 { memory@0 {
device_type = "memory";
reg = <0x0 0x2000000>; reg = <0x0 0x2000000>;
}; };

9
arch/mips/lib/csum_partial.S
View File

@ -56,14 +56,20 @@
#define UNIT(unit) ((unit)*NBYTES) #define UNIT(unit) ((unit)*NBYTES)
#define ADDC(sum,reg) \ #define ADDC(sum,reg) \
.set push; \
.set noat; \
ADD sum, reg; \ ADD sum, reg; \
sltu v1, sum, reg; \ sltu v1, sum, reg; \
ADD sum, v1; \ ADD sum, v1; \
.set pop
#define ADDC32(sum,reg) \ #define ADDC32(sum,reg) \
.set push; \
.set noat; \
addu sum, reg; \ addu sum, reg; \
sltu v1, sum, reg; \ sltu v1, sum, reg; \
addu sum, v1; \ addu sum, v1; \
.set pop
#define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3) \ #define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3) \
LOAD _t0, (offset + UNIT(0))(src); \ LOAD _t0, (offset + UNIT(0))(src); \
@ -710,6 +716,8 @@ LEAF(csum_partial)
ADDC(sum, t2) ADDC(sum, t2)
.Ldone\@: .Ldone\@:
/* fold checksum */ /* fold checksum */
.set push
.set noat
#ifdef USE_DOUBLE #ifdef USE_DOUBLE
dsll32 v1, sum, 0 dsll32 v1, sum, 0
daddu sum, v1 daddu sum, v1
@ -732,6 +740,7 @@ LEAF(csum_partial)
or sum, sum, t0 or sum, sum, t0
1: 1:
#endif #endif
.set pop
.set reorder .set reorder
ADDC32(sum, psum) ADDC32(sum, psum)
jr ra jr ra

14
arch/mips/lib/delay.c
View File

@ -6,7 +6,7 @@
* Copyright (C) 1994 by Waldorf Electronics * Copyright (C) 1994 by Waldorf Electronics
* Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle * Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc. * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
* Copyright (C) 2007 Maciej W. Rozycki * Copyright (C) 2007, 2014 Maciej W. Rozycki
*/ */
#include <linux/module.h> #include <linux/module.h>
#include <linux/param.h> #include <linux/param.h>
@ -15,6 +15,12 @@
#include <asm/compiler.h> #include <asm/compiler.h>
#include <asm/war.h> #include <asm/war.h>
#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
#define GCC_DADDI_IMM_ASM() "I"
#else
#define GCC_DADDI_IMM_ASM() "r"
#endif
void __delay(unsigned long loops) void __delay(unsigned long loops)
{ {
__asm__ __volatile__ ( __asm__ __volatile__ (
@ -22,13 +28,13 @@ void __delay(unsigned long loops)
" .align 3 \n" " .align 3 \n"
"1: bnez %0, 1b \n" "1: bnez %0, 1b \n"
#if BITS_PER_LONG == 32 #if BITS_PER_LONG == 32
" subu %0, 1 \n" " subu %0, %1 \n"
#else #else
" dsubu %0, 1 \n" " dsubu %0, %1 \n"
#endif #endif
" .set reorder \n" " .set reorder \n"
: "=r" (loops) : "=r" (loops)
: "0" (loops)); : GCC_DADDI_IMM_ASM() (1), "0" (loops));
} }
EXPORT_SYMBOL(__delay); EXPORT_SYMBOL(__delay);

13
arch/mips/lib/strncpy_user.S
View File

@ -35,7 +35,6 @@ LEAF(__strncpy_from_\func\()_asm)
bnez v0, .Lfault\@ bnez v0, .Lfault\@
FEXPORT(__strncpy_from_\func\()_nocheck_asm) FEXPORT(__strncpy_from_\func\()_nocheck_asm)
.set noreorder
move t0, zero move t0, zero
move v1, a1 move v1, a1
.ifeqs "\func","kernel" .ifeqs "\func","kernel"
@ -45,21 +44,21 @@ FEXPORT(__strncpy_from_\func\()_nocheck_asm)
.endif .endif
PTR_ADDIU v1, 1 PTR_ADDIU v1, 1
R10KCBARRIER(0(ra)) R10KCBARRIER(0(ra))
sb v0, (a0)
beqz v0, 2f beqz v0, 2f
sb v0, (a0)
PTR_ADDIU t0, 1 PTR_ADDIU t0, 1
PTR_ADDIU a0, 1
bne t0, a2, 1b bne t0, a2, 1b
PTR_ADDIU a0, 1
2: PTR_ADDU v0, a1, t0 2: PTR_ADDU v0, a1, t0
xor v0, a1 xor v0, a1
bltz v0, .Lfault\@ bltz v0, .Lfault\@
nop move v0, t0
jr ra # return n jr ra # return n
move v0, t0
END(__strncpy_from_\func\()_asm) END(__strncpy_from_\func\()_asm)
.Lfault\@: jr ra .Lfault\@:
li v0, -EFAULT li v0, -EFAULT
jr ra
.section __ex_table,"a" .section __ex_table,"a"
PTR 1b, .Lfault\@ PTR 1b, .Lfault\@

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