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ftgmac100: Fix potential ordering issue in NAPI poll

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We need to ensure the loads from the descriptor are done after the
MMIO store clearing the interrupts has completed, otherwise we
might still miss work.

A read back from the MMIO register will "push" the posted store and
ioread32 has a barrier on weakly aordered architectures that will
order subsequent accesses.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Benjamin Herrenschmidt 2017-04-18 08:37:05 +10:00 committed by David S. Miller
parent 33de693248
commit ccaf725a1f
1 changed files with 7 additions and 0 deletions
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7
drivers/net/ethernet/faraday/ftgmac100.c
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@ -1349,6 +1349,13 @@ static int ftgmac100_poll(struct napi_struct *napi, int budget)
*/
iowrite32(FTGMAC100_INT_RXTX,
priv->base + FTGMAC100_OFFSET_ISR);
/* Push the above (and provides a barrier vs. subsequent
* reads of the descriptor).
*/
ioread32(priv->base + FTGMAC100_OFFSET_ISR);
/* Check RX and TX descriptors for more work to do */
if (ftgmac100_check_rx(priv) ||
ftgmac100_tx_buf_cleanable(priv))
return budget;