MLK-16538-3: hdmi/dp: Add imx8qm hdmi/dp driver
Add hdmi/dp drm architecture driver. HDMI and DP driver can work in imx8qm ARM2 board. The driver support basic hotplug function. Default working mode is 1080p60. Acked-by: Robby Cai <robby.cai@nxp.com> Signed-off-by: Sandor Yu <Sandor.yu@nxp.com> Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
This commit is contained in:
Sandor Yu
Jason Liu
parent
a0a18c1133
commit
ccf331b51d
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@ -47,3 +47,4 @@ config DRM_IMX_HDMI
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source "drivers/gpu/drm/imx/ipuv3/Kconfig"
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source "drivers/gpu/drm/imx/dpu/Kconfig"
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source "drivers/gpu/drm/imx/hdp/Kconfig"
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@ -12,3 +12,4 @@ obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
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obj-$(CONFIG_DRM_IMX_IPUV3) += ipuv3/
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obj-$(CONFIG_DRM_IMX_DPU) += dpu/
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obj-$(CONFIG_DRM_IMX_HDP) += hdp/
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393
drivers/gpu/drm/imx/hdp/API_AFE_mcu1_dp.c
Normal file
393
drivers/gpu/drm/imx/hdp/API_AFE_mcu1_dp.c
Normal file
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@ -0,0 +1,393 @@
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/******************************************************************************
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*
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* Copyright (C) 2016-2017 Cadence Design Systems, Inc.
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* All rights reserved worldwide.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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* INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
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* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Copyright 2017 NXP
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*
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******************************************************************************
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*
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* API_AFE_mcu1_dp.c
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*
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******************************************************************************
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*/
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#include <linux/delay.h>
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#include "API_AFE_mcu1_dp.h"
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#include "../../../../mxc/hdp/all.h"
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static void AFE_WriteReg(state_struct *state, ENUM_AFE_LINK_RATE link_rate,
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u32 addr, u32 val1_6, u32 val2_7, u32 val5_4)
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{
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switch (link_rate) {
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case AFE_LINK_RATE_1_6:
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Afe_write(state, addr, val1_6);
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break;
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case AFE_LINK_RATE_2_7:
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Afe_write(state, addr, val2_7);
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break;
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case AFE_LINK_RATE_5_4:
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Afe_write(state, addr, val5_4);
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break;
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case AFE_LINK_RATE_8_1: /* Not used in MCU1 */
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default:
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pr_err("Warning. Unsupported Link Rate!\n");
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break;
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}
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}
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void phy_cfg_24mhz(state_struct *state, int num_lanes)
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{
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int k;
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for (k = 0; k < num_lanes; k++) {
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Afe_write(state, XCVR_DIAG_LANE_FCM_EN_MGN_TMR | (k << 9), 0x0090);
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Afe_write(state, TX_RCVDET_EN_TMR | (k << 9), 0x0960);
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Afe_write(state, TX_RCVDET_ST_TMR | (k << 9), 0x0030);
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}
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}
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/* Valid for 24 MHz only */
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void phy_cfg_dp_cmn_pll0(state_struct *state, int num_lanes)
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{
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int k;
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volatile u16 rdata;
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Afe_write(state, PHY_HDP_CLK_CTL, 0x2405);
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Afe_write(state, CMN_PLL0_INTDIV, 0x0086);
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Afe_write(state, CMN_PLL0_FRACDIV, 0xF915);
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Afe_write(state, CMN_PLL0_HIGH_THR, 0x0022);
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Afe_write(state, CMN_PLL0_SS_CTRL1, 0x0140);
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rdata = Afe_read(state, CMN_DIAG_HSCLK_SEL);
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rdata = rdata & 0xFFFC;
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rdata = rdata | 0x0001;
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Afe_write(state, CMN_DIAG_HSCLK_SEL, rdata);
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for (k = 0; k < num_lanes; k = k + 1) {
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rdata = Afe_read(state, (XCVR_DIAG_HSCLK_SEL | (k << 9)));
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rdata = rdata & 0xCFFF;
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rdata = rdata | 0x1000;
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Afe_write(state, (XCVR_DIAG_HSCLK_SEL | (k << 9)), rdata);
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}
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Afe_write(state, CMN_PLL0_VCOCAL_START, 0x3061);
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Afe_write(state, CMN_PLLSM0_USER_DEF_CTRL, 0x0000);
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Afe_write(state, CMN_DIAG_PLL0_V2I_TUNE, 0x0006);
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Afe_write(state, CMN_DIAG_PLL0_PTATIS_TUNE1, 0x008c);
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Afe_write(state, CMN_DIAG_PLL0_PTATIS_TUNE2, 0x002e);
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Afe_write(state, CMN_DIAG_PLL0_CP_TUNE, 0x0026);
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Afe_write(state, CMN_DIAG_PLL0_LF_PROG, 0x0008);
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Afe_write(state, CMN_PLL0_VCOCAL_INIT_TMR, 0x00F0);
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Afe_write(state, CMN_PLL0_VCOCAL_ITER_TMR, 0x0018);
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Afe_write(state, CMN_PLL0_SS_CTRL2, 0x7F03);
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Afe_write(state, CMN_PLL0_DSM_DIAG, 0x0020);
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Afe_write(state, CMN_DIAG_PLL0_OVRD, 0x0000);
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Afe_write(state, CMN_DIAG_PLL0_FBH_OVRD, 0x0000);
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Afe_write(state, CMN_DIAG_PLL0_FBL_OVRD, 0x0000);
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}
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/* Valid for 24 MHz only */
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void phy_cfg_dp_pll0(state_struct *state, int num_lanes, ENUM_AFE_LINK_RATE link_rate)
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{
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int k;
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volatile u16 rdata;
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rdata = Afe_read(state, PHY_HDP_CLK_CTL);
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rdata = rdata & 0x00FF;
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switch (link_rate) {
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case AFE_LINK_RATE_1_6:
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case AFE_LINK_RATE_2_7:
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rdata = rdata | 0x2400;
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break;
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case AFE_LINK_RATE_5_4:
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rdata = rdata | 0x1200;
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break;
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case AFE_LINK_RATE_8_1: /* nNot used in MCU1 */
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default:
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pr_err("Warning. Unsupported Link Rate!\n");
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break;
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}
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Afe_write(state, PHY_HDP_CLK_CTL, rdata);
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rdata = Afe_read(state, CMN_DIAG_HSCLK_SEL);
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rdata = rdata & 0xFFCC;
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switch (link_rate) {
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case AFE_LINK_RATE_1_6:
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case AFE_LINK_RATE_2_7:
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rdata = rdata | 0x0011;
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break;
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case AFE_LINK_RATE_5_4:
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rdata = rdata | 0x0000;
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break;
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case AFE_LINK_RATE_8_1: /* Not used in MCU1 */
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default:
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pr_err("Warning. Unsupported Link Rate!\n");
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break;
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}
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Afe_write(state, CMN_DIAG_HSCLK_SEL, rdata);
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for (k = 0; k < num_lanes; k = k + 1) {
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rdata = Afe_read(state, (XCVR_DIAG_HSCLK_SEL | (k << 9)));
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rdata = rdata & 0xCFFF;
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switch (link_rate) {
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case AFE_LINK_RATE_1_6:
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case AFE_LINK_RATE_2_7:
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rdata = rdata | 0x1000;
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break;
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case AFE_LINK_RATE_5_4:
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rdata = rdata | 0x0000;
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break;
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case AFE_LINK_RATE_8_1: /* Not used in MCU1 */
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default:
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pr_err("Warning. Unsupported Link Rate!\n");
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break;
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}
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Afe_write(state, (XCVR_DIAG_HSCLK_SEL | (k << 9)), rdata);
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}
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AFE_WriteReg(state, link_rate, CMN_PLL0_VCOCAL_START, 0x3061, 0x30D0, 0x30D0);
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AFE_WriteReg(state, link_rate, CMN_PLLSM0_USER_DEF_CTRL, 0x0000, 0x1000,
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0x1000);
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AFE_WriteReg(state, link_rate, CMN_DIAG_PLL0_V2I_TUNE, 0x0006, 0x0007, 0x0007);
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Afe_write(state, CMN_DIAG_PLL0_PTATIS_TUNE1, 0x008C);
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Afe_write(state, CMN_DIAG_PLL0_PTATIS_TUNE2, 0x002E);
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AFE_WriteReg(state, link_rate, CMN_DIAG_PLL0_CP_TUNE, 0x0026, 0x0029, 0x0029);
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Afe_write(state, CMN_DIAG_PLL0_LF_PROG, 0x0008);
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Afe_write(state, CMN_PLL0_VCOCAL_INIT_TMR, 0x00F0);
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Afe_write(state, CMN_PLL0_VCOCAL_ITER_TMR, 0x0018);
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AFE_WriteReg(state, link_rate, CMN_PLL0_INTDIV, 0x0086, 0x00E0, 0x00E0);
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AFE_WriteReg(state, link_rate, CMN_PLL0_FRACDIV, 0xF915, 0xF479, 0xF479);
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AFE_WriteReg(state, link_rate, CMN_PLL0_HIGH_THR, 0x0022, 0x0038, 0x0038);
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AFE_WriteReg(state, link_rate, CMN_PLL0_SS_CTRL1, 0x0140, 0x0204, 0x0204);
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Afe_write(state, CMN_PLL0_SS_CTRL2, 0x7F03);
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Afe_write(state, CMN_PLL0_DSM_DIAG, 0x0020);
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Afe_write(state, CMN_DIAG_PLL0_OVRD, 0x0000);
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Afe_write(state, CMN_DIAG_PLL0_FBH_OVRD, 0x0000);
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Afe_write(state, CMN_DIAG_PLL0_FBL_OVRD, 0x0000);
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for (k = 0; k < num_lanes; k = k + 1) {
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rdata = Afe_read(state, (XCVR_DIAG_PLLDRC_CTRL | (k << 9)));
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rdata = rdata & 0x8FFF;
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switch (link_rate) {
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case AFE_LINK_RATE_1_6:
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case AFE_LINK_RATE_2_7:
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rdata = rdata | 0x2000;
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break;
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case AFE_LINK_RATE_5_4:
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rdata = rdata | 0x1000;
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break;
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case AFE_LINK_RATE_8_1: /* Not used in MCU1 */
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default:
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pr_err("Warning. Unsupported Link Rate!\n");
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break;
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}
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Afe_write(state, (XCVR_DIAG_PLLDRC_CTRL | (k << 9)), rdata);
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}
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}
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void phy_cfg_dp_ln(state_struct *state, int num_lanes)
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{
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int k;
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for (k = 0; k < num_lanes; k = k + 1) {
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Afe_write(state, (XCVR_PSM_RCTRL | (k << 9)), 0xBEFC);
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Afe_write(state, (TX_PSC_A0 | (k << 9)), 0x6799);
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Afe_write(state, (TX_PSC_A1 | (k << 9)), 0x6798);
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Afe_write(state, (TX_PSC_A2 | (k << 9)), 0x0098);
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Afe_write(state, (TX_PSC_A3 | (k << 9)), 0x0098);
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}
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}
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u16 aux_cal_cfg(state_struct *state, u16 prev_calib_code)
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{
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u16 txpu_calib_code;
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u16 txpd_calib_code;
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u16 txpu_adj_calib_code;
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u16 txpd_adj_calib_code;
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u16 new_calib_code;
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u16 rdata;
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txpu_calib_code = Afe_read(state, CMN_TXPUCAL_CTRL);
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txpd_calib_code = Afe_read(state, CMN_TXPDCAL_CTRL);
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txpu_adj_calib_code = Afe_read(state, CMN_TXPU_ADJ_CTRL);
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txpd_adj_calib_code = Afe_read(state, CMN_TXPD_ADJ_CTRL);
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new_calib_code = ((txpu_calib_code + txpd_calib_code) / 2)
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+ txpu_adj_calib_code + txpd_adj_calib_code;
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if (new_calib_code != prev_calib_code) {
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rdata = Afe_read(state, TX_ANA_CTRL_REG_1);
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rdata &= 0xDFFF;
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Afe_write(state, TX_ANA_CTRL_REG_1, rdata);
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Afe_write(state, TX_DIG_CTRL_REG_2, new_calib_code);
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udelay(10000);
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rdata |= 0x2000;
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Afe_write(state, TX_ANA_CTRL_REG_1, rdata);
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udelay(150);
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}
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return new_calib_code;
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}
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void aux_cfg(state_struct *state)
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{
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volatile u16 rdata;
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Afe_write(state, TX_DIG_CTRL_REG_2, 36);
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Afe_write(state, TX_ANA_CTRL_REG_2, 0x0100);
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udelay(150);
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Afe_write(state, TX_ANA_CTRL_REG_2, 0x0300);
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udelay(150);
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Afe_write(state, TX_ANA_CTRL_REG_3, 0x0000);
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udelay(150);
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Afe_write(state, TX_ANA_CTRL_REG_1, 0x2008);
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udelay(150);
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Afe_write(state, TX_ANA_CTRL_REG_1, 0x2018);
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udelay(150);
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Afe_write(state, TX_ANA_CTRL_REG_1, 0xA018);
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udelay(150);
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Afe_write(state, TX_ANA_CTRL_REG_2, 0x030C);
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udelay(150);
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Afe_write(state, TX_ANA_CTRL_REG_5, 0x0000);
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udelay(150);
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Afe_write(state, TX_ANA_CTRL_REG_4, 0x1001);
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udelay(150);
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Afe_write(state, TX_ANA_CTRL_REG_1, 0xA098);
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udelay(5000);
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Afe_write(state, TX_ANA_CTRL_REG_1, 0xA198);
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udelay(5000);
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Afe_write(state, TX_ANA_CTRL_REG_2, 0x030D);
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udelay(5000);
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Afe_write(state, TX_ANA_CTRL_REG_2, 0x030F);
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udelay(5000);
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pr_info("TX_ANA_CTRL_REG_1 %x)\n", rdata);
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rdata = Afe_read(state, TX_ANA_CTRL_REG_2);
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pr_info("TX_ANA_CTRL_REG_2 %x)\n", rdata);
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rdata = Afe_read(state, TX_ANA_CTRL_REG_3);
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pr_info("TX_ANA_CTRL_REG_3 %x)\n", rdata);
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rdata = Afe_read(state, TX_ANA_CTRL_REG_4);
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pr_info("TX_ANA_CTRL_REG_4 %x)\n", rdata);
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rdata = Afe_read(state, TX_ANA_CTRL_REG_5);
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pr_info("TX_ANA_CTRL_REG_5 %x)\n", rdata);
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}
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void AFE_init(state_struct *state, int num_lanes, ENUM_AFE_LINK_RATE link_rate)
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{
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volatile u16 val;
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val = Afe_read(state, PHY_PMA_CMN_CTRL1);
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val = val & 0xFFF7;
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val = val | 0x0008;
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Afe_write(state, PHY_PMA_CMN_CTRL1, val);
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Afe_write(state, CMN_DIAG_PLL0_TEST_MODE, 0x0020);
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Afe_write(state, CMN_PSM_CLK_CTRL, 0x0016);
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phy_cfg_24mhz(state, num_lanes);
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phy_cfg_dp_pll0(state, num_lanes, link_rate);
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val = Afe_read(state, PHY_PMA_CMN_CTRL1);
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val = val & 0xFF8F;
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val = val | 0x0030;
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Afe_write(state, PHY_PMA_CMN_CTRL1, val);
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phy_cfg_dp_ln(state, num_lanes);
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/* Configure PHY in A2 Mode */
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Afe_write(state, PHY_HDP_MODE_CTRL, 0x0004);
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}
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void AFE_power(state_struct *state, int num_lanes, ENUM_AFE_LINK_RATE link_rate)
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{
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static u16 prev_calib_code;
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volatile u16 val;
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Afe_write(state, TX_DIAG_ACYA_0, 1);
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Afe_write(state, TX_DIAG_ACYA_1, 1);
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Afe_write(state, TX_DIAG_ACYA_2, 1);
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Afe_write(state, TX_DIAG_ACYA_3, 1);
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Afe_write(state, TXDA_CYA_AUXDA_CYA, 1);
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/* Wait for A2 ACK (PHY_HDP_MODE_CTL [6] = 1’b1) */
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do {
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val = Afe_read(state, PHY_HDP_MODE_CTRL);
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val = val >> 6;
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} while ((val & 1) == 0);
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/* to check if PLL has locked (bit 6) */
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val = Afe_read(state, PHY_PMA_CMN_CTRL2);
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val = val >> 6;
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||||
|
||||
if ((val & 1) == 0) {
|
||||
pr_err("ERROR: PLL is not locked\n");
|
||||
} else {
|
||||
pr_info("PHY_PMA_CMN_CTRL2 = %x\n", val);
|
||||
}
|
||||
|
||||
/* to check if cmn_ready is asserted (bit 0) */
|
||||
val = Afe_read(state, PHY_PMA_CMN_CTRL1);
|
||||
|
||||
if ((val & 1) == 0) {
|
||||
pr_err("ERROR: cmn_ready is not asserted\n");
|
||||
} else {
|
||||
pr_info("PHY_PMA_CMN_CTRL1 = %x\n", val);
|
||||
}
|
||||
|
||||
/* Configure PHY in A0 mode (PHY must be in the A0 power state in order to transmit data) */
|
||||
Afe_write(state, PHY_HDP_MODE_CTRL, 0x0101);
|
||||
|
||||
/* Wait for A2 ACK (PHY_HDP_MODE_CTL [4] = 1’b1) */
|
||||
do {
|
||||
val = Afe_read(state, PHY_HDP_MODE_CTRL);
|
||||
val = val >> 4;
|
||||
} while ((val & 1) == 0);
|
||||
|
||||
prev_calib_code = aux_cal_cfg(state, prev_calib_code);
|
||||
|
||||
aux_cfg(state);
|
||||
|
||||
}
|
||||
165
drivers/gpu/drm/imx/hdp/API_AFE_mcu1_dp.h
Normal file
165
drivers/gpu/drm/imx/hdp/API_AFE_mcu1_dp.h
Normal file
|
|
@ -0,0 +1,165 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2016-2017 Cadence Design Systems, Inc.
|
||||
* All rights reserved worldwide.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software without
|
||||
* specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
|
||||
* INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
|
||||
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
|
||||
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
******************************************************************************
|
||||
*
|
||||
* API_AFE_mcu1_dp.h
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef API_AFE_MCU1_DP_H
|
||||
# define API_AFE_MCU1_DP_H
|
||||
|
||||
#define PHY_PMA_CMN_CTRL1 0xC800
|
||||
#define PHY_PMA_CMN_CTRL2 0xC801
|
||||
#define XCVR_DIAG_LANE_FCM_EN_MGN_TMR 0x40F2
|
||||
#define XCVR_DIAG_LANE_FCM_EN_MGN_TMR_0 0x40F2
|
||||
#define XCVR_DIAG_LANE_FCM_EN_MGN_TMR_1 0x42F2
|
||||
#define XCVR_DIAG_LANE_FCM_EN_MGN_TMR_2 0x44F2
|
||||
#define XCVR_DIAG_LANE_FCM_EN_MGN_TMR_3 0x46F2
|
||||
#define TX_RCVDET_EN_TMR 0x4122
|
||||
#define TX_RCVDET_EN_TMR_0 0x4122
|
||||
#define TX_RCVDET_EN_TMR_1 0x4322
|
||||
#define TX_RCVDET_EN_TMR_2 0x4522
|
||||
#define TX_RCVDET_EN_TMR_3 0x4722
|
||||
#define TX_RCVDET_ST_TMR 0x4123
|
||||
#define TX_RCVDET_ST_TMR_0 0x4123
|
||||
#define TX_RCVDET_ST_TMR_1 0x4323
|
||||
#define TX_RCVDET_ST_TMR_2 0x4523
|
||||
#define TX_RCVDET_ST_TMR_3 0x4723
|
||||
#define PHY_HDP_CLK_CTL 0xC009
|
||||
#define CMN_DIAG_HSCLK_SEL 0x01E0
|
||||
#define XCVR_DIAG_HSCLK_SEL 0x40E1
|
||||
#define XCVR_DIAG_HSCLK_SEL_0 0x40E1
|
||||
#define XCVR_DIAG_HSCLK_SEL_1 0x42E1
|
||||
#define XCVR_DIAG_HSCLK_SEL_2 0x44E1
|
||||
#define XCVR_DIAG_HSCLK_SEL_3 0x46E1
|
||||
#define CMN_PLL0_VCOCAL_START 0x0081
|
||||
#define CMN_PLLSM0_USER_DEF_CTRL 0x002F
|
||||
#define CMN_DIAG_PLL0_V2I_TUNE 0x01C5
|
||||
#define CMN_DIAG_PLL0_PTATIS_TUNE1 0x01C8
|
||||
#define CMN_DIAG_PLL0_PTATIS_TUNE2 0x01C9
|
||||
#define CMN_DIAG_PLL0_CP_TUNE 0x01C6
|
||||
#define CMN_DIAG_PER_CAL_ADJ 0x01EC
|
||||
#define CMN_DIAG_PLL0_LF_PROG 0x01C7
|
||||
#define CMN_PLL0_VCOCAL_INIT_TMR 0x0084
|
||||
#define CMN_PLL0_VCOCAL_ITER_TMR 0x0085
|
||||
#define CMN_PLL0_INTDIV 0x0094
|
||||
#define CMN_PLL0_FRACDIV 0x0095
|
||||
#define CMN_PLL0_HIGH_THR 0x0096
|
||||
#define CMN_PLL0_SS_CTRL1 0x0098
|
||||
#define CMN_PLL0_SS_CTRL2 0x0099
|
||||
#define CMN_PLL0_DSM_DIAG 0x0097
|
||||
#define CMN_DIAG_PLL0_OVRD 0x01C2
|
||||
#define CMN_DIAG_PLL0_FBH_OVRD 0x01C0
|
||||
#define CMN_DIAG_PLL0_FBL_OVRD 0x01C1
|
||||
#define XCVR_DIAG_PLLDRC_CTRL 0x40E0
|
||||
#define XCVR_DIAG_PLLDRC_CTRL_0 0x40E0
|
||||
#define XCVR_DIAG_PLLDRC_CTRL_1 0x42E0
|
||||
#define XCVR_DIAG_PLLDRC_CTRL_2 0x44E0
|
||||
#define XCVR_DIAG_PLLDRC_CTRL_3 0x46E0
|
||||
#define CMN_DIAG_PLL0_TEST_MODE 0x01C4
|
||||
#define PHY_HDP_MODE_CTRL 0xC008
|
||||
#define XCVR_PSM_RCTRL 0x4001
|
||||
#define XCVR_PSM_RCTRL_0 0x4001
|
||||
#define XCVR_PSM_RCTRL_1 0x4201
|
||||
#define XCVR_PSM_RCTRL_2 0x4401
|
||||
#define XCVR_PSM_RCTRL_3 0x4601
|
||||
#define TX_PSC_A0 0x4100
|
||||
#define TX_PSC_A0_0 0x4100
|
||||
#define TX_PSC_A0_1 0x4300
|
||||
#define TX_PSC_A0_2 0x4500
|
||||
#define TX_PSC_A0_3 0x4700
|
||||
#define TX_PSC_A1 0x4101
|
||||
#define TX_PSC_A1_0 0x4101
|
||||
#define TX_PSC_A1_1 0x4301
|
||||
#define TX_PSC_A1_2 0x4501
|
||||
#define TX_PSC_A1_3 0x4701
|
||||
#define TX_PSC_A2 0x4102
|
||||
#define TX_PSC_A2_0 0x4102
|
||||
#define TX_PSC_A2_1 0x4302
|
||||
#define TX_PSC_A2_2 0x4502
|
||||
#define TX_PSC_A2_3 0x4702
|
||||
#define TX_PSC_A3 0x4103
|
||||
#define TX_PSC_A3_0 0x4103
|
||||
#define TX_PSC_A3_1 0x4303
|
||||
#define TX_PSC_A3_2 0x4503
|
||||
#define TX_PSC_A3_3 0x4703
|
||||
#define TX_DIAG_TX_DRV 0x41E1
|
||||
#define TX_DIAG_TX_DRV_0 0x41E1
|
||||
#define TX_DIAG_TX_DRV_1 0x43E1
|
||||
#define TX_DIAG_TX_DRV_2 0x45E1
|
||||
#define TX_DIAG_TX_DRV_3 0x47E1
|
||||
#define PHY_HDP_MODE CTRL 0xC008
|
||||
#define TX_DIAG_ACYA_0 0x41ff
|
||||
#define TX_DIAG_ACYA_1 0x43ff
|
||||
#define TX_DIAG_ACYA_2 0x45ff
|
||||
#define TX_DIAG_ACYA_3 0x47ff
|
||||
|
||||
#define TX_TXCC_MGNFS_MULT_000_0 0x4050
|
||||
#define TX_TXCC_MGNFS_MULT_000_1 0x4250
|
||||
#define TX_TXCC_MGNFS_MULT_000_2 0x4450
|
||||
#define TX_TXCC_MGNFS_MULT_000_3 0x4650
|
||||
|
||||
#define TX_TXCC_CPOST_MULT_00_0 0x404C
|
||||
#define TX_TXCC_CPOST_MULT_00_1 0x424C
|
||||
#define TX_TXCC_CPOST_MULT_00_2 0x444C
|
||||
#define TX_TXCC_CPOST_MULT_00_3 0x464C
|
||||
|
||||
#define TX_ANA_CTRL_REG_1 0x5020
|
||||
#define TX_ANA_CTRL_REG_2 0x5021
|
||||
#define TX_ANA_CTRL_REG_3 0x5026
|
||||
#define TX_ANA_CTRL_REG_4 0x5027
|
||||
#define TX_ANA_CTRL_REG_5 0x5029
|
||||
|
||||
#define TX_DIG_CTRL_REG_2 0x5024
|
||||
#define TX_DIG_CTRL_REG_1 0x5023
|
||||
#define TXDA_CYA_AUXDA_CYA 0x5025
|
||||
#define CMN_TXPUCAL_CTRL 0x00E0
|
||||
#define CMN_TXPDCAL_CTRL 0x00F0
|
||||
#define CMN_TXPU_ADJ_CTRL 0x0108
|
||||
#define CMN_TXPD_ADJ_CTRL 0x010c
|
||||
#define TXDA_COEFF_CALC 0x5022
|
||||
#define CMN_PSM_CLK_CTRL 0x0061
|
||||
|
||||
#define PHY_HDP_TX_CTL_L0 0xC408
|
||||
#define PHY_HDP_TX_CTL_L1 0xC448
|
||||
#define PHY_HDP_TX_CTL_L2 0xC488
|
||||
#define PHY_HDP_TX_CTL_L3 0xC4C8
|
||||
|
||||
#endif //API_AFE_MCU1_DP_H
|
||||
592
drivers/gpu/drm/imx/hdp/API_AFE_ss28fdsoi_kiran_hdmitx.c
Normal file
592
drivers/gpu/drm/imx/hdp/API_AFE_ss28fdsoi_kiran_hdmitx.c
Normal file
|
|
@ -0,0 +1,592 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2016-2017 Cadence Design Systems, Inc.
|
||||
* All rights reserved worldwide.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software without
|
||||
* specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
|
||||
* INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
|
||||
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
|
||||
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
******************************************************************************
|
||||
*
|
||||
* API_AFE_ss28fdsoi_kiran_hdmitx.c
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include "API_AFE_ss28fdsoi_kiran_hdmitx.h"
|
||||
#include "ss28fdsoi_hdmitx_table.h"
|
||||
|
||||
static int inside(u32 value, u32 left_sharp_corner,
|
||||
u32 right_sharp_corner)
|
||||
{
|
||||
if (value < left_sharp_corner)
|
||||
return 0;
|
||||
if (value > right_sharp_corner)
|
||||
return 0;
|
||||
return 1;
|
||||
}
|
||||
|
||||
int get_table_row_match_column(const u32 *array, u32 table_rows,
|
||||
u32 table_cols, u32 start_row,
|
||||
u32 column_to_search,
|
||||
u32 value_to_search_in_column)
|
||||
{
|
||||
u32 idx_cols, idx_rows;
|
||||
u32 value;
|
||||
for (idx_rows = start_row; idx_rows < table_rows; idx_rows++) {
|
||||
for (idx_cols = 0; idx_cols < table_cols; idx_cols++) {
|
||||
/* pr_info("get_table_row_match_column: TAG row: %0d, col: %0d, value: %0d\n",
|
||||
idx_rows, idx_cols, *((array + idx_rows * table_cols) + idx_cols)); */
|
||||
if (idx_cols == column_to_search) {
|
||||
value =
|
||||
*((array + idx_rows * table_cols) +
|
||||
idx_cols);
|
||||
if (value == value_to_search_in_column) {
|
||||
return idx_rows;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
int get_table_row(const u32 *array, u32 table_rows,
|
||||
u32 table_cols, u32 variable_in_range,
|
||||
u32 range_min_column, u32 range_max_column,
|
||||
u32 column_to_search, u32 column_value)
|
||||
{
|
||||
u32 i = 0;
|
||||
while (1) {
|
||||
i = get_table_row_match_column(array, table_rows, table_cols, i,
|
||||
column_to_search, column_value);
|
||||
if (i + 1) {
|
||||
if (inside(variable_in_range,
|
||||
*((array + i * table_cols) + range_min_column),
|
||||
*((array + i * table_cols) + range_max_column))) {
|
||||
break;
|
||||
}
|
||||
i++;
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
}
|
||||
return i;
|
||||
}
|
||||
|
||||
int phy_cfg_hdp_ss28fdsoi(state_struct *state, int num_lanes, VIC_MODES vicMode, int bpp,
|
||||
VIC_PXL_ENCODING_FORMAT format)
|
||||
{
|
||||
const int phy_reset_workaround = 0;
|
||||
u32 vco_freq_khz;
|
||||
unsigned char i;
|
||||
u32 row, feedback_factor;
|
||||
uint32_t reg_val;
|
||||
int pixel_freq_khz = vic_table[vicMode][PIXEL_FREQ_KHZ];
|
||||
uint32_t character_clock_ratio_num = 1;
|
||||
uint32_t character_clock_ratio_den = 1;
|
||||
int character_freq_khz;
|
||||
u32 ftemp;
|
||||
clk_ratio_t clk_ratio = CLK_RATIO_1_1;
|
||||
|
||||
reg_field_t cmnda_pll0_hs_sym_div_sel;
|
||||
reg_field_t cmnda_pll0_ip_div;
|
||||
reg_field_t cmnda_pll0_fb_div_low;
|
||||
reg_field_t cmnda_pll0_fb_div_high;
|
||||
reg_field_t cmn_ref_clk_dig_div;
|
||||
reg_field_t divider_scaler;
|
||||
reg_field_t cmnda_hs_clk_0_sel;
|
||||
reg_field_t cmnda_hs_clk_1_sel;
|
||||
reg_field_t tx_subrate;
|
||||
reg_field_t vco_ring_select;
|
||||
reg_field_t pll_feedback_divider_total;
|
||||
reg_field_t voltage_to_current_coarse;
|
||||
reg_field_t voltage_to_current;
|
||||
reg_field_t ndac_ctrl;
|
||||
reg_field_t pmos_ctrl;
|
||||
reg_field_t ptat_ndac_ctrl;
|
||||
reg_field_t charge_pump_gain;
|
||||
|
||||
/* Set field position in a target register */
|
||||
cmnda_pll0_fb_div_high.value = 0x00A;
|
||||
cmnda_pll0_hs_sym_div_sel.msb = 9;
|
||||
cmnda_pll0_hs_sym_div_sel.lsb = 8;
|
||||
cmnda_pll0_ip_div.msb = 7;
|
||||
cmnda_pll0_ip_div.lsb = 0;
|
||||
cmnda_pll0_fb_div_low.msb = 9;
|
||||
cmnda_pll0_fb_div_low.lsb = 0;
|
||||
cmnda_pll0_fb_div_high.msb = 9;
|
||||
cmnda_pll0_fb_div_high.lsb = 0;
|
||||
cmn_ref_clk_dig_div.msb = 13;
|
||||
cmn_ref_clk_dig_div.lsb = 12;
|
||||
divider_scaler.msb = 14;
|
||||
divider_scaler.lsb = 12;
|
||||
cmnda_hs_clk_0_sel.msb = 1;
|
||||
cmnda_hs_clk_0_sel.lsb = 0;
|
||||
cmnda_hs_clk_1_sel.msb = 1;
|
||||
cmnda_hs_clk_1_sel.lsb = 0;
|
||||
tx_subrate.msb = 2;
|
||||
tx_subrate.lsb = 0;
|
||||
vco_ring_select.msb = 12;
|
||||
vco_ring_select.lsb = 12;
|
||||
pll_feedback_divider_total.msb = 9;
|
||||
pll_feedback_divider_total.lsb = 0;
|
||||
voltage_to_current_coarse.msb = 2;
|
||||
voltage_to_current_coarse.lsb = 0;
|
||||
voltage_to_current.msb = 5;
|
||||
voltage_to_current.lsb = 4;
|
||||
ndac_ctrl.msb = 11;
|
||||
ndac_ctrl.lsb = 8;
|
||||
pmos_ctrl.msb = 7;
|
||||
pmos_ctrl.lsb = 0;
|
||||
ptat_ndac_ctrl.msb = 5;
|
||||
ptat_ndac_ctrl.lsb = 0;
|
||||
charge_pump_gain.msb = 8;
|
||||
charge_pump_gain.lsb = 0;
|
||||
|
||||
pr_info
|
||||
("phy_cfg_hdp() num_lanes: %0d, vicMode: %0d, color depth: %0d-bit, encoding: %0d\n",
|
||||
num_lanes, vicMode, bpp, format);
|
||||
|
||||
/* register PHY_PMA_ISOLATION_CTRL
|
||||
enable PHY isolation mode only for CMN */
|
||||
if (phy_reset_workaround) {
|
||||
Afe_write(state, 0xC81F, 0xD000);
|
||||
reg_val = Afe_read(state, 0xC812);
|
||||
reg_val &= 0xFF00;
|
||||
reg_val |= 0x0012;
|
||||
/* set cmn_pll0_clk_datart1_div/cmn_pll0_clk_datart0_div dividers */
|
||||
Afe_write(state, 0xC812, reg_val);
|
||||
/* register PHY_ISO_CMN_CTRL */
|
||||
Afe_write(state, 0xC010, 0x0000); /* assert PHY reset from isolation register */
|
||||
/* register PHY_PMA_ISO_CMN_CTRL */
|
||||
Afe_write(state, 0xC810, 0x0000); /* assert PMA CMN reset */
|
||||
/* register XCVR_DIAG_BIDI_CTRL */
|
||||
for (i = 0; i < num_lanes; i++) {
|
||||
Afe_write(state, 0x40E8 | (i << 9), 0x00FF);
|
||||
}
|
||||
} else {
|
||||
/*--------------------------------------------------------------
|
||||
* Describing Task phy_cfg_hdp
|
||||
* ------------------------------------------------------------*/
|
||||
/* register PHY_PMA_CMN_CTRL1 */
|
||||
for (i = 0; i < num_lanes; i++)
|
||||
Afe_write(state, 0x40E8 | (i << 9), 0x007F);
|
||||
}
|
||||
/* register CMN_DIAG_PLL0_TEST_MODE */
|
||||
Afe_write(state, 0x01C4, 0x0020);
|
||||
/* register CMN_PSM_CLK_CTRL */
|
||||
Afe_write(state, 0x0061, 0x0016);
|
||||
|
||||
/* Determine the TMDS/PIXEL clock ratio */
|
||||
switch (format) {
|
||||
case YCBCR_4_2_2:
|
||||
clk_ratio = CLK_RATIO_1_1;
|
||||
character_clock_ratio_num = 1;
|
||||
character_clock_ratio_den = 1;
|
||||
break;
|
||||
case YCBCR_4_2_0:
|
||||
switch (bpp) {
|
||||
case 8:
|
||||
clk_ratio = CLK_RATIO_1_2;
|
||||
character_clock_ratio_num = 1;
|
||||
character_clock_ratio_den = 2;
|
||||
break;
|
||||
case 10:
|
||||
clk_ratio = CLK_RATIO_5_8;
|
||||
character_clock_ratio_num = 5;
|
||||
character_clock_ratio_den = 8;
|
||||
break;
|
||||
case 12:
|
||||
clk_ratio = CLK_RATIO_3_4;
|
||||
character_clock_ratio_num = 3;
|
||||
character_clock_ratio_den = 4;
|
||||
break;
|
||||
case 16:
|
||||
clk_ratio = CLK_RATIO_1_1;
|
||||
character_clock_ratio_num = 1;
|
||||
character_clock_ratio_den = 1;
|
||||
break;
|
||||
default:
|
||||
pr_err("Invalid ColorDepth\n");
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
switch (bpp) { /* Assume RGB */
|
||||
case 10:
|
||||
clk_ratio = CLK_RATIO_5_4;
|
||||
character_clock_ratio_num = 5;
|
||||
character_clock_ratio_den = 4;
|
||||
break;
|
||||
case 12:
|
||||
clk_ratio = CLK_RATIO_3_2;
|
||||
character_clock_ratio_num = 3;
|
||||
character_clock_ratio_den = 2;
|
||||
break;
|
||||
case 16:
|
||||
clk_ratio = CLK_RATIO_2_1;
|
||||
character_clock_ratio_num = 2;
|
||||
character_clock_ratio_den = 1;
|
||||
break;
|
||||
default:
|
||||
clk_ratio = CLK_RATIO_1_1;
|
||||
character_clock_ratio_num = 1;
|
||||
character_clock_ratio_den = 1;
|
||||
}
|
||||
}
|
||||
|
||||
/* Determine a relevant feedback factor as used
|
||||
* in the ss28fdsoi_hdmitx_clock_control_table table */
|
||||
switch (clk_ratio) {
|
||||
case CLK_RATIO_1_1:
|
||||
feedback_factor = 1000;
|
||||
break;
|
||||
case CLK_RATIO_5_4:
|
||||
feedback_factor = 1250;
|
||||
break;
|
||||
case CLK_RATIO_3_2:
|
||||
feedback_factor = 1500;
|
||||
break;
|
||||
case CLK_RATIO_2_1:
|
||||
feedback_factor = 2000;
|
||||
break;
|
||||
case CLK_RATIO_1_2:
|
||||
feedback_factor = 500;
|
||||
break;
|
||||
case CLK_RATIO_5_8:
|
||||
feedback_factor = 625;
|
||||
break;
|
||||
case CLK_RATIO_3_4:
|
||||
feedback_factor = 750;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Get right row from the ss28fdsoi_hdmitx_clock_control_table table.
|
||||
* Check if 'pixel_freq_khz' falls inside the
|
||||
* <PIXEL_CLK_FREQ_KHZ_MIN, PIXEL_CLK_FREQ_KHZ_MAX> range.
|
||||
* Consider only the rows with FEEDBACK_FACTOR column matching feedback_factor. */
|
||||
row =
|
||||
get_table_row((const u32 *)&ss28fdsoi_hdmitx_clock_control_table,
|
||||
SS28FDSOI_HDMITX_CLOCK_CONTROL_TABLE_ROWS,
|
||||
SS28FDSOI_HDMITX_CLOCK_CONTROL_TABLE_COLS,
|
||||
pixel_freq_khz, PIXEL_CLK_FREQ_KHZ_MIN,
|
||||
PIXEL_CLK_FREQ_KHZ_MAX, FEEDBACK_FACTOR,
|
||||
feedback_factor);
|
||||
|
||||
/* Check if row was found */
|
||||
ftemp = pixel_freq_khz;
|
||||
if (row + 1) {
|
||||
pr_info
|
||||
("Pixel clock frequency (%u kHz) is supported in this color depth (%0d-bit). Settings found in row %0d\n",
|
||||
ftemp, bpp, row);
|
||||
} else {
|
||||
pr_info
|
||||
("Pixel clock frequency (%u kHz) not supported for this color depth (%0d-bit), row=%d\n",
|
||||
ftemp, bpp, row);
|
||||
}
|
||||
character_freq_khz = pixel_freq_khz * character_clock_ratio_num / character_clock_ratio_den;
|
||||
ftemp = character_freq_khz;
|
||||
pr_info("Character clock frequency: %u kHz.\n", ftemp);
|
||||
|
||||
/* Extract particular values from the ss28fdsoi_hdmitx_clock_control_table table */
|
||||
set_field_value(&cmnda_pll0_hs_sym_div_sel,
|
||||
ss28fdsoi_hdmitx_clock_control_table[row]
|
||||
[CMNDA_PLL0_HS_SYM_DIV_SEL]);
|
||||
set_field_value(&cmnda_pll0_ip_div,
|
||||
ss28fdsoi_hdmitx_clock_control_table[row]
|
||||
[CMNDA_PLL0_IP_DIV]);
|
||||
set_field_value(&cmnda_pll0_fb_div_low,
|
||||
ss28fdsoi_hdmitx_clock_control_table[row]
|
||||
[CMNDA_PLL0_FB_DIV_LOW]);
|
||||
set_field_value(&cmnda_pll0_fb_div_high,
|
||||
ss28fdsoi_hdmitx_clock_control_table[row]
|
||||
[CMNDA_PLL0_FB_DIV_HIGH]);
|
||||
set_field_value(&cmn_ref_clk_dig_div,
|
||||
ss28fdsoi_hdmitx_clock_control_table[row]
|
||||
[CMN_REF_CLK_DIG_DIV]);
|
||||
set_field_value(÷r_scaler,
|
||||
ss28fdsoi_hdmitx_clock_control_table[row]
|
||||
[REF_CLK_DIVIDER_SCALER]);
|
||||
set_field_value(&cmnda_hs_clk_0_sel,
|
||||
ss28fdsoi_hdmitx_clock_control_table[row]
|
||||
[CMNDA_HS_CLK_0_SEL]);
|
||||
set_field_value(&cmnda_hs_clk_1_sel,
|
||||
ss28fdsoi_hdmitx_clock_control_table[row]
|
||||
[CMNDA_HS_CLK_1_SEL]);
|
||||
set_field_value(&tx_subrate,
|
||||
ss28fdsoi_hdmitx_clock_control_table[row]
|
||||
[HSCLK_DIV_TX_SUB_RATE]);
|
||||
set_field_value(&vco_ring_select,
|
||||
ss28fdsoi_hdmitx_clock_control_table[row]
|
||||
[VCO_RING_SELECT]);
|
||||
set_field_value(&pll_feedback_divider_total,
|
||||
ss28fdsoi_hdmitx_clock_control_table[row]
|
||||
[PLL_FB_DIV_TOTAL]);
|
||||
|
||||
/* Display parameters (informative message) */
|
||||
pr_info("set_field_value() cmnda_pll0_hs_sym_div_sel : 0x%X\n",
|
||||
cmnda_pll0_hs_sym_div_sel.value);
|
||||
pr_info("set_field_value() cmnda_pll0_ip_div : 0x%02X\n",
|
||||
cmnda_pll0_ip_div.value);
|
||||
pr_info("set_field_value() cmnda_pll0_fb_div_low : 0x%03X\n",
|
||||
cmnda_pll0_fb_div_low.value);
|
||||
pr_info("set_field_value() cmnda_pll0_fb_div_high : 0x%03X\n",
|
||||
cmnda_pll0_fb_div_high.value);
|
||||
pr_info("set_field_value() cmn_ref_clk_dig_div : 0x%X\n",
|
||||
cmn_ref_clk_dig_div.value);
|
||||
pr_info("set_field_value() divider_scaler : 0x%X\n",
|
||||
divider_scaler.value);
|
||||
pr_info("set_field_value() cmnda_hs_clk_0_sel : %0d\n",
|
||||
cmnda_hs_clk_0_sel.value);
|
||||
pr_info("set_field_value() cmnda_hs_clk_1_sel : %0d\n",
|
||||
cmnda_hs_clk_1_sel.value);
|
||||
pr_info("set_field_value() tx_subrate : %0d\n",
|
||||
tx_subrate.value);
|
||||
pr_info("set_field_value() vco_ring_select : %0d\n",
|
||||
vco_ring_select.value);
|
||||
pr_info("set_field_value() pll_feedback_divider_total: %0d\n",
|
||||
pll_feedback_divider_total.value);
|
||||
|
||||
vco_freq_khz =
|
||||
pixel_freq_khz * pll_feedback_divider_total.value /
|
||||
cmnda_pll0_ip_div.value;
|
||||
|
||||
/* Get right row from the ss28fdsoi_hdmitx_pll_tuning_table table.
|
||||
* Check if 'vco_freq_mhz' falls inside the
|
||||
* <PLL_VCO_FREQ_MHZ_MIN, PLL_VCO_FREQ_MHZ_MAX> range.
|
||||
* Consider only the rows with PLL_FEEDBACK_DIV_TOTAL.
|
||||
* column matching pll_feedback_divider_total. */
|
||||
row =
|
||||
get_table_row((const u32 *)&ss28fdsoi_hdmitx_pll_tuning_table,
|
||||
SS28FDSOI_HDMITX_PLL_TUNING_TABLE_ROWS,
|
||||
SS28FDSOI_HDMITX_PLL_TUNING_TABLE_COLS, vco_freq_khz,
|
||||
PLL_VCO_FREQ_KHZ_MIN, PLL_VCO_FREQ_KHZ_MAX,
|
||||
PLL_FEEDBACK_DIV_TOTAL,
|
||||
pll_feedback_divider_total.value);
|
||||
ftemp = vco_freq_khz;
|
||||
if (row + 1) {
|
||||
pr_info
|
||||
("VCO frequency (%u kHz) is supported. Settings found in row %0d\n",
|
||||
ftemp, row);
|
||||
} else {
|
||||
pr_info("VCO frequency (%u kHz) not supported\n", ftemp);
|
||||
}
|
||||
|
||||
/* Extract particular values from the ss28fdsoi_hdmitx_pll_tuning_table table */
|
||||
set_field_value(&voltage_to_current_coarse,
|
||||
ss28fdsoi_hdmitx_pll_tuning_table[row]
|
||||
[VOLTAGE_TO_CURRENT_COARSE]);
|
||||
set_field_value(&voltage_to_current,
|
||||
ss28fdsoi_hdmitx_pll_tuning_table[row]
|
||||
[VOLTAGE_TO_CURRENT]);
|
||||
set_field_value(&ndac_ctrl,
|
||||
ss28fdsoi_hdmitx_pll_tuning_table[row][NDAC_CTRL]);
|
||||
set_field_value(&pmos_ctrl,
|
||||
ss28fdsoi_hdmitx_pll_tuning_table[row][PMOS_CTRL]);
|
||||
set_field_value(&ptat_ndac_ctrl,
|
||||
ss28fdsoi_hdmitx_pll_tuning_table[row][PTAT_NDAC_CTRL]);
|
||||
set_field_value(&charge_pump_gain,
|
||||
ss28fdsoi_hdmitx_pll_tuning_table[row]
|
||||
[CHARGE_PUMP_GAIN]);
|
||||
|
||||
/* Display parameters (informative message) */
|
||||
pr_info("set_field_value() voltage_to_current_coarse : 0x%X\n",
|
||||
voltage_to_current_coarse.value);
|
||||
pr_info("set_field_value() voltage_to_current : 0x%X\n",
|
||||
voltage_to_current.value);
|
||||
pr_info("set_field_value() ndac_ctrl : 0x%X\n",
|
||||
ndac_ctrl.value);
|
||||
pr_info("set_field_value() pmos_ctrl : 0x%02X\n",
|
||||
pmos_ctrl.value);
|
||||
pr_info("set_field_value() ptat_ndac_ctrl : 0x%02X\n",
|
||||
ptat_ndac_ctrl.value);
|
||||
pr_info("set_field_value() charge_pump_gain : 0x%03X\n",
|
||||
charge_pump_gain.value);
|
||||
|
||||
/* ---------------------------------------------------------------
|
||||
* Describing Task phy_cfg_hdmi_pll0_0pt5736
|
||||
*---------------------------------------------------------------*/
|
||||
|
||||
Afe_write(state, 0x0081, 0x30A0);
|
||||
/* register CMN_PLL0_VCOCAL_INIT_TMR */
|
||||
Afe_write(state, 0x0084, 0x0064);
|
||||
/* register CMN_PLL0_VCOCAL_ITER_TMR */
|
||||
Afe_write(state, 0x0085, 0x000A);
|
||||
/* register PHY_HDP_CLK_CTL */
|
||||
reg_val = Afe_read(state, 0xC009);
|
||||
reg_val &= 0x00FF;
|
||||
reg_val |= 0x1200;
|
||||
Afe_write(state, 0xC009, reg_val);
|
||||
/* register CMN_DIAG_PLL0_INCLK_CTRL */
|
||||
reg_val = set_reg_value(cmnda_pll0_hs_sym_div_sel);
|
||||
reg_val |= set_reg_value(cmnda_pll0_ip_div);
|
||||
Afe_write(state, 0x01CA, reg_val);
|
||||
/* register CMN_DIAG_PLL0_FBL_OVRD */
|
||||
reg_val = set_reg_value(cmnda_pll0_fb_div_low);
|
||||
reg_val |= (1 << 15);
|
||||
Afe_write(state, 0x01C1, reg_val);
|
||||
/* register PHY_PMA_CMN_CTRL1 */
|
||||
reg_val = Afe_read(state, 0xC800);
|
||||
reg_val &= 0xCFFF;
|
||||
reg_val |= set_reg_value(cmn_ref_clk_dig_div);
|
||||
Afe_write(state, 0xC800, reg_val);
|
||||
/* register CMN_CDIAG_REFCLK_CTRL */
|
||||
reg_val = set_reg_value(divider_scaler);
|
||||
Afe_write(state, 0x0062, reg_val);
|
||||
/* register CMN_DIAG_HSCLK_SEL */
|
||||
reg_val = Afe_read(state, 0x01E0);
|
||||
reg_val &= 0xFF00;
|
||||
reg_val |= (cmnda_hs_clk_0_sel.value >> 1) << 0;
|
||||
reg_val |= (cmnda_hs_clk_1_sel.value >> 1) << 4;
|
||||
Afe_write(state, 0x01E0, reg_val);
|
||||
|
||||
/* register XCVR_DIAG_HSCLK_SEL */
|
||||
for (i = 0; i < num_lanes; i++) {
|
||||
reg_val = Afe_read(state, 0x40E1 | (i << 9));
|
||||
reg_val &= 0xCFFF;
|
||||
reg_val |= (cmnda_hs_clk_0_sel.value >> 1) << 12;
|
||||
Afe_write(state, 0x40E1 | (i << 9), reg_val);
|
||||
}
|
||||
|
||||
/* register TX_DIAG_TX_CTRL */
|
||||
for (i = 0; i < num_lanes; i++) {
|
||||
reg_val = Afe_read(state, 0x41E0 | (i << 9));
|
||||
reg_val &= 0xFF3F;
|
||||
reg_val |= (tx_subrate.value >> 1) << 6;
|
||||
Afe_write(state, 0x41E0 | (i << 9), reg_val);
|
||||
}
|
||||
|
||||
/* register CMN_PLLSM0_USER_DEF_CTRL */
|
||||
reg_val = set_reg_value(vco_ring_select);
|
||||
Afe_write(state, 0x002F, reg_val);
|
||||
/* register CMN_DIAG_PLL0_OVRD */
|
||||
Afe_write(state, 0x01C2, 0x0000);
|
||||
/* register CMN_DIAG_PLL0_FBH_OVRD */
|
||||
reg_val = set_reg_value(cmnda_pll0_fb_div_high);
|
||||
reg_val |= (1 << 15);
|
||||
Afe_write(state, 0x01C0, reg_val);
|
||||
/* register CMN_DIAG_PLL0_V2I_TUNE */
|
||||
reg_val = set_reg_value(voltage_to_current_coarse);
|
||||
reg_val |= set_reg_value(voltage_to_current);
|
||||
Afe_write(state, 0x01C5, reg_val);
|
||||
/* register CMN_DIAG_PLL0_PTATIS_TUNE1 */
|
||||
reg_val = set_reg_value(pmos_ctrl);
|
||||
reg_val |= set_reg_value(ndac_ctrl);
|
||||
Afe_write(state, 0x01C8, reg_val);
|
||||
/* register CMN_DIAG_PLL0_PTATIS_TUNE2 */
|
||||
reg_val = set_reg_value(ptat_ndac_ctrl);
|
||||
Afe_write(state, 0x01C9, reg_val);
|
||||
/* register CMN_DIAG_PLL0_CP_TUNE */
|
||||
reg_val = set_reg_value(charge_pump_gain);
|
||||
Afe_write(state, 0x01C6, reg_val);
|
||||
/* register CMN_DIAG_PLL0_LF_PROG */
|
||||
Afe_write(state, 0x01C7, 0x0008);
|
||||
|
||||
/* register XCVR_DIAG_PLLDRC_CTRL */
|
||||
for (i = 0; i < num_lanes; i++) {
|
||||
reg_val = Afe_read(state, 0x40E0 | (i << 9));
|
||||
reg_val &= 0xBFFF;
|
||||
Afe_write(state, 0x40E0 | (i << 9), reg_val);
|
||||
}
|
||||
|
||||
/* register PHY_PMA_CMN_CTRL1 */
|
||||
reg_val = Afe_read(state, 0xC800);
|
||||
reg_val &= 0xFF8F;
|
||||
reg_val |= 0x0030;
|
||||
Afe_write(state, 0xC800, reg_val);
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
*--------------------Back to task phy_cfg_hdp------------------------
|
||||
*--------------------------------------------------------------------*/
|
||||
|
||||
if (phy_reset_workaround) {
|
||||
/* register PHY_ISO_CMN_CTRL */
|
||||
Afe_write(state, 0xC010, 0x0001); // Deassert PHY reset */
|
||||
for (i = 0; i < num_lanes; i++) {
|
||||
/* register TX_DIAG_ACYA */
|
||||
Afe_write(state, 0x41FF | (i << 9), 0x0001);
|
||||
}
|
||||
/* register PHY_PMA_ISO_CMN_CTRL */
|
||||
Afe_write(state, 0xC810, 0x0003);
|
||||
for (i = 0; i < num_lanes; i++) {
|
||||
/* register XCVR_PSM_RCTRL */
|
||||
Afe_write(state, 0x4001 | (i << 9), 0xFEFC);
|
||||
}
|
||||
/* register PHY_PMA_ISO_CMN_CTRL */
|
||||
Afe_write(state, 0xC810, 0x0013); /* Assert cmn_macro_pwr_en */
|
||||
|
||||
/* PHY_PMA_ISO_CMN_CTRL */
|
||||
while (!(Afe_read(state, 0xC810) & (1 << 5))) ; /* wait for cmn_macro_pwr_en_ack */
|
||||
|
||||
/* PHY_PMA_CMN_CTRL1 */
|
||||
while (!(Afe_read(state, 0xC800) & (1 << 0))) ; /* wait for cmn_ready */
|
||||
} else {
|
||||
for (i = 0; i < num_lanes; i++) {
|
||||
Afe_write(state, 0x41FF | (i << 9), 0x0001);
|
||||
/* register XCVR_PSM_RCTRL */
|
||||
Afe_write(state, 0x4001 | (i << 9), 0xBEFC);
|
||||
}
|
||||
}
|
||||
for (i = 0; i < num_lanes; i++) {
|
||||
/* register TX_PSC_A0 */
|
||||
Afe_write(state, 0x4100 | (i << 9), 0x6791);
|
||||
/* register TX_PSC_A1 */
|
||||
Afe_write(state, 0x4101 | (i << 9), 0x6790);
|
||||
/* register TX_PSC_A2 */
|
||||
Afe_write(state, 0x4102 | (i << 9), 0x0090);
|
||||
/* register TX_PSC_A3 */
|
||||
Afe_write(state, 0x4103 | (i << 9), 0x0090);
|
||||
}
|
||||
|
||||
/* register PHY_HDP_MODE_CTL */
|
||||
Afe_write(state, 0xC008, 0x0004);
|
||||
return character_freq_khz;
|
||||
|
||||
}
|
||||
|
||||
int hdmi_tx_kiran_power_configuration_seq(state_struct *state, int num_lanes)
|
||||
{
|
||||
/* Configure the power state. */
|
||||
|
||||
/* PHY_DP_MODE_CTL */
|
||||
while (!(Afe_read(state, 0xC008) & (1 << 6))) ;
|
||||
|
||||
/* PHY_DP_MODE_CTL */
|
||||
Afe_write(state, 0xC008, (((0x0F << num_lanes) & 0x0F) << 12) | 0x0001);
|
||||
|
||||
/* PHY_DP_MODE_CTL */
|
||||
while (!(Afe_read(state, 0xC008) & (1 << 4))) ;
|
||||
return 0;
|
||||
}
|
||||
62
drivers/gpu/drm/imx/hdp/API_AFE_ss28fdsoi_kiran_hdmitx.h
Normal file
62
drivers/gpu/drm/imx/hdp/API_AFE_ss28fdsoi_kiran_hdmitx.h
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2016-2017 Cadence Design Systems, Inc.
|
||||
* All rights reserved worldwide.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software without
|
||||
* specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
|
||||
* INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
|
||||
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
|
||||
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
******************************************************************************
|
||||
*
|
||||
* API_AFE_ss28fdsoi_kiran_hdmitx.h
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef API_AFE_SS28FDSOI_KIRAN_HDMITX_H_
|
||||
#define API_AFE_SS28FDSOI_KIRAN_HDMITX_H_
|
||||
|
||||
#include "../../../../mxc/hdp/all.h"
|
||||
|
||||
int phy_cfg_hdp_ss28fdsoi(state_struct *state, int num_lanes,
|
||||
VIC_MODES vicMode, int bpp, VIC_PXL_ENCODING_FORMAT format);
|
||||
int hdmi_tx_kiran_power_configuration_seq(state_struct *state, int num_lanes);
|
||||
int get_table_row_match_column(const u32 *array, u32 table_rows,
|
||||
u32 table_cols, u32 start_row,
|
||||
u32 column_to_search,
|
||||
u32 value_to_search_in_column);
|
||||
int get_table_row(const u32 *array, u32 table_rows,
|
||||
u32 table_cols, u32 variable_in_range,
|
||||
u32 range_min_column, u32 range_max_column,
|
||||
u32 column_to_search, u32 column_value);
|
||||
|
||||
#endif
|
||||
11
drivers/gpu/drm/imx/hdp/Kconfig
Normal file
11
drivers/gpu/drm/imx/hdp/Kconfig
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
config DRM_IMX_HDP
|
||||
tristate "IMX8 HD Display Controller"
|
||||
select DRM_IMX
|
||||
select MX8_HDP_DP
|
||||
select DRM_KMS_HELPER
|
||||
select VIDEOMODE_HELPERS
|
||||
select DRM_GEM_CMA_HELPER
|
||||
select DRM_KMS_CMA_HELPER
|
||||
select DRM_PANEL
|
||||
help
|
||||
Choose this if you want to use DP/HDMI on i.MX8.
|
||||
5
drivers/gpu/drm/imx/hdp/Makefile
Normal file
5
drivers/gpu/drm/imx/hdp/Makefile
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
obj-$(CONFIG_DRM_IMX_HDP) += imx-hdp.o \
|
||||
imx-dp.o imx-hdmi.o \
|
||||
API_AFE_ss28fdsoi_kiran_hdmitx.o \
|
||||
ss28fdsoi_hdmitx_table.o \
|
||||
API_AFE_mcu1_dp.o
|
||||
77
drivers/gpu/drm/imx/hdp/hdmitx_firmware.h
Normal file
77
drivers/gpu/drm/imx/hdp/hdmitx_firmware.h
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2016-2017 Cadence Design Systems, Inc.
|
||||
* All rights reserved worldwide.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software without
|
||||
* specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
|
||||
* INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
|
||||
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
|
||||
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
******************************************************************************
|
||||
*
|
||||
* This file was auto-generated from dram0.data and iram0.data firmware images
|
||||
* Do not edit it manually.
|
||||
*
|
||||
******************************************************************************
|
||||
*
|
||||
* hdmitx_firmware.c
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
#include <linux/io.h>
|
||||
|
||||
static u32 const hdmitx_iram0[] = {
|
||||
0x00000000,
|
||||
};
|
||||
|
||||
static u32 const hdmitx_dram0[] = {
|
||||
0x00000000,
|
||||
};
|
||||
|
||||
u32 const *hdmitx_iram0_get_ptr(void)
|
||||
{
|
||||
return (u32 const *)hdmitx_iram0;
|
||||
}
|
||||
|
||||
u32 const *hdmitx_dram0_get_ptr(void)
|
||||
{
|
||||
return (u32 const *)hdmitx_dram0;
|
||||
}
|
||||
|
||||
size_t hdmitx_iram0_get_size(void)
|
||||
{
|
||||
return sizeof(hdmitx_iram0);
|
||||
}
|
||||
|
||||
size_t hdmitx_dram0_get_size(void)
|
||||
{
|
||||
return sizeof(hdmitx_dram0);
|
||||
}
|
||||
196
drivers/gpu/drm/imx/hdp/imx-dp.c
Normal file
196
drivers/gpu/drm/imx/hdp/imx-dp.c
Normal file
|
|
@ -0,0 +1,196 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include "mhdp_firmware.h"
|
||||
#include "imx-hdp.h"
|
||||
#include "imx-hdmi.h"
|
||||
#include "imx-dp.h"
|
||||
|
||||
void dp_fw_load(state_struct *state)
|
||||
{
|
||||
printk("loading hdmi firmware\n");
|
||||
CDN_API_LoadFirmware(state,
|
||||
(u8 *)mhdp_iram0_get_ptr(),
|
||||
mhdp_iram0_get_size(),
|
||||
(u8 *)mhdp_dram0_get_ptr(),
|
||||
mhdp_dram0_get_size());
|
||||
}
|
||||
|
||||
void dp_fw_init(state_struct *state, u32 core_rate)
|
||||
{
|
||||
u8 echo_msg[] = "echo test";
|
||||
u8 echo_resp[sizeof(echo_msg) + 1];
|
||||
int ret;
|
||||
u8 resp;
|
||||
|
||||
/* configure the clock */
|
||||
CDN_API_SetClock(state, core_rate/1000000);
|
||||
printk("CDN_API_SetClock completed\n");
|
||||
|
||||
cdn_apb_write(state, APB_CTRL << 2, 0);
|
||||
printk("Started firmware!\n");
|
||||
|
||||
ret = CDN_API_CheckAlive_blocking(state);
|
||||
printk("CDN_API_CheckAlive returned (ret = %d)\n", ret);
|
||||
|
||||
/* turn on IP activity */
|
||||
ret = CDN_API_MainControl_blocking(state, 1, &resp);
|
||||
printk("CDN_API_MainControl_blocking (ret = %d resp = %u)\n",
|
||||
ret, resp);
|
||||
|
||||
ret = CDN_API_General_Test_Echo_Ext_blocking(state, echo_msg, echo_resp,
|
||||
sizeof(echo_msg), CDN_BUS_TYPE_APB);
|
||||
printk("CDN_API_General_Test_Echo_Ext_blocking (ret = %d echo_resp = %s)\n",
|
||||
ret, echo_resp);
|
||||
|
||||
/* Line swaping */
|
||||
CDN_API_General_Write_Register_blocking(state,
|
||||
ADDR_SOURCD_PHY + (LANES_CONFIG << 2), 0x0040001b);
|
||||
printk("CDN_API_General_Write_Register_blockin ... setting LANES_CONFIG\n");
|
||||
}
|
||||
|
||||
void dp_phy_init(state_struct *state, int num_lanes, int max_link_rate, int tmp)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* PHY initialization while phy reset pin is active */
|
||||
AFE_init(state, num_lanes, (ENUM_AFE_LINK_RATE)max_link_rate);
|
||||
printk("AFE_init\n");
|
||||
|
||||
/* In this point the phy reset should be deactivated */
|
||||
hdp_phy_reset(1);
|
||||
printk("deasserted reset\n");
|
||||
|
||||
/* PHY power set */
|
||||
AFE_power(state, num_lanes, (ENUM_AFE_LINK_RATE)max_link_rate);
|
||||
printk("AFE_power exit\n");
|
||||
|
||||
/* Video off */
|
||||
ret = CDN_API_DPTX_SetVideo_blocking(state, 0);
|
||||
printk("CDN_API_DPTX_SetVideo_blocking (ret = %d)\n", ret);
|
||||
}
|
||||
|
||||
/* Max Link Rate: 06h (1.62Gbps), 0Ah (2.7Gbps), 14h (5.4Gbps), 1Eh (8.1Gbps)--N/A */
|
||||
void dp_mode_set(state_struct *state, int vic, int format, int color_depth, int max_link_rate)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Set Host capabilities */
|
||||
/* Number of lanes and SSC */
|
||||
u8 num_lanes = 4;
|
||||
u8 ssc = 0;
|
||||
u8 scrambler = 0;
|
||||
/* Max voltage swing */
|
||||
u8 max_vswing = 3;
|
||||
u8 force_max_vswing = 0;
|
||||
/* Max pre-emphasis */
|
||||
u8 max_preemph = 2;
|
||||
u8 force_max_preemph = 0;
|
||||
/* Supported test patterns mask */
|
||||
u8 supp_test_patterns = 0x0F;
|
||||
/* AUX training? */
|
||||
u8 no_aux_training = 0;
|
||||
/* Lane mapping */
|
||||
u8 lane_mapping = 0x1B; /* we have 4 lane, so it's OK */
|
||||
/* Extended Host capabilities */
|
||||
u8 ext_host_cap = 1;
|
||||
/* Bits per sub-pixel */
|
||||
u8 bits_per_subpixel = 8;
|
||||
/* Stereoscopic video */
|
||||
STEREO_VIDEO_ATTR stereo = 0;
|
||||
/* B/W Balance Type: 0 no data, 1 IT601, 2 ITU709 */
|
||||
BT_TYPE bt_type = 0;
|
||||
/* Transfer Unit */
|
||||
u8 transfer_unit = 64;
|
||||
VIC_SYMBOL_RATE sym_rate;
|
||||
|
||||
ret = CDN_API_DPTX_SetHostCap_blocking(state,
|
||||
max_link_rate,
|
||||
(num_lanes & 0x7) | ((ssc & 1) << 3) | ((scrambler & 1) << 4),
|
||||
(max_vswing & 0x3) | ((force_max_vswing & 1) << 4),
|
||||
(max_preemph & 0x3) | ((force_max_preemph & 1) << 4),
|
||||
supp_test_patterns,
|
||||
no_aux_training, //fast link training
|
||||
lane_mapping,
|
||||
ext_host_cap
|
||||
);
|
||||
printk("CDN_API_DPTX_SetHostCap_blocking (ret = %d)\n", ret);
|
||||
|
||||
switch (max_link_rate) {
|
||||
case 0x0a:
|
||||
sym_rate = RATE_2_7;
|
||||
break;
|
||||
case 0x14:
|
||||
sym_rate = RATE_5_4;
|
||||
break;
|
||||
default:
|
||||
sym_rate = RATE_1_6;
|
||||
}
|
||||
|
||||
ret = CDN_API_DPTX_Set_VIC_blocking(state,
|
||||
vic,
|
||||
bits_per_subpixel,
|
||||
num_lanes,
|
||||
sym_rate,
|
||||
format,
|
||||
stereo,
|
||||
bt_type,
|
||||
transfer_unit
|
||||
);
|
||||
printk("CDN_API_DPTX_Set_VIC_blocking (ret = %d)\n", ret);
|
||||
|
||||
ret = CDN_API_DPTX_TrainingControl_blocking(state, 1);
|
||||
printk("CDN_API_DPTX_TrainingControl_blocking (ret = %d)\n", ret);
|
||||
|
||||
/* Set video on */
|
||||
ret = CDN_API_DPTX_SetVideo_blocking(state, 1);
|
||||
printk("CDN_API_DPTX_SetVideo_blocking (ret = %d)\n", ret);
|
||||
|
||||
udelay(1000);
|
||||
}
|
||||
|
||||
int dp_get_edid_block(void *data, u8 *buf, unsigned int block, size_t len)
|
||||
{
|
||||
DPTX_Read_EDID_response edidResp;
|
||||
state_struct *state = data;
|
||||
CDN_API_STATUS ret = 0;
|
||||
|
||||
memset(&edidResp, 0, sizeof(edidResp));
|
||||
switch (block) {
|
||||
case 0:
|
||||
ret = CDN_API_DPTX_Read_EDID_blocking(state, 0, 0, &edidResp);
|
||||
break;
|
||||
case 1:
|
||||
ret = CDN_API_DPTX_Read_EDID_blocking(state, 0, 1, &edidResp);
|
||||
break;
|
||||
case 2:
|
||||
ret = CDN_API_DPTX_Read_EDID_blocking(state, 1, 0, &edidResp);
|
||||
break;
|
||||
case 3:
|
||||
ret = CDN_API_DPTX_Read_EDID_blocking(state, 1, 1, &edidResp);
|
||||
break;
|
||||
default:
|
||||
pr_warn("EDID block %x read not support\n", block);
|
||||
}
|
||||
|
||||
memcpy(buf, edidResp.buff, 128);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void dp_get_hpd_state(state_struct *state, u8 *hpd)
|
||||
{
|
||||
CDN_API_DPTX_GetHpdStatus_blocking(state, hpd);
|
||||
}
|
||||
24
drivers/gpu/drm/imx/hdp/imx-dp.h
Normal file
24
drivers/gpu/drm/imx/hdp/imx-dp.h
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#ifndef _IMX_DP_H_
|
||||
#define _IMX_DP_H_
|
||||
|
||||
void dp_fw_load(state_struct *state);
|
||||
void dp_fw_init(state_struct *state, u32 rate);
|
||||
void dp_mode_set(state_struct *state, int vic, int format, int color_depth, int max_link_rate);
|
||||
void dp_phy_init(state_struct *state, int num_lanes, int max_link_rate, int tmp);
|
||||
int dp_get_edid_block(void *data, u8 *buf, u32 block, size_t len);
|
||||
void dp_get_hpd_state(state_struct *state, u8 *hpd);
|
||||
|
||||
#endif
|
||||
148
drivers/gpu/drm/imx/hdp/imx-hdmi.c
Normal file
148
drivers/gpu/drm/imx/hdp/imx-hdmi.c
Normal file
|
|
@ -0,0 +1,148 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include "hdmitx_firmware.h"
|
||||
#include "imx-hdp.h"
|
||||
#include "imx-hdmi.h"
|
||||
#include "API_AFE_ss28fdsoi_kiran_hdmitx.h"
|
||||
|
||||
static int character_freq_khz;
|
||||
|
||||
void hdmi_fw_load(state_struct *state)
|
||||
{
|
||||
printk("loading hdmi firmware\n");
|
||||
CDN_API_LoadFirmware(state,
|
||||
(u8 *)hdmitx_iram0_get_ptr(),
|
||||
hdmitx_iram0_get_size(),
|
||||
(u8 *)hdmitx_dram0_get_ptr(),
|
||||
hdmitx_dram0_get_size());
|
||||
}
|
||||
|
||||
void hdmi_fw_init(state_struct *state, u32 core_rate)
|
||||
{
|
||||
u8 echo_msg[] = "echo test";
|
||||
u8 echo_resp[sizeof(echo_msg) + 1];
|
||||
int ret;
|
||||
u8 sts;
|
||||
|
||||
/* configure the clock */
|
||||
CDN_API_SetClock(state, core_rate/1000000);
|
||||
printk("CDN_API_SetClock completed\n");
|
||||
|
||||
/* moved from CDN_API_LoadFirmware */
|
||||
cdn_apb_write(state, APB_CTRL << 2, 0);
|
||||
printk("Started firmware!\n");
|
||||
|
||||
ret = CDN_API_CheckAlive_blocking(state);
|
||||
printk("CDN_API_CheckAlive returned ret = %d\n", ret);
|
||||
|
||||
/* turn on IP activity */
|
||||
ret = CDN_API_MainControl_blocking(state, 1, &sts);
|
||||
printk("CDN_API_MainControl_blocking ret = %d sts = %u\n", ret, sts);
|
||||
|
||||
ret = CDN_API_General_Test_Echo_Ext_blocking(state, echo_msg, echo_resp,
|
||||
sizeof(echo_msg), CDN_BUS_TYPE_APB);
|
||||
printk("CDN_API_General_Test_Echo_Ext_blocking - APB(ret = %d echo_resp = %s)\n",
|
||||
ret, echo_resp);
|
||||
}
|
||||
|
||||
void hdmi_phy_init(state_struct *state, int vic, int format, int color_depth)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Configure PHY */
|
||||
character_freq_khz = phy_cfg_hdp_ss28fdsoi(state, 4, vic, color_depth, format);
|
||||
|
||||
hdp_phy_reset(1);
|
||||
|
||||
hdmi_tx_kiran_power_configuration_seq(state, 4);
|
||||
|
||||
/* Set the lane swapping */
|
||||
ret = CDN_API_General_Write_Register_blocking(state, ADDR_SOURCD_PHY + (LANES_CONFIG << 2),
|
||||
F_SOURCE_PHY_LANE0_SWAP(3) | F_SOURCE_PHY_LANE1_SWAP(0) |
|
||||
F_SOURCE_PHY_LANE2_SWAP(1) | F_SOURCE_PHY_LANE3_SWAP(2) |
|
||||
F_SOURCE_PHY_COMB_BYPASS(0) | F_SOURCE_PHY_20_10(1));
|
||||
printk("CDN_API_General_Write_Register_blocking LANES_CONFIG ret = %d\n", ret);
|
||||
}
|
||||
|
||||
void hdmi_mode_set(state_struct *state, int vic, int format, int color_depth, int temp)
|
||||
{
|
||||
int ret;
|
||||
GENERAL_Read_Register_response regresp;
|
||||
|
||||
/* B/W Balance Type: 0 no data, 1 IT601, 2 ITU709 */
|
||||
BT_TYPE bw_type = 0;
|
||||
/* Mode = 0 - DVI, 1 - HDMI1.4, 2 HDMI 2.0 */
|
||||
HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE ptype = 1;
|
||||
|
||||
if (vic == VIC_MODE_97_60Hz)
|
||||
ptype = 2;
|
||||
|
||||
ret = CDN_API_HDMITX_Init_blocking(state);
|
||||
printk("CDN_API_STATUS CDN_API_HDMITX_Init_blocking ret = %d\n", ret);
|
||||
|
||||
/* Set HDMI TX Mode */
|
||||
ret = CDN_API_HDMITX_Set_Mode_blocking(state, ptype, character_freq_khz);
|
||||
printk("CDN_API_HDMITX_Set_Mode_blocking ret = %d\n", ret);
|
||||
|
||||
ret = CDN_API_Set_AVI(state, vic, format, bw_type);
|
||||
printk("CDN_API_Set_AVI ret = %d\n", ret);
|
||||
|
||||
ret = CDN_API_HDMITX_SetVic_blocking(state, vic, color_depth, format);
|
||||
printk("CDN_API_HDMITX_SetVic_blocking ret = %d\n", ret);
|
||||
|
||||
/* adjust the vsync/hsync polarity */
|
||||
CDN_API_General_Read_Register_blocking(
|
||||
state, ADDR_SOURCE_VIF + (HSYNC2VSYNC_POL_CTRL << 2), ®resp);
|
||||
printk("Initial HSYNC2VSYNC_POL_CTRL: 0x%x\n", regresp.val);
|
||||
if ((regresp.val & 0x6) != 0) {
|
||||
__raw_writel(0x4, state->mem.ss_base);
|
||||
}
|
||||
msleep(50);
|
||||
}
|
||||
|
||||
int hdmi_get_edid_block(void *data, u8 *buf, u32 block, size_t len)
|
||||
{
|
||||
HDMITX_TRANS_DATA edidResp;
|
||||
state_struct *state = data;
|
||||
CDN_API_STATUS ret = 0;
|
||||
|
||||
memset(&edidResp, 0, sizeof(edidResp));
|
||||
switch (block) {
|
||||
case 0:
|
||||
ret = CDN_API_HDMITX_READ_EDID_blocking(state, 0, 0, &edidResp);
|
||||
break;
|
||||
case 1:
|
||||
ret = CDN_API_HDMITX_READ_EDID_blocking(state, 0, 1, &edidResp);
|
||||
break;
|
||||
case 2:
|
||||
ret = CDN_API_HDMITX_READ_EDID_blocking(state, 1, 0, &edidResp);
|
||||
break;
|
||||
case 3:
|
||||
ret = CDN_API_HDMITX_READ_EDID_blocking(state, 1, 1, &edidResp);
|
||||
break;
|
||||
default:
|
||||
printk("EDID block %x read not support\n", block);
|
||||
}
|
||||
|
||||
memcpy(buf, edidResp.buff, 128);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void hdmi_get_hpd_state(state_struct *state, u8 *hpd)
|
||||
{
|
||||
CDN_API_HDMITX_GetHpdStatus_blocking(state, hpd);
|
||||
}
|
||||
23
drivers/gpu/drm/imx/hdp/imx-hdmi.h
Normal file
23
drivers/gpu/drm/imx/hdp/imx-hdmi.h
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#ifndef _IMX_HDMI_H_
|
||||
#define _IMX_HDMI_H_
|
||||
void hdmi_fw_load(state_struct *state);
|
||||
void hdmi_fw_init(state_struct *state, u32 rate);
|
||||
void hdmi_phy_init(state_struct *state, int vic, int format, int color_depth);
|
||||
void hdmi_mode_set(state_struct *state, int vic, int format, int color_depth, int max_link);
|
||||
int hdmi_get_edid_block(void *data, u8 *buf, u32 block, size_t len);
|
||||
void hdmi_get_hpd_state(state_struct *state, u8 *hpd);
|
||||
|
||||
#endif
|
||||
1022
drivers/gpu/drm/imx/hdp/imx-hdp.c
Normal file
1022
drivers/gpu/drm/imx/hdp/imx-hdp.c
Normal file
File diff suppressed because it is too large
Load diff
193
drivers/gpu/drm/imx/hdp/imx-hdp.h
Normal file
193
drivers/gpu/drm/imx/hdp/imx-hdp.h
Normal file
|
|
@ -0,0 +1,193 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#ifndef _IMX_HDP_H_
|
||||
#define _IMX_HDP_H_
|
||||
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <drm/drm_of.h>
|
||||
#include <drm/drmP.h>
|
||||
#include <drm/drm_atomic_helper.h>
|
||||
#include <drm/drm_crtc_helper.h>
|
||||
#include <drm/drm_edid.h>
|
||||
#include <drm/drm_encoder_slave.h>
|
||||
#include <soc/imx8/sc/sci.h>
|
||||
|
||||
#include <drm/drm_dp_helper.h>
|
||||
#include "../../../../mxc/hdp/all.h"
|
||||
|
||||
#define PLL_1188MHZ (1188000000)
|
||||
#define PLL_675MHZ (675000000)
|
||||
|
||||
#define HDP_TX_SS_LIS_BASE 0x0000
|
||||
#define HDP_TX_SS_CSR_BASE 0x1000
|
||||
#define HDP_TX_SS_GPIO_BASE 0x2000
|
||||
#define HDP_TX_SS_CTRL0_BASE 0x8000
|
||||
|
||||
#define CSR_PIXEL_LINK_MUX_CTL 0x00
|
||||
#define PL_MUX_CTL_VCP_OFFSET 5
|
||||
#define PL_MUX_CTL_HCP_OFFSET 4
|
||||
#define PL_MUX_CTL_PL_MUX_OFFSET 2
|
||||
#define PL_MUX_CTL_PL_SEL_OFFSET 0
|
||||
|
||||
#define CSR_PIXEL_LINK_MUX_STATUS 0x04
|
||||
#define PL_MUX_STATUS_PL1_INT_OFFSET 18
|
||||
#define PL_MUX_STATUS_PL1_ADD_OFFSET 16
|
||||
#define PL_MUX_STATUS_PL1_TYP_OFFSET 11
|
||||
#define PL_MUX_STATUS_PL0_INT_OFFSET 9
|
||||
#define PL_MUX_STATUS_PL0_ADD_OFFSET 7
|
||||
#define PL_MUX_STATUS_PL0_TYP_OFFSET 2
|
||||
#define PL_MUX_STATUS_PL_DLY_OFFSET 0
|
||||
|
||||
#define CSR_HDP_TX_CTRL_CTRL0 0x08
|
||||
#define CSR_HDP_TX_CTRL_CTRL1 0x0c
|
||||
|
||||
/**
|
||||
* imx_hdp_call - Calls a struct imx hdp_operations operation on
|
||||
* an entity
|
||||
*
|
||||
* @entity: entity where the @operation will be called
|
||||
* @operation: type of the operation. Should be the name of a member of
|
||||
* struct &media_entity_operations.
|
||||
*
|
||||
* This helper function will check if @operation is not %NULL. On such case,
|
||||
* it will issue a call to @operation\(@args\).
|
||||
*/
|
||||
|
||||
#define imx_hdp_call(hdp, operation, args...) \
|
||||
(!(hdp) ? -ENODEV : (((hdp)->ops && (hdp)->ops->operation) ? \
|
||||
(hdp)->ops->operation(args) : -ENOIOCTLCMD))
|
||||
|
||||
struct hdp_ops {
|
||||
void (*fw_load)(state_struct *state);
|
||||
void (*fw_init)(state_struct *state, u32 rate);
|
||||
void (*phy_init)(state_struct *state, int vic, int format, int color_depth);
|
||||
void (*mode_set)(state_struct *state, int vic, int format, int color_depth, int max_link);
|
||||
int (*get_edid_block)(void *data, u8 *buf, u32 block, size_t len);
|
||||
void (*get_hpd_state)(state_struct *state, u8 *hpd);
|
||||
};
|
||||
|
||||
struct hdp_devtype {
|
||||
u8 load_fw;
|
||||
u8 is_hdmi;
|
||||
struct hdp_ops *ops;
|
||||
struct hdp_rw_func *rw;
|
||||
};
|
||||
|
||||
struct hdp_video {
|
||||
u32 bpp;
|
||||
u32 format;
|
||||
u32 lanes;
|
||||
u32 color_type; /* bt */
|
||||
u32 color_depth; /* bpc */
|
||||
struct drm_display_mode cur_mode;
|
||||
struct drm_display_mode pre_mode;
|
||||
void __iomem *regs_base;
|
||||
};
|
||||
|
||||
struct hdp_audio {
|
||||
u32 interface; /* I2S SPDIF */
|
||||
u32 freq;
|
||||
u32 nlanes;
|
||||
u32 nChannels;
|
||||
u32 sample_width;
|
||||
u32 sample_rate;
|
||||
u32 audio_cts;
|
||||
u32 audio_n;
|
||||
bool audio_enable;
|
||||
spinlock_t audio_lock;
|
||||
struct mutex audio_mutex;
|
||||
void __iomem *regs_base;
|
||||
};
|
||||
|
||||
struct hdp_hdcp {
|
||||
void __iomem *regs_base;
|
||||
};
|
||||
|
||||
struct hdp_phy {
|
||||
u32 index;
|
||||
u32 number;
|
||||
bool enabled;
|
||||
struct phy *phy;
|
||||
void __iomem *regs_base;
|
||||
};
|
||||
|
||||
struct hdp_clks {
|
||||
struct clk *av_pll;
|
||||
struct clk *dig_pll;
|
||||
struct clk *clk_ipg;
|
||||
struct clk *clk_core;
|
||||
struct clk *clk_pxl;
|
||||
struct clk *clk_pxl_mux;
|
||||
struct clk *clk_pxl_link;
|
||||
|
||||
struct clk *clk_hdp;
|
||||
struct clk *clk_phy;
|
||||
struct clk *clk_apb;
|
||||
|
||||
struct clk *clk_lis;
|
||||
struct clk *clk_msi;
|
||||
struct clk *clk_lpcg;
|
||||
struct clk *clk_even;
|
||||
struct clk *clk_dbl;
|
||||
struct clk *clk_vif;
|
||||
struct clk *clk_apb_csr;
|
||||
struct clk *clk_apb_ctrl;
|
||||
struct clk *av_pll_div;
|
||||
struct clk *dig_pll_div;
|
||||
};
|
||||
|
||||
struct imx_hdp {
|
||||
struct device *dev;
|
||||
struct drm_connector connector;
|
||||
struct drm_encoder encoder;
|
||||
struct drm_bridge bridge;
|
||||
|
||||
struct edid *edid;
|
||||
char cable_state;
|
||||
char fw_running;
|
||||
|
||||
void __iomem *regs_base; /* Controller regs base */
|
||||
void __iomem *ss_base; /* HDP Subsystem regs base */
|
||||
|
||||
u8 load_fw;
|
||||
u8 is_hdmi;
|
||||
|
||||
struct mutex mutex; /* for state below and previous_mode */
|
||||
enum drm_connector_force force; /* mutex-protected force state */
|
||||
|
||||
struct hdp_video video;
|
||||
|
||||
struct drm_dp_aux aux;
|
||||
struct mutex aux_mutex;
|
||||
|
||||
struct drm_dp_link dp_link;
|
||||
S_LINK_STAT lkstat;
|
||||
ENUM_AFE_LINK_RATE link_rate;
|
||||
|
||||
sc_ipc_t ipcHndl;
|
||||
u32 mu_id;
|
||||
u32 dual_mode;
|
||||
struct hdp_ops *ops;
|
||||
struct hdp_rw_func *rw;
|
||||
struct hdp_clks clks;
|
||||
state_struct state;
|
||||
|
||||
};
|
||||
|
||||
int imx_hdpaux_init(struct device *dev, struct imx_hdp *dp);
|
||||
void imx_hdpaux_destroy(struct device *dev, struct imx_hdp *dp);
|
||||
void hdp_phy_reset(u8 reset);
|
||||
|
||||
#endif
|
||||
77
drivers/gpu/drm/imx/hdp/mhdp_firmware.h
Normal file
77
drivers/gpu/drm/imx/hdp/mhdp_firmware.h
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2016-2017 Cadence Design Systems, Inc.
|
||||
* All rights reserved worldwide.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software without
|
||||
* specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
|
||||
* INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
|
||||
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
|
||||
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
******************************************************************************
|
||||
*
|
||||
* This file was auto-generated from dram0.data and iram0.data firmware images
|
||||
* Do not edit it manually.
|
||||
*
|
||||
******************************************************************************
|
||||
*
|
||||
* mhdp_firmware.c
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
#include <linux/io.h>
|
||||
|
||||
static u32 const mhdp_iram0[] = {
|
||||
0x00000000,
|
||||
};
|
||||
|
||||
static u32 const mhdp_dram0[] = {
|
||||
0x00000000,
|
||||
};
|
||||
|
||||
u32 const *mhdp_iram0_get_ptr(void)
|
||||
{
|
||||
return (u32 const *)mhdp_iram0;
|
||||
}
|
||||
|
||||
u32 const *mhdp_dram0_get_ptr(void)
|
||||
{
|
||||
return (u32 const *)mhdp_dram0;
|
||||
}
|
||||
|
||||
size_t mhdp_iram0_get_size(void)
|
||||
{
|
||||
return sizeof(mhdp_iram0);
|
||||
}
|
||||
|
||||
size_t mhdp_dram0_get_size(void)
|
||||
{
|
||||
return sizeof(mhdp_dram0);
|
||||
}
|
||||
106
drivers/gpu/drm/imx/hdp/ss28fdsoi_hdmitx_table.c
Normal file
106
drivers/gpu/drm/imx/hdp/ss28fdsoi_hdmitx_table.c
Normal file
|
|
@ -0,0 +1,106 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2016-2017 Cadence Design Systems, Inc.
|
||||
* All rights reserved worldwide.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software without
|
||||
* specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
|
||||
* INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
|
||||
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
|
||||
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
******************************************************************************
|
||||
*
|
||||
* ss28fdsoi_hdmitx_table.c
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#include "ss28fdsoi_hdmitx_table.h"
|
||||
|
||||
const u32 ss28fdsoi_hdmitx_clock_control_table[SS28FDSOI_HDMITX_CLOCK_CONTROL_TABLE_ROWS][SS28FDSOI_HDMITX_CLOCK_CONTROL_TABLE_COLS] = {
|
||||
{ 25000, 42500, 1000, 250000, 425000, 0x05, 0x01, 0x01, 400, 0x182, 0x00A, 2000000, 3400000, 0, 2, 2, 2, 4, 125000, 212500, 0x03, 25000, 42500 },
|
||||
{ 42500, 85000, 1000, 425000, 850000, 0x08, 0x03, 0x01, 320, 0x132, 0x00A, 1700000, 3400000, 0, 1, 1, 2, 4, 212500, 425000, 0x02, 42500, 85000 },
|
||||
{ 85000, 170000, 1000, 850000, 1700000, 0x11, 0x00, 0x07, 340, 0x146, 0x00A, 1700000, 3400000, 0, 1, 1, 2, 2, 425000, 850000, 0x01, 85000, 170000 },
|
||||
{ 170000, 340000, 1000, 1700000, 3400000, 0x22, 0x01, 0x07, 340, 0x146, 0x00A, 1700000, 3400000, 0, 1, 1, 2, 1, 850000, 1700000, 0x00, 170000, 340000 },
|
||||
{ 340000, 600000, 1000, 3400000, 6000000, 0x3C, 0x03, 0x06, 600, 0x24A, 0x00A, 3400000, 6000000, 1, 1, 1, 2, 1, 1700000, 3000000, 0x00, 340000, 600000 },
|
||||
{ 25000, 34000, 1205, 312500, 425000, 0x04, 0x01, 0x01, 400, 0x182, 0x00A, 2500000, 3400000, 0, 2, 2, 2, 4, 156250, 212500, 0x03, 31250, 42500 },
|
||||
{ 34000, 68000, 1205, 425000, 850000, 0x06, 0x02, 0x01, 300, 0x11E, 0x00A, 1700000, 3400000, 0, 1, 1, 2, 4, 212500, 425000, 0x02, 42500, 85000 },
|
||||
{ 68000, 136000, 1205, 850000, 1700000, 0x0D, 0x02, 0x02, 325, 0x137, 0x00A, 1700000, 3400000, 0, 1, 1, 2, 2, 425000, 850000, 0x01, 85000, 170000 },
|
||||
{ 136000, 272000, 1205, 1700000, 3400000, 0x1A, 0x02, 0x04, 325, 0x137, 0x00A, 1700000, 3400000, 0, 1, 1, 2, 1, 850000, 1700000, 0x00, 170000, 340000 },
|
||||
{ 272000, 480000, 1205, 3400000, 6000000, 0x30, 0x03, 0x05, 600, 0x24A, 0x00A, 3400000, 6000000, 1, 1, 1, 2, 1, 1700000, 3000000, 0x00, 340000, 600000 },
|
||||
{ 25000, 28000, 1500, 375000, 420000, 0x03, 0x01, 0x01, 360, 0x15A, 0x00A, 3000000, 3360000, 0, 2, 2, 2, 4, 187500, 210000, 0x03, 37500, 42000 },
|
||||
{ 28000, 56000, 1500, 420000, 840000, 0x06, 0x02, 0x01, 360, 0x15A, 0x00A, 1680000, 3360000, 0, 1, 1, 2, 4, 210000, 420000, 0x02, 42000, 84000 },
|
||||
{ 56000, 113000, 1500, 840000, 1695000, 0x0B, 0x00, 0x05, 330, 0x13C, 0x00A, 1680000, 3390000, 0, 1, 1, 2, 2, 420000, 847500, 0x01, 84000, 169500 },
|
||||
{ 113000, 226000, 1500, 1695000, 3390000, 0x16, 0x01, 0x05, 330, 0x13C, 0x00A, 1695000, 3390000, 0, 1, 1, 2, 1, 847500, 1695000, 0x00, 169500, 339000 },
|
||||
{ 226000, 400000, 1500, 3390000, 6000000, 0x28, 0x03, 0x04, 600, 0x24A, 0x00A, 3390000, 6000000, 1, 1, 1, 2, 1, 1695000, 3000000, 0x00, 339000, 600000 },
|
||||
{ 25000, 42500, 2000, 500000, 850000, 0x05, 0x01, 0x01, 400, 0x182, 0x00A, 2000000, 3400000, 0, 1, 1, 2, 4, 250000, 425000, 0x02, 50000, 85000 },
|
||||
{ 42500, 85000, 2000, 850000, 1700000, 0x08, 0x03, 0x01, 320, 0x132, 0x00A, 1700000, 3400000, 0, 1, 1, 2, 2, 425000, 850000, 0x01, 85000, 170000 },
|
||||
{ 85000, 170000, 2000, 1700000, 3400000, 0x11, 0x00, 0x07, 340, 0x146, 0x00A, 1700000, 3400000, 0, 1, 1, 2, 1, 850000, 1700000, 0x00, 170000, 340000 },
|
||||
{ 170000, 300000, 2000, 3400000, 6000000, 0x22, 0x01, 0x06, 680, 0x29A, 0x00A, 3400000, 6000000, 1, 1, 1, 2, 1, 1700000, 3000000, 0x00, 340000, 600000 }
|
||||
};
|
||||
|
||||
const u32 ss28fdsoi_hdmitx_pll_tuning_table[SS28FDSOI_HDMITX_PLL_TUNING_TABLE_ROWS][SS28FDSOI_HDMITX_PLL_TUNING_TABLE_COLS] = {
|
||||
{0, 1700000, 2000000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 300.0, 0x08D},
|
||||
{0, 1700000, 2000000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 320.0, 0x08E},
|
||||
{0, 1700000, 2000000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 325.0, 0x08E},
|
||||
{0, 1700000, 2000000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 330.0, 0x08E},
|
||||
{0, 1700000, 2000000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 340.0, 0x08F},
|
||||
{0, 1700000, 2000000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 360.0, 0x0A7},
|
||||
{0, 1700000, 2000000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 400.0, 0x0C5},
|
||||
{1, 2000000, 2400000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 300.0, 0x086},
|
||||
{1, 2000000, 2400000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 320.0, 0x087},
|
||||
{1, 2000000, 2400000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 325.0, 0x087},
|
||||
{1, 2000000, 2400000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 330.0, 0x104},
|
||||
{1, 2000000, 2400000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 340.0, 0x08B},
|
||||
{1, 2000000, 2400000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 360.0, 0x08D},
|
||||
{1, 2000000, 2400000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 400.0, 0x0A6},
|
||||
{2, 2400000, 2800000, 0x3, 0x1, 0x0, 0x04, 0x0D, 300.0, 0x04E},
|
||||
{2, 2400000, 2800000, 0x3, 0x1, 0x0, 0x04, 0x0D, 320.0, 0x04F},
|
||||
{2, 2400000, 2800000, 0x3, 0x1, 0x0, 0x04, 0x0D, 325.0, 0x04F},
|
||||
{2, 2400000, 2800000, 0x3, 0x1, 0x0, 0x04, 0x0D, 330.0, 0x085},
|
||||
{2, 2400000, 2800000, 0x3, 0x1, 0x0, 0x04, 0x0D, 340.0, 0x085},
|
||||
{2, 2400000, 2800000, 0x3, 0x1, 0x0, 0x04, 0x0D, 360.0, 0x086},
|
||||
{2, 2400000, 2800000, 0x3, 0x1, 0x0, 0x04, 0x0D, 400.0, 0x08B},
|
||||
{3, 2800000, 3400000, 0x3, 0x1, 0x0, 0x04, 0x0D, 300.0, 0x047},
|
||||
{3, 2800000, 3400000, 0x3, 0x1, 0x0, 0x04, 0x0D, 320.0, 0x04B},
|
||||
{3, 2800000, 3400000, 0x3, 0x1, 0x0, 0x04, 0x0D, 325.0, 0x04B},
|
||||
{3, 2800000, 3400000, 0x3, 0x1, 0x0, 0x04, 0x0D, 330.0, 0x04B},
|
||||
{3, 2800000, 3400000, 0x3, 0x1, 0x0, 0x04, 0x0D, 340.0, 0x04D},
|
||||
{3, 2800000, 3400000, 0x3, 0x1, 0x0, 0x04, 0x0D, 360.0, 0x04E},
|
||||
{3, 2800000, 3400000, 0x3, 0x1, 0x0, 0x04, 0x0D, 400.0, 0x085},
|
||||
{4, 3400000, 3900000, 0x7, 0x1, 0x0, 0x8E, 0x2F, 600.0, 0x08D},
|
||||
{4, 3400000, 3900000, 0x7, 0x1, 0x0, 0x8E, 0x2F, 680.0, 0x0A6},
|
||||
{5, 3900000, 4500000, 0x7, 0x1, 0x0, 0x8E, 0x2F, 600.0, 0x087},
|
||||
{5, 3900000, 4500000, 0x7, 0x1, 0x0, 0x8E, 0x2F, 680.0, 0x0A4},
|
||||
{6, 4500000, 5200000, 0x7, 0x1, 0x0, 0x04, 0x0D, 600.0, 0x04F},
|
||||
{6, 4500000, 5200000, 0x7, 0x1, 0x0, 0x04, 0x0D, 680.0, 0x086},
|
||||
{7, 5200000, 6000000, 0x7, 0x1, 0x0, 0x04, 0x0D, 600.0, 0x04D},
|
||||
{7, 5200000, 6000000, 0x7, 0x1, 0x0, 0x04, 0x0D, 680.0, 0x04F}
|
||||
};
|
||||
109
drivers/gpu/drm/imx/hdp/ss28fdsoi_hdmitx_table.h
Normal file
109
drivers/gpu/drm/imx/hdp/ss28fdsoi_hdmitx_table.h
Normal file
|
|
@ -0,0 +1,109 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2016-2017 Cadence Design Systems, Inc.
|
||||
* All rights reserved worldwide.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software without
|
||||
* specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
|
||||
* INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
|
||||
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
|
||||
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
******************************************************************************
|
||||
*
|
||||
* ss28fdsoi_hdmitx_table.h
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef SS28FDSOI_HDMITX_TABLE_H_
|
||||
#define SS28FDSOI_HDMITX_TABLE_H_
|
||||
|
||||
#include <linux/io.h>
|
||||
|
||||
# define SS28FDSOI_HDMITX_CLOCK_CONTROL_TABLE_ROWS 19
|
||||
# define SS28FDSOI_HDMITX_CLOCK_CONTROL_TABLE_COLS 23
|
||||
|
||||
# define SS28FDSOI_HDMITX_PLL_TUNING_TABLE_ROWS 36
|
||||
# define SS28FDSOI_HDMITX_PLL_TUNING_TABLE_COLS 19
|
||||
|
||||
typedef enum {
|
||||
//PIXEL_CLK_FREQ_MHZ_MIN,
|
||||
PIXEL_CLK_FREQ_KHZ_MIN,
|
||||
//PIXEL_CLK_FREQ_MHZ_MAX,
|
||||
PIXEL_CLK_FREQ_KHZ_MAX,
|
||||
FEEDBACK_FACTOR,
|
||||
DATA_RANGE_MBPS_MIN,
|
||||
DATA_RANGE_MBPS_MAX,
|
||||
CMNDA_PLL0_IP_DIV,
|
||||
CMN_REF_CLK_DIG_DIV,
|
||||
REF_CLK_DIVIDER_SCALER,
|
||||
PLL_FB_DIV_TOTAL,
|
||||
CMNDA_PLL0_FB_DIV_LOW,
|
||||
CMNDA_PLL0_FB_DIV_HIGH,
|
||||
//VCO_FREQ_MHZ_MIN,
|
||||
//VCO_FREQ_MHZ_MAX,
|
||||
VCO_FREQ_KHZ_MIN,
|
||||
VCO_FREQ_KHZ_MAX,
|
||||
VCO_RING_SELECT,
|
||||
CMNDA_HS_CLK_0_SEL,
|
||||
CMNDA_HS_CLK_1_SEL,
|
||||
HSCLK_DIV_AT_XCVR,
|
||||
HSCLK_DIV_TX_SUB_RATE,
|
||||
TX_CLK_KHZ_MIN,
|
||||
TX_CLK_KHZ_MAX,
|
||||
CMNDA_PLL0_HS_SYM_DIV_SEL,
|
||||
CMNDA_PLL0_CLK_FREQ_KHZ_MIN,
|
||||
CMNDA_PLL0_CLK_FREQ_KHZ_MAX
|
||||
} CLK_CTRL_PARAM;
|
||||
|
||||
typedef enum {
|
||||
VCO_FREQ_BIN,
|
||||
/* PLL_VCO_FREQ_MHZ_MIN, */
|
||||
/* PLL_VCO_FREQ_MHZ_MAX, */
|
||||
PLL_VCO_FREQ_KHZ_MIN,
|
||||
PLL_VCO_FREQ_KHZ_MAX,
|
||||
VOLTAGE_TO_CURRENT_COARSE,
|
||||
VOLTAGE_TO_CURRENT,
|
||||
NDAC_CTRL,
|
||||
PMOS_CTRL,
|
||||
PTAT_NDAC_CTRL,
|
||||
/*PLL_FEEDBACK_DIV_TOTAL, float to int */
|
||||
PLL_FEEDBACK_DIV_TOTAL,
|
||||
CHARGE_PUMP_GAIN
|
||||
} PLL_TUNE_PARAM;
|
||||
|
||||
extern const u32
|
||||
ss28fdsoi_hdmitx_clock_control_table[SS28FDSOI_HDMITX_CLOCK_CONTROL_TABLE_ROWS]
|
||||
[SS28FDSOI_HDMITX_CLOCK_CONTROL_TABLE_COLS];
|
||||
extern const u32
|
||||
ss28fdsoi_hdmitx_pll_tuning_table[SS28FDSOI_HDMITX_PLL_TUNING_TABLE_ROWS]
|
||||
[SS28FDSOI_HDMITX_PLL_TUNING_TABLE_COLS];
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue