perf events: Enable raw event support for Intel unhalted_reference_cycles event
This patch adds the encoding and definitions necessary for the unhalted_reference_cycles event avaialble since Intel Core 2 processors. Signed-off-by: Stephane Eranian <eranian@google.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/1323559734-3488-2-git-send-email-eranian@google.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -112,23 +112,24 @@ struct x86_pmu_capability {
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/*
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* All 3 fixed-mode PMCs are configured via this single MSR:
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*/
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#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
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#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
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/*
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* The counts are available in three separate MSRs:
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*/
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/* Instr_Retired.Any: */
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#define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
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#define X86_PMC_IDX_FIXED_INSTRUCTIONS (X86_PMC_IDX_FIXED + 0)
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#define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
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#define X86_PMC_IDX_FIXED_INSTRUCTIONS (X86_PMC_IDX_FIXED + 0)
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/* CPU_CLK_Unhalted.Core: */
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#define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
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#define X86_PMC_IDX_FIXED_CPU_CYCLES (X86_PMC_IDX_FIXED + 1)
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#define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
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#define X86_PMC_IDX_FIXED_CPU_CYCLES (X86_PMC_IDX_FIXED + 1)
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/* CPU_CLK_Unhalted.Ref: */
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#define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
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#define X86_PMC_IDX_FIXED_BUS_CYCLES (X86_PMC_IDX_FIXED + 2)
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#define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
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#define X86_PMC_IDX_FIXED_REF_CYCLES (X86_PMC_IDX_FIXED + 2)
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#define X86_PMC_MSK_FIXED_REF_CYCLES (1ULL << X86_PMC_IDX_FIXED_REF_CYCLES)
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/*
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* We model BTS tracing as another fixed-mode PMC.
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@ -1304,9 +1304,15 @@ static int __init init_hw_perf_events(void)
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0, x86_pmu.num_counters, 0);
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if (x86_pmu.event_constraints) {
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/*
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* event on fixed counter2 (REF_CYCLES) only works on this
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* counter, so do not extend mask to generic counters
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*/
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for_each_event_constraint(c, x86_pmu.event_constraints) {
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if (c->cmask != X86_RAW_EVENT_MASK)
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if (c->cmask != X86_RAW_EVENT_MASK
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|| c->idxmsk64 == X86_PMC_MSK_FIXED_REF_CYCLES) {
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continue;
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}
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c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
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c->weight += x86_pmu.num_counters;
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@ -45,12 +45,7 @@ static struct event_constraint intel_core2_event_constraints[] __read_mostly =
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{
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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/*
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* Core2 has Fixed Counter 2 listed as CPU_CLK_UNHALTED.REF and event
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* 0x013c as CPU_CLK_UNHALTED.BUS and specifies there is a fixed
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* ratio between these counters.
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*/
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/* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
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FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
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INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
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INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
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INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
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@ -68,7 +63,7 @@ static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
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{
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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/* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
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FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
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INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
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INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
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INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
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@ -90,7 +85,7 @@ static struct event_constraint intel_westmere_event_constraints[] __read_mostly
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{
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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/* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
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FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
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INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
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INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
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INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
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@ -102,7 +97,7 @@ static struct event_constraint intel_snb_event_constraints[] __read_mostly =
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{
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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/* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
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FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
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INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
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INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
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INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
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@ -125,7 +120,7 @@ static struct event_constraint intel_gen_event_constraints[] __read_mostly =
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{
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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/* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
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FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
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EVENT_CONSTRAINT_END
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};
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