powerpc/powernv: Add iommu DMA bypass support for IODA2
This patch adds the support for to create a direct iommu "bypass" window on IODA2 bridges (such as Power8) allowing to bypass iommu page translation completely for 64-bit DMA capable devices, thus significantly improving DMA performances. Additionally, this adds a hook to the struct iommu_table so that the IOMMU API / VFIO can disable the bypass when external ownership is requested, since in that case, the device will be used by an environment such as userspace or a KVM guest which must not be allowed to bypass translations. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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@ -134,6 +134,7 @@ static inline int dma_supported(struct device *dev, u64 mask)
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}
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extern int dma_set_mask(struct device *dev, u64 dma_mask);
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extern int __dma_set_mask(struct device *dev, u64 dma_mask);
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#define dma_alloc_coherent(d,s,h,f) dma_alloc_attrs(d,s,h,f,NULL)
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@ -77,6 +77,7 @@ struct iommu_table {
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#ifdef CONFIG_IOMMU_API
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struct iommu_group *it_group;
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#endif
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void (*set_bypass)(struct iommu_table *tbl, bool enable);
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};
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/* Pure 2^n version of get_order */
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@ -191,12 +191,10 @@ EXPORT_SYMBOL(dma_direct_ops);
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#define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16)
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int dma_set_mask(struct device *dev, u64 dma_mask)
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int __dma_set_mask(struct device *dev, u64 dma_mask)
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{
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struct dma_map_ops *dma_ops = get_dma_ops(dev);
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if (ppc_md.dma_set_mask)
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return ppc_md.dma_set_mask(dev, dma_mask);
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if ((dma_ops != NULL) && (dma_ops->set_dma_mask != NULL))
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return dma_ops->set_dma_mask(dev, dma_mask);
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if (!dev->dma_mask || !dma_supported(dev, dma_mask))
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@ -204,6 +202,12 @@ int dma_set_mask(struct device *dev, u64 dma_mask)
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*dev->dma_mask = dma_mask;
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return 0;
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}
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int dma_set_mask(struct device *dev, u64 dma_mask)
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{
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if (ppc_md.dma_set_mask)
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return ppc_md.dma_set_mask(dev, dma_mask);
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return __dma_set_mask(dev, dma_mask);
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}
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EXPORT_SYMBOL(dma_set_mask);
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u64 dma_get_required_mask(struct device *dev)
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@ -1088,6 +1088,14 @@ int iommu_take_ownership(struct iommu_table *tbl)
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memset(tbl->it_map, 0xff, sz);
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iommu_clear_tces_and_put_pages(tbl, tbl->it_offset, tbl->it_size);
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/*
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* Disable iommu bypass, otherwise the user can DMA to all of
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* our physical memory via the bypass window instead of just
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* the pages that has been explicitly mapped into the iommu
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*/
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if (tbl->set_bypass)
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tbl->set_bypass(tbl, false);
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return 0;
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}
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EXPORT_SYMBOL_GPL(iommu_take_ownership);
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@ -1102,6 +1110,10 @@ void iommu_release_ownership(struct iommu_table *tbl)
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/* Restore bit#0 set by iommu_init_table() */
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if (tbl->it_offset == 0)
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set_bit(0, tbl->it_map);
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/* The kernel owns the device now, we can restore the iommu bypass */
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if (tbl->set_bypass)
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tbl->set_bypass(tbl, true);
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}
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EXPORT_SYMBOL_GPL(iommu_release_ownership);
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@ -21,6 +21,7 @@
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/msi.h>
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#include <linux/memblock.h>
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#include <asm/sections.h>
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#include <asm/io.h>
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@ -460,9 +461,39 @@ static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev
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return;
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pe = &phb->ioda.pe_array[pdn->pe_number];
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WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
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set_iommu_table_base_and_group(&pdev->dev, &pe->tce32_table);
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}
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static int pnv_pci_ioda_dma_set_mask(struct pnv_phb *phb,
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struct pci_dev *pdev, u64 dma_mask)
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{
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struct pci_dn *pdn = pci_get_pdn(pdev);
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struct pnv_ioda_pe *pe;
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uint64_t top;
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bool bypass = false;
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if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
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return -ENODEV;;
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pe = &phb->ioda.pe_array[pdn->pe_number];
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if (pe->tce_bypass_enabled) {
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top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
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bypass = (dma_mask >= top);
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}
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if (bypass) {
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dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
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set_dma_ops(&pdev->dev, &dma_direct_ops);
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set_dma_offset(&pdev->dev, pe->tce_bypass_base);
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} else {
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dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
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set_dma_ops(&pdev->dev, &dma_iommu_ops);
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set_iommu_table_base(&pdev->dev, &pe->tce32_table);
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}
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return 0;
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}
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static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
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{
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struct pci_dev *dev;
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@ -657,6 +688,56 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
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__free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs));
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}
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static void pnv_pci_ioda2_set_bypass(struct iommu_table *tbl, bool enable)
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{
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struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe,
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tce32_table);
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uint16_t window_id = (pe->pe_number << 1 ) + 1;
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int64_t rc;
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pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
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if (enable) {
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phys_addr_t top = memblock_end_of_DRAM();
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top = roundup_pow_of_two(top);
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rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
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pe->pe_number,
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window_id,
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pe->tce_bypass_base,
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top);
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} else {
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rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
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pe->pe_number,
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window_id,
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pe->tce_bypass_base,
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0);
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/*
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* We might want to reset the DMA ops of all devices on
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* this PE. However in theory, that shouldn't be necessary
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* as this is used for VFIO/KVM pass-through and the device
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* hasn't yet been returned to its kernel driver
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*/
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}
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if (rc)
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pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
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else
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pe->tce_bypass_enabled = enable;
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}
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static void pnv_pci_ioda2_setup_bypass_pe(struct pnv_phb *phb,
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struct pnv_ioda_pe *pe)
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{
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/* TVE #1 is selected by PCI address bit 59 */
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pe->tce_bypass_base = 1ull << 59;
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/* Install set_bypass callback for VFIO */
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pe->tce32_table.set_bypass = pnv_pci_ioda2_set_bypass;
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/* Enable bypass by default */
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pnv_pci_ioda2_set_bypass(&pe->tce32_table, true);
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}
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static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
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struct pnv_ioda_pe *pe)
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{
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@ -727,6 +808,8 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
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else
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pnv_ioda_setup_bus_dma(pe, pe->pbus);
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/* Also create a bypass window */
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pnv_pci_ioda2_setup_bypass_pe(phb, pe);
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return;
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fail:
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if (pe->tce32_seg >= 0)
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@ -1286,6 +1369,7 @@ void __init pnv_pci_init_ioda_phb(struct device_node *np,
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/* Setup TCEs */
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phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
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phb->dma_set_mask = pnv_pci_ioda_dma_set_mask;
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/* Setup shutdown function for kexec */
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phb->shutdown = pnv_pci_ioda_shutdown;
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@ -634,6 +634,16 @@ static void pnv_pci_dma_dev_setup(struct pci_dev *pdev)
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pnv_pci_dma_fallback_setup(hose, pdev);
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}
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int pnv_pci_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
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{
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struct pci_controller *hose = pci_bus_to_host(pdev->bus);
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struct pnv_phb *phb = hose->private_data;
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if (phb && phb->dma_set_mask)
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return phb->dma_set_mask(phb, pdev, dma_mask);
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return __dma_set_mask(&pdev->dev, dma_mask);
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}
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void pnv_pci_shutdown(void)
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{
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struct pci_controller *hose;
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@ -54,7 +54,9 @@ struct pnv_ioda_pe {
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struct iommu_table tce32_table;
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phys_addr_t tce_inval_reg_phys;
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/* XXX TODO: Add support for additional 64-bit iommus */
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/* 64-bit TCE bypass region */
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bool tce_bypass_enabled;
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uint64_t tce_bypass_base;
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/* MSIs. MVE index is identical for for 32 and 64 bit MSI
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* and -1 if not supported. (It's actually identical to the
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unsigned int hwirq, unsigned int virq,
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unsigned int is_64, struct msi_msg *msg);
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void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
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int (*dma_set_mask)(struct pnv_phb *phb, struct pci_dev *pdev,
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u64 dma_mask);
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void (*fixup_phb)(struct pci_controller *hose);
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u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
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void (*shutdown)(struct pnv_phb *phb);
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@ -7,12 +7,20 @@ extern void pnv_smp_init(void);
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static inline void pnv_smp_init(void) { }
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#endif
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struct pci_dev;
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#ifdef CONFIG_PCI
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extern void pnv_pci_init(void);
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extern void pnv_pci_shutdown(void);
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extern int pnv_pci_dma_set_mask(struct pci_dev *pdev, u64 dma_mask);
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#else
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static inline void pnv_pci_init(void) { }
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static inline void pnv_pci_shutdown(void) { }
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static inline int pnv_pci_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
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{
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return -ENODEV;
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}
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#endif
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extern void pnv_lpc_init(void);
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@ -27,6 +27,7 @@
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#include <linux/interrupt.h>
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#include <linux/bug.h>
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#include <linux/cpuidle.h>
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#include <linux/pci.h>
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#include <asm/machdep.h>
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#include <asm/firmware.h>
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@ -141,6 +142,13 @@ static void pnv_progress(char *s, unsigned short hex)
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{
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}
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static int pnv_dma_set_mask(struct device *dev, u64 dma_mask)
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{
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if (dev_is_pci(dev))
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return pnv_pci_dma_set_mask(to_pci_dev(dev), dma_mask);
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return __dma_set_mask(dev, dma_mask);
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}
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static void pnv_shutdown(void)
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{
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/* Let the PCI code clear up IODA tables */
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@ -238,6 +246,7 @@ define_machine(powernv) {
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.machine_shutdown = pnv_shutdown,
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.power_save = powernv_idle,
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.calibrate_decr = generic_calibrate_decr,
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.dma_set_mask = pnv_dma_set_mask,
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#ifdef CONFIG_KEXEC
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.kexec_cpu_down = pnv_kexec_cpu_down,
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#endif
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