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MLK-18955-2: ASoC: fsl_spdif: fix sysclk_df type 

According to SPDIF spec STC SYSCLK_DF field is 9 bits width, values
being in 0..511 range. So use a proper type to handle sysclk_df.

Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit bb7d180782208d5546a6ff6f89fb55180c1ba721)
pull/10/head
Viorel Suman 2018-07-18 11:04:11 +03:00 committed by Jason Liu
parent abbb423d25
commit cd33c7c041
1 changed files with 6 additions and 5 deletions
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11
sound/soc/fsl/fsl_spdif.c
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@ -114,7 +114,7 @@ struct fsl_spdif_priv {
bool dpll_locked;
u32 txrate[SPDIF_TXRATE_MAX];
u8 txclk_df[SPDIF_TXRATE_MAX];
u8 sysclk_df[SPDIF_TXRATE_MAX];
u16 sysclk_df[SPDIF_TXRATE_MAX];
u8 txclk_src[SPDIF_TXRATE_MAX];
u8 rxclk_src;
struct clk *txclk[SPDIF_TXRATE_MAX];
@ -456,7 +456,8 @@ static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
struct platform_device *pdev = spdif_priv->pdev;
unsigned long csfs = 0;
u32 stc, mask, rate;
u8 clk, txclk_df, sysclk_df;
u8 clk, txclk_df;
u16 sysclk_df;
switch (sample_rate) {
case 32000:
@ -1215,9 +1216,9 @@ static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
{
const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 };
bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk);
u64 rate_actual, sub;
u32 sysclk_dfmin, sysclk_dfmax;
u32 txclk_df, sysclk_df, arate;
u64 rate_actual, sub, arate;
u16 sysclk_dfmin, sysclk_dfmax, sysclk_df;
u8 txclk_df;
/* The sysclk has an extra divisor [2, 512] */
sysclk_dfmin = is_sysclk ? 2 : 1;