MLK-18205-2 dt-bindings: clock: add i.MX8MM clock header
Add i.MX8MM clock definition. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com> Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>pull/10/head
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/*
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* Copyright 2017-2018 NXP
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX8MM_H
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#define __DT_BINDINGS_CLOCK_IMX8MM_H
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#define IMX8MM_CLK_DUMMY 0
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#define IMX8MM_CLK_32K 1
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#define IMX8MM_CLK_24M 2
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#define IMX8MM_OSC_HDMI_CLK 3
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#define IMX8MM_CLK_EXT1 4
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#define IMX8MM_CLK_EXT2 5
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#define IMX8MM_CLK_EXT3 6
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#define IMX8MM_CLK_EXT4 7
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#define IMX8MM_AUDIO_PLL1_REF_SEL 8
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#define IMX8MM_AUDIO_PLL2_REF_SEL 9
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#define IMX8MM_VIDEO_PLL1_REF_SEL 10
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#define IMX8MM_DRAM_PLL_REF_SEL 11
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#define IMX8MM_GPU_PLL_REF_SEL 12
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#define IMX8MM_VPU_PLL_REF_SEL 13
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#define IMX8MM_ARM_PLL_REF_SEL 14
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#define IMX8MM_SYS_PLL1_REF_SEL 15
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#define IMX8MM_SYS_PLL2_REF_SEL 16
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#define IMX8MM_SYS_PLL3_REF_SEL 17
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#define IMX8MM_AUDIO_PLL1 18
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#define IMX8MM_AUDIO_PLL2 19
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#define IMX8MM_VIDEO_PLL1 20
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#define IMX8MM_DRAM_PLL 21
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#define IMX8MM_GPU_PLL 22
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#define IMX8MM_VPU_PLL 23
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#define IMX8MM_ARM_PLL 24
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#define IMX8MM_SYS_PLL1 25
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#define IMX8MM_SYS_PLL2 26
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#define IMX8MM_SYS_PLL3 27
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#define IMX8MM_AUDIO_PLL1_BYPASS 28
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#define IMX8MM_AUDIO_PLL2_BYPASS 29
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#define IMX8MM_VIDEO_PLL1_BYPASS 30
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#define IMX8MM_DRAM_PLL_BYPASS 31
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#define IMX8MM_GPU_PLL_BYPASS 32
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#define IMX8MM_VPU_PLL_BYPASS 33
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#define IMX8MM_ARM_PLL_BYPASS 34
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#define IMX8MM_SYS_PLL1_BYPASS 35
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#define IMX8MM_SYS_PLL2_BYPASS 36
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#define IMX8MM_SYS_PLL3_BYPASS 37
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#define IMX8MM_AUDIO_PLL1_OUT 38
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#define IMX8MM_AUDIO_PLL2_OUT 39
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#define IMX8MM_VIDEO_PLL1_OUT 40
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#define IMX8MM_DRAM_PLL_OUT 41
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#define IMX8MM_GPU_PLL_OUT 42
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#define IMX8MM_VPU_PLL_OUT 43
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#define IMX8MM_ARM_PLL_OUT 44
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#define IMX8MM_SYS_PLL1_OUT 45
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#define IMX8MM_SYS_PLL2_OUT 46
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#define IMX8MM_SYS_PLL3_OUT 47
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#define IMX8MM_SYS_PLL1_40M 48
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#define IMX8MM_SYS_PLL1_80M 49
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#define IMX8MM_SYS_PLL1_100M 50
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#define IMX8MM_SYS_PLL1_133M 51
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#define IMX8MM_SYS_PLL1_160M 52
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#define IMX8MM_SYS_PLL1_200M 53
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#define IMX8MM_SYS_PLL1_266M 54
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#define IMX8MM_SYS_PLL1_400M 55
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#define IMX8MM_SYS_PLL1_800M 56
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#define IMX8MM_SYS_PLL2_50M 57
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#define IMX8MM_SYS_PLL2_100M 58
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#define IMX8MM_SYS_PLL2_125M 59
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#define IMX8MM_SYS_PLL2_166M 60
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#define IMX8MM_SYS_PLL2_200M 61
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#define IMX8MM_SYS_PLL2_250M 62
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#define IMX8MM_SYS_PLL2_333M 63
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#define IMX8MM_SYS_PLL2_500M 64
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#define IMX8MM_SYS_PLL2_1000M 65
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#define IMX8MM_CLK_A53_SRC 66
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#define IMX8MM_CLK_M4_SRC 67
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#define IMX8MM_CLK_VPU_SRC 68
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#define IMX8MM_CLK_GPU3D_SRC 69
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#define IMX8MM_CLK_GPU2D_SRC 70
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#define IMX8MM_CLK_A53_CG 71
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#define IMX8MM_CLK_M4_CG 72
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#define IMX8MM_CLK_VPU_CG 73
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#define IMX8MM_CLK_GPU3D_CG 74
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#define IMX8MM_CLK_GPU2D_CG 75
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#define IMX8MM_CLK_A53_DIV 76
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#define IMX8MM_CLK_M4_DIV 77
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#define IMX8MM_CLK_VPU_DIV 78
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#define IMX8MM_CLK_GPU3D_DIV 79
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#define IMX8MM_CLK_GPU2D_DIV 80
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#define IMX8MM_CLK_MAIN_AXI_SRC 81
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#define IMX8MM_CLK_ENET_AXI_SRC 82
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#define IMX8MM_CLK_NAND_USDHC_BUS_SRC 83
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#define IMX8MM_CLK_VPU_BUS_SRC 84
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#define IMX8MM_CLK_DISP_AXI_SRC 85
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#define IMX8MM_CLK_DISP_APB_SRC 86
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#define IMX8MM_CLK_DISP_RTRM_SRC 87
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#define IMX8MM_CLK_USB_BUS_SRC 88
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#define IMX8MM_CLK_GPU_AXI_SRC 89
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#define IMX8MM_CLK_GPU_AHB_SRC 90
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#define IMX8MM_CLK_NOC_SRC 91
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#define IMX8MM_CLK_NOC_APB_SRC 92
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#define IMX8MM_CLK_MAIN_AXI_CG 93
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#define IMX8MM_CLK_ENET_AXI_CG 94
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#define IMX8MM_CLK_NAND_USDHC_BUS_CG 95
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#define IMX8MM_CLK_VPU_BUS_CG 96
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#define IMX8MM_CLK_DISP_AXI_CG 97
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#define IMX8MM_CLK_DISP_APB_CG 98
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#define IMX8MM_CLK_DISP_RTRM_CG 99
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#define IMX8MM_CLK_USB_BUS_CG 100
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#define IMX8MM_CLK_GPU_AXI_CG 101
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#define IMX8MM_CLK_GPU_AHB_CG 102
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#define IMX8MM_CLK_NOC_CG 103
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#define IMX8MM_CLK_NOC_APB_CG 104
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#define IMX8MM_CLK_MAIN_AXI_PRE_DIV 105
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#define IMX8MM_CLK_ENET_AXI_PRE_DIV 106
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#define IMX8MM_CLK_NAND_USDHC_BUS_PRE_DIV 107
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#define IMX8MM_CLK_VPU_BUS_PRE_DIV 108
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#define IMX8MM_CLK_DISP_AXI_PRE_DIV 109
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#define IMX8MM_CLK_DISP_APB_PRE_DIV 110
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#define IMX8MM_CLK_DISP_RTRM_PRE_DIV 111
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#define IMX8MM_CLK_USB_BUS_PRE_DIV 112
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#define IMX8MM_CLK_GPU_AXI_PRE_DIV 113
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#define IMX8MM_CLK_GPU_AHB_PRE_DIV 114
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#define IMX8MM_CLK_NOC_PRE_DIV 115
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#define IMX8MM_CLK_NOC_APB_PRE_DIV 116
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#define IMX8MM_CLK_MAIN_AXI_DIV 117
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#define IMX8MM_CLK_ENET_AXI_DIV 118
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#define IMX8MM_CLK_NAND_USDHC_BUS_DIV 119
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#define IMX8MM_CLK_VPU_BUS_DIV 120
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#define IMX8MM_CLK_DISP_AXI_DIV 121
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#define IMX8MM_CLK_DISP_APB_DIV 122
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#define IMX8MM_CLK_DISP_RTRM_DIV 123
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#define IMX8MM_CLK_USB_BUS_DIV 124
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#define IMX8MM_CLK_GPU_AXI_DIV 125
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#define IMX8MM_CLK_GPU_AHB_DIV 126
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#define IMX8MM_CLK_NOC_DIV 127
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#define IMX8MM_CLK_NOC_APB_DIV 128
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#define IMX8MM_CLK_AHB_SRC 129
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#define IMX8MM_CLK_AUDIO_AHB_SRC 130
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#define IMX8MM_CLK_DSI_ESC_RX_SRC 131
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#define IMX8MM_CLK_AHB_CG 132
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#define IMX8MM_CLK_AUDIO_AHB_CG 133
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#define IMX8MM_CLK_DSI_ESC_RX_CG 134
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#define IMX8MM_CLK_AHB_PRE_DIV 135
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#define IMX8MM_CLK_AUDIO_AHB_PRE_DIV 136
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#define IMX8MM_CLK_DSI_ESC_RX_PRE_DIV 137
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#define IMX8MM_CLK_AHB_DIV 138
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#define IMX8MM_CLK_AUDIO_AHB_DIV 139
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#define IMX8MM_CLK_DSI_ESC_RX_DIV 140
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#define IMX8MM_CLK_IPG_ROOT 141
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#define IMX8MM_CLK_IPG_AUDIO_ROOT 142
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#define IMX8MM_CLK_IPG_DSI_ESC_RX_ROOT 143
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#define IMX8MM_CLK_DRAM_ALT_SRC 144
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#define IMX8MM_CLK_DRAM_APB_SRC 145
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#define IMX8MM_CLK_VPU_G1_SRC 146
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#define IMX8MM_CLK_VPU_G2_SRC 147
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#define IMX8MM_CLK_DISP_DTRC_SRC 148
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#define IMX8MM_CLK_DISP_DC8000_SRC 149
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#define IMX8MM_CLK_PCIE1_CTRL_SRC 150
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#define IMX8MM_CLK_PCIE1_PHY_SRC 151
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#define IMX8MM_CLK_PCIE1_AUX_SRC 152
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#define IMX8MM_CLK_DC_PIXEL_SRC 153
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#define IMX8MM_CLK_LCDIF_PIXEL_SRC 154
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#define IMX8MM_CLK_SAI1_SRC 155
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#define IMX8MM_CLK_SAI2_SRC 156
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#define IMX8MM_CLK_SAI3_SRC 157
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#define IMX8MM_CLK_SAI4_SRC 158
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#define IMX8MM_CLK_SAI5_SRC 159
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#define IMX8MM_CLK_SAI6_SRC 160
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#define IMX8MM_CLK_SPDIF1_SRC 161
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#define IMX8MM_CLK_SPDIF2_SRC 162
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#define IMX8MM_CLK_ENET_REF_SRC 163
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#define IMX8MM_CLK_ENET_TIMER_SRC 164
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#define IMX8MM_CLK_ENET_PHY_REF_SRC 165
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#define IMX8MM_CLK_NAND_SRC 166
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#define IMX8MM_CLK_QSPI_SRC 167
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#define IMX8MM_CLK_USDHC1_SRC 168
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#define IMX8MM_CLK_USDHC2_SRC 169
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#define IMX8MM_CLK_I2C1_SRC 170
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#define IMX8MM_CLK_I2C2_SRC 171
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#define IMX8MM_CLK_I2C3_SRC 172
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#define IMX8MM_CLK_I2C4_SRC 173
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#define IMX8MM_CLK_UART1_SRC 174
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#define IMX8MM_CLK_UART2_SRC 175
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#define IMX8MM_CLK_UART3_SRC 176
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#define IMX8MM_CLK_UART4_SRC 177
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#define IMX8MM_CLK_USB_CORE_REF_SRC 178
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#define IMX8MM_CLK_USB_PHY_REF_SRC 179
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#define IMX8MM_CLK_ECSPI1_SRC 180
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#define IMX8MM_CLK_ECSPI2_SRC 181
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#define IMX8MM_CLK_PWM1_SRC 182
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#define IMX8MM_CLK_PWM2_SRC 183
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#define IMX8MM_CLK_PWM3_SRC 184
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#define IMX8MM_CLK_PWM4_SRC 185
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#define IMX8MM_CLK_GPT1_SRC 186
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#define IMX8MM_CLK_WDOG_SRC 187
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#define IMX8MM_CLK_WRCLK_SRC 188
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#define IMX8MM_CLK_DSI_CORE_SRC 189
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#define IMX8MM_CLK_DSI_PHY_REF_SRC 190
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#define IMX8MM_CLK_DSI_DBI_SRC 191
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#define IMX8MM_CLK_USDHC3_SRC 192
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#define IMX8MM_CLK_CSI1_CORE_SRC 193
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#define IMX8MM_CLK_CSI1_PHY_REF_SRC 194
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#define IMX8MM_CLK_CSI1_ESC_SRC 195
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#define IMX8MM_CLK_CSI2_CORE_SRC 196
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#define IMX8MM_CLK_CSI2_PHY_REF_SRC 197
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#define IMX8MM_CLK_CSI2_ESC_SRC 198
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#define IMX8MM_CLK_PCIE2_CTRL_SRC 199
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#define IMX8MM_CLK_PCIE2_PHY_SRC 200
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#define IMX8MM_CLK_PCIE2_AUX_SRC 201
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#define IMX8MM_CLK_ECSPI3_SRC 202
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#define IMX8MM_CLK_PDM_SRC 203
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#define IMX8MM_CLK_VPU_H1_SRC 204
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#define IMX8MM_CLK_DRAM_ALT_CG 205
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#define IMX8MM_CLK_DRAM_APB_CG 206
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#define IMX8MM_CLK_VPU_G1_CG 207
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#define IMX8MM_CLK_VPU_G2_CG 208
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#define IMX8MM_CLK_DISP_DTRC_CG 209
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#define IMX8MM_CLK_DISP_DC8000_CG 210
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#define IMX8MM_CLK_PCIE1_CTRL_CG 211
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#define IMX8MM_CLK_PCIE1_PHY_CG 212
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#define IMX8MM_CLK_PCIE1_AUX_CG 213
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#define IMX8MM_CLK_DC_PIXEL_CG 214
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#define IMX8MM_CLK_LCDIF_PIXEL_CG 215
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#define IMX8MM_CLK_SAI1_CG 216
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#define IMX8MM_CLK_SAI2_CG 217
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#define IMX8MM_CLK_SAI3_CG 218
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#define IMX8MM_CLK_SAI4_CG 219
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#define IMX8MM_CLK_SAI5_CG 220
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#define IMX8MM_CLK_SAI6_CG 221
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#define IMX8MM_CLK_SPDIF1_CG 222
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#define IMX8MM_CLK_SPDIF2_CG 223
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#define IMX8MM_CLK_ENET_REF_CG 224
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#define IMX8MM_CLK_ENET_TIMER_CG 225
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#define IMX8MM_CLK_ENET_PHY_REF_CG 226
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#define IMX8MM_CLK_NAND_CG 227
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#define IMX8MM_CLK_QSPI_CG 228
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#define IMX8MM_CLK_USDHC1_CG 229
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#define IMX8MM_CLK_USDHC2_CG 230
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#define IMX8MM_CLK_I2C1_CG 231
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#define IMX8MM_CLK_I2C2_CG 232
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#define IMX8MM_CLK_I2C3_CG 233
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#define IMX8MM_CLK_I2C4_CG 234
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#define IMX8MM_CLK_UART1_CG 235
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#define IMX8MM_CLK_UART2_CG 236
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#define IMX8MM_CLK_UART3_CG 237
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#define IMX8MM_CLK_UART4_CG 238
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#define IMX8MM_CLK_USB_CORE_REF_CG 239
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#define IMX8MM_CLK_USB_PHY_REF_CG 240
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#define IMX8MM_CLK_ECSPI1_CG 241
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#define IMX8MM_CLK_ECSPI2_CG 242
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#define IMX8MM_CLK_PWM1_CG 243
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#define IMX8MM_CLK_PWM2_CG 244
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#define IMX8MM_CLK_PWM3_CG 245
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#define IMX8MM_CLK_PWM4_CG 246
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#define IMX8MM_CLK_GPT1_CG 247
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#define IMX8MM_CLK_WDOG_CG 248
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#define IMX8MM_CLK_WRCLK_CG 249
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#define IMX8MM_CLK_DSI_CORE_CG 250
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#define IMX8MM_CLK_DSI_PHY_REF_CG 251
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#define IMX8MM_CLK_DSI_DBI_CG 252
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#define IMX8MM_CLK_USDHC3_CG 253
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#define IMX8MM_CLK_CSI1_CORE_CG 254
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#define IMX8MM_CLK_CSI1_PHY_REF_CG 255
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#define IMX8MM_CLK_CSI1_ESC_CG 256
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#define IMX8MM_CLK_CSI2_CORE_CG 257
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#define IMX8MM_CLK_CSI2_PHY_REF_CG 258
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#define IMX8MM_CLK_CSI2_ESC_CG 259
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#define IMX8MM_CLK_PCIE2_CTRL_CG 260
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#define IMX8MM_CLK_PCIE2_PHY_CG 261
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#define IMX8MM_CLK_PCIE2_AUX_CG 262
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#define IMX8MM_CLK_ECSPI3_CG 263
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#define IMX8MM_CLK_PDM_CG 264
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#define IMX8MM_CLK_VPU_H1_CG 265
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#define IMX8MM_CLK_DRAM_ALT_PRE_DIV 266
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#define IMX8MM_CLK_DRAM_APB_PRE_DIV 267
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#define IMX8MM_CLK_VPU_G1_PRE_DIV 268
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#define IMX8MM_CLK_VPU_G2_PRE_DIV 269
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#define IMX8MM_CLK_DISP_DTRC_PRE_DIV 270
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#define IMX8MM_CLK_DISP_DC8000_PRE_DIV 271
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#define IMX8MM_CLK_PCIE1_CTRL_PRE_DIV 272
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#define IMX8MM_CLK_PCIE1_PHY_PRE_DIV 273
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#define IMX8MM_CLK_PCIE1_AUX_PRE_DIV 274
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#define IMX8MM_CLK_DC_PIXEL_PRE_DIV 275
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#define IMX8MM_CLK_LCDIF_PIXEL_PRE_DIV 276
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#define IMX8MM_CLK_SAI1_PRE_DIV 277
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#define IMX8MM_CLK_SAI2_PRE_DIV 278
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#define IMX8MM_CLK_SAI3_PRE_DIV 279
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#define IMX8MM_CLK_SAI4_PRE_DIV 280
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#define IMX8MM_CLK_SAI5_PRE_DIV 281
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#define IMX8MM_CLK_SAI6_PRE_DIV 282
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#define IMX8MM_CLK_SPDIF1_PRE_DIV 283
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#define IMX8MM_CLK_SPDIF2_PRE_DIV 284
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#define IMX8MM_CLK_ENET_REF_PRE_DIV 285
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#define IMX8MM_CLK_ENET_TIMER_PRE_DIV 286
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#define IMX8MM_CLK_ENET_PHY_REF_PRE_DIV 287
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#define IMX8MM_CLK_NAND_PRE_DIV 288
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#define IMX8MM_CLK_QSPI_PRE_DIV 289
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#define IMX8MM_CLK_USDHC1_PRE_DIV 290
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#define IMX8MM_CLK_USDHC2_PRE_DIV 291
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#define IMX8MM_CLK_I2C1_PRE_DIV 292
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#define IMX8MM_CLK_I2C2_PRE_DIV 293
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#define IMX8MM_CLK_I2C3_PRE_DIV 294
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#define IMX8MM_CLK_I2C4_PRE_DIV 295
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#define IMX8MM_CLK_UART1_PRE_DIV 296
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#define IMX8MM_CLK_UART2_PRE_DIV 297
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#define IMX8MM_CLK_UART3_PRE_DIV 298
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#define IMX8MM_CLK_UART4_PRE_DIV 299
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#define IMX8MM_CLK_USB_CORE_REF_PRE_DIV 300
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#define IMX8MM_CLK_USB_PHY_REF_PRE_DIV 301
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#define IMX8MM_CLK_ECSPI1_PRE_DIV 302
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#define IMX8MM_CLK_ECSPI2_PRE_DIV 303
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#define IMX8MM_CLK_PWM1_PRE_DIV 304
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#define IMX8MM_CLK_PWM2_PRE_DIV 305
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#define IMX8MM_CLK_PWM3_PRE_DIV 306
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#define IMX8MM_CLK_PWM4_PRE_DIV 307
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#define IMX8MM_CLK_GPT1_PRE_DIV 308
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#define IMX8MM_CLK_WDOG_PRE_DIV 309
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#define IMX8MM_CLK_WRCLK_PRE_DIV 310
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#define IMX8MM_CLK_DSI_CORE_PRE_DIV 311
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#define IMX8MM_CLK_DSI_PHY_REF_PRE_DIV 312
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#define IMX8MM_CLK_DSI_DBI_PRE_DIV 313
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#define IMX8MM_CLK_USDHC3_PRE_DIV 314
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#define IMX8MM_CLK_CSI1_CORE_PRE_DIV 315
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#define IMX8MM_CLK_CSI1_PHY_REF_PRE_DIV 316
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#define IMX8MM_CLK_CSI1_ESC_PRE_DIV 317
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#define IMX8MM_CLK_CSI2_CORE_PRE_DIV 318
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#define IMX8MM_CLK_CSI2_PHY_REF_PRE_DIV 319
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#define IMX8MM_CLK_CSI2_ESC_PRE_DIV 320
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#define IMX8MM_CLK_PCIE2_CTRL_PRE_DIV 321
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#define IMX8MM_CLK_PCIE2_PHY_PRE_DIV 322
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#define IMX8MM_CLK_PCIE2_AUX_PRE_DIV 323
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#define IMX8MM_CLK_ECSPI3_PRE_DIV 324
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#define IMX8MM_CLK_PDM_PRE_DIV 325
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#define IMX8MM_CLK_VPU_H1_PRE_DIV 326
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#define IMX8MM_CLK_DRAM_ALT_DIV 327
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#define IMX8MM_CLK_DRAM_APB_DIV 328
|
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#define IMX8MM_CLK_VPU_G1_DIV 329
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#define IMX8MM_CLK_VPU_G2_DIV 330
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#define IMX8MM_CLK_DISP_DTRC_DIV 331
|
||||
#define IMX8MM_CLK_DISP_DC8000_DIV 332
|
||||
#define IMX8MM_CLK_PCIE1_CTRL_DIV 333
|
||||
#define IMX8MM_CLK_PCIE1_PHY_DIV 334
|
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#define IMX8MM_CLK_PCIE1_AUX_DIV 335
|
||||
#define IMX8MM_CLK_DC_PIXEL_DIV 336
|
||||
#define IMX8MM_CLK_LCDIF_PIXEL_DIV 337
|
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#define IMX8MM_CLK_SAI1_DIV 338
|
||||
#define IMX8MM_CLK_SAI2_DIV 339
|
||||
#define IMX8MM_CLK_SAI3_DIV 340
|
||||
#define IMX8MM_CLK_SAI4_DIV 341
|
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#define IMX8MM_CLK_SAI5_DIV 342
|
||||
#define IMX8MM_CLK_SAI6_DIV 343
|
||||
#define IMX8MM_CLK_SPDIF1_DIV 344
|
||||
#define IMX8MM_CLK_SPDIF2_DIV 345
|
||||
#define IMX8MM_CLK_ENET_REF_DIV 346
|
||||
#define IMX8MM_CLK_ENET_TIMER_DIV 347
|
||||
#define IMX8MM_CLK_ENET_PHY_REF_DIV 348
|
||||
#define IMX8MM_CLK_NAND_DIV 349
|
||||
#define IMX8MM_CLK_QSPI_DIV 350
|
||||
#define IMX8MM_CLK_USDHC1_DIV 351
|
||||
#define IMX8MM_CLK_USDHC2_DIV 352
|
||||
#define IMX8MM_CLK_I2C1_DIV 353
|
||||
#define IMX8MM_CLK_I2C2_DIV 354
|
||||
#define IMX8MM_CLK_I2C3_DIV 355
|
||||
#define IMX8MM_CLK_I2C4_DIV 356
|
||||
#define IMX8MM_CLK_UART1_DIV 357
|
||||
#define IMX8MM_CLK_UART2_DIV 358
|
||||
#define IMX8MM_CLK_UART3_DIV 359
|
||||
#define IMX8MM_CLK_UART4_DIV 360
|
||||
#define IMX8MM_CLK_USB_CORE_REF_DIV 361
|
||||
#define IMX8MM_CLK_USB_PHY_REF_DIV 362
|
||||
#define IMX8MM_CLK_ECSPI1_DIV 363
|
||||
#define IMX8MM_CLK_ECSPI2_DIV 364
|
||||
#define IMX8MM_CLK_PWM1_DIV 365
|
||||
#define IMX8MM_CLK_PWM2_DIV 366
|
||||
#define IMX8MM_CLK_PWM3_DIV 367
|
||||
#define IMX8MM_CLK_PWM4_DIV 368
|
||||
#define IMX8MM_CLK_GPT1_DIV 369
|
||||
#define IMX8MM_CLK_WDOG_DIV 370
|
||||
#define IMX8MM_CLK_WRCLK_DIV 371
|
||||
#define IMX8MM_CLK_DSI_CORE_DIV 372
|
||||
#define IMX8MM_CLK_DSI_PHY_REF_DIV 373
|
||||
#define IMX8MM_CLK_DSI_DBI_DIV 374
|
||||
#define IMX8MM_CLK_USDHC3_DIV 375
|
||||
#define IMX8MM_CLK_CSI1_CORE_DIV 376
|
||||
#define IMX8MM_CLK_CSI1_PHY_REF_DIV 377
|
||||
#define IMX8MM_CLK_CSI1_ESC_DIV 378
|
||||
#define IMX8MM_CLK_CSI2_CORE_DIV 379
|
||||
#define IMX8MM_CLK_CSI2_PHY_REF_DIV 380
|
||||
#define IMX8MM_CLK_CSI2_ESC_DIV 381
|
||||
#define IMX8MM_CLK_PCIE2_CTRL_DIV 382
|
||||
#define IMX8MM_CLK_PCIE2_PHY_DIV 383
|
||||
#define IMX8MM_CLK_PCIE2_AUX_DIV 384
|
||||
#define IMX8MM_CLK_ECSPI3_DIV 385
|
||||
#define IMX8MM_CLK_PDM_DIV 386
|
||||
#define IMX8MM_CLK_VPU_H1_DIV 387
|
||||
#define IMX8MM_CLK_ECSPI1_ROOT 388
|
||||
#define IMX8MM_CLK_ECSPI2_ROOT 389
|
||||
#define IMX8MM_CLK_ECSPI3_ROOT 390
|
||||
#define IMX8MM_CLK_ENET1_ROOT 391
|
||||
#define IMX8MM_CLK_GPT1_ROOT 392
|
||||
#define IMX8MM_CLK_I2C1_ROOT 393
|
||||
#define IMX8MM_CLK_I2C2_ROOT 394
|
||||
#define IMX8MM_CLK_I2C3_ROOT 395
|
||||
#define IMX8MM_CLK_I2C4_ROOT 396
|
||||
#define IMX8MM_CLK_OCOTP_ROOT 397
|
||||
#define IMX8MM_CLK_PCIE1_ROOT 398
|
||||
#define IMX8MM_CLK_PWM1_ROOT 399
|
||||
#define IMX8MM_CLK_PWM2_ROOT 400
|
||||
#define IMX8MM_CLK_PWM3_ROOT 401
|
||||
#define IMX8MM_CLK_PWM4_ROOT 402
|
||||
#define IMX8MM_CLK_QSPI_ROOT 403
|
||||
#define IMX8MM_CLK_NAND_ROOT 404
|
||||
#define IMX8MM_CLK_SAI1_ROOT 405
|
||||
#define IMX8MM_CLK_SAI1_IPG 406
|
||||
#define IMX8MM_CLK_SAI2_ROOT 407
|
||||
#define IMX8MM_CLK_SAI2_IPG 408
|
||||
#define IMX8MM_CLK_SAI3_ROOT 409
|
||||
#define IMX8MM_CLK_SAI3_IPG 410
|
||||
#define IMX8MM_CLK_SAI4_ROOT 411
|
||||
#define IMX8MM_CLK_SAI4_IPG 412
|
||||
#define IMX8MM_CLK_SAI5_ROOT 413
|
||||
#define IMX8MM_CLK_SAI5_IPG 414
|
||||
#define IMX8MM_CLK_SAI6_ROOT 415
|
||||
#define IMX8MM_CLK_SAI6_IPG 416
|
||||
#define IMX8MM_CLK_UART1_ROOT 417
|
||||
#define IMX8MM_CLK_UART2_ROOT 418
|
||||
#define IMX8MM_CLK_UART3_ROOT 419
|
||||
#define IMX8MM_CLK_UART4_ROOT 420
|
||||
#define IMX8MM_CLK_USB1_CTRL_ROOT 421
|
||||
#define IMX8MM_CLK_GPU3D_ROOT 422
|
||||
#define IMX8MM_CLK_USDHC1_ROOT 423
|
||||
#define IMX8MM_CLK_USDHC2_ROOT 424
|
||||
#define IMX8MM_CLK_WDOG1_ROOT 425
|
||||
#define IMX8MM_CLK_WDOG2_ROOT 426
|
||||
#define IMX8MM_CLK_WDOG3_ROOT 427
|
||||
#define IMX8MM_CLK_VPU_G1_ROOT 428
|
||||
#define IMX8MM_CLK_GPU_ROOT 429
|
||||
#define IMX8MM_CLK_VPU_H1_ROOT 430
|
||||
#define IMX8MM_CLK_VPU_G2_ROOT 431
|
||||
#define IMX8MM_CLK_PDM_ROOT 432
|
||||
#define IMX8MM_CLK_DISP_ROOT 433
|
||||
#define IMX8MM_CLK_DISP_AXI_ROOT 434
|
||||
#define IMX8MM_CLK_DISP_APB_ROOT 435
|
||||
#define IMX8MM_CLK_DISP_RTRM_ROOT 436
|
||||
#define IMX8MM_CLK_USDHC3_ROOT 437
|
||||
#define IMX8MM_CLK_TMU_ROOT 438
|
||||
#define IMX8MM_CLK_VPU_DEC_ROOT 439
|
||||
#define IMX8MM_CLK_SDMA1_ROOT 440
|
||||
#define IMX8MM_CLK_SDMA2_ROOT 441
|
||||
#define IMX8MM_CLK_SDMA3_ROOT 442
|
||||
#define IMX8MM_CLK_GPT_3M 443
|
||||
#define IMX8MM_CLK_ARM 444
|
||||
#define IMX8MM_CLK_PDM_IPG 445
|
||||
|
||||
#define IMX8MM_CLK_END 446
|
||||
#endif
|
Loading…
Reference in New Issue